//-----------------------------------
#define CFG_K3D_CTRL_ADDR 0x0000
#define K3D_Y_STS_DONE_OFFSET 19
#define K3D_Y_STS_DONE_MASK 0x00080000
#define K3D_Y_STS_ENA_OFFSET 18
#define K3D_Y_STS_ENA_MASK 0x00040000
#define K3D_Y_OUT_ENA_OFFSET 17
#define K3D_Y_OUT_ENA_MASK 0x00020000
#define K3D_REF_CUR_SW_OFFSET 16
#define K3D_REF_CUR_SW_MASK 0x00010000
#define K3D_OUT_SW_MAX_OFFSET 8
#define K3D_OUT_SW_MAX_MASK 0x00007F00
#define K3D_MODE_OFFSET 4
#define K3D_MODE_MASK 0x00000030
#define K3D_REF_1_ENA_OFFSET 3
#define K3D_REF_1_ENA_MASK 0x00000008
#define K3D_AUTO_ENA_OFFSET 2
#define K3D_AUTO_ENA_MASK 0x00000004
#define K3D_SUM_OUT_ENA_OFFSET 1
#define K3D_SUM_OUT_ENA_MASK 0x00000002
#define K3D_FORCE_START_OFFSET 0
#define K3D_FORCE_START_MASK 0x00000001

//-----------------------------------
#define CFG_K3D_FRM_CFG_ADDR 0x0004
#define FRM_Y_MAX_OFFSET 16
#define FRM_Y_MAX_MASK 0x07FF0000
#define FRM_X_MAX_OFFSET 0
#define FRM_X_MAX_MASK 0x000007FF

//-----------------------------------
#define CFG_K3D_RFRM_INI_ADDR 0x0008
#define RFRM_Y_INI_OFFSET 16
#define RFRM_Y_INI_MASK 0x0FFF0000
#define RFRM_X_INI_OFFSET 0
#define RFRM_X_INI_MASK 0x000003FF

//-----------------------------------
#define CFG_K3D_RBLK_CFG_ADDR 0x000C
#define RFRM_X_EXD_OFFSET 20
#define RFRM_X_EXD_MASK 0x00F00000
#define RBLK_US_MAX_OFFSET 16
#define RBLK_US_MAX_MASK 0x000F0000
#define RBLK_LS_MAX_OFFSET 8
#define RBLK_LS_MAX_MASK 0x0000FF00
#define RBLK_Y_MAX_OFFSET 0
#define RBLK_Y_MAX_MASK 0x0000003F

//-----------------------------------
#define CFG_K3D_CBLK_CFG_ADDR 0x00010
#define CFRM_X_EXD_OFFSET 28
#define CFRM_X_EXD_MASK 0xF0000000
#define CFRM_Y_INI_OFFSET 16
#define CFRM_Y_INI_MASK 0x0FFF0000
#define CBLK_Y_MAX_OFFSET 0
#define CBLK_Y_MAX_MASK 0x0000003F

//-----------------------------------
#define CFG_K3D_MISC_CFG_ADDR 0x00014
#define BLK_CHK_ENA_OFFSET 31
#define BLK_CHK_ENA_MASK 0x80000000
#define BLK_SUBP_ENA_OFFSET 30
#define BLK_SUBP_ENA_MASK 0x40000000
#define BLK_START_Y_OFFSET 8
#define BLK_START_Y_MASK 0x00000F00
#define BLK_START_X_OFFSET 0
#define BLK_START_X_MASK 0x000000FF

//-----------------------------------
#define CFG_K3D_OUT_CFG_ADDR 0x00018
#define CUR_ONES_SHIFT_OFFSET 24
#define CUR_ONES_SHIFT_MASK 0x03000000
#define BLK_SUM_CFG_OFFSET 16
#define BLK_SUM_CFG_MASK 0x00FF0000
#define BLK_VEC_CFG_OFFSET 0
#define BLK_VEC_CFG_MASK 0x0000FFFF

//-----------------------------------
#define CFG_K3D_DONE_ST_ADDR 0x0001C
#define K3D_DONE_OFFSET 0
#define K3D_DONE_MASK 0x00000001

//-----------------------------------
#define CFG_K3D_DBG_ST_ADDR 0x00020
#define K3D_STS_OFFSET 0
#define K3D_STS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_K3D_FRM_ST_ADDR 0x00024
#define K3D_FRM_CNT_SOFT_RST_OFFSET 16
#define K3D_FRM_CNT_SOFT_RST_MASK 0x00010000
#define K3D_FRM_CNT_OFFSET 0
#define K3D_FRM_CNT_MASK 0x0000FFFF

//-----------------------------------
#define CFG_K3D_CAL_CFG_ADDR 0x00028
#define K3D_CAL_SHIFT_OFFSET 4
#define K3D_CAL_SHIFT_MASK 0x00000030

//-----------------------------------
#define CFG_K3D_Y_STS0_ADDR 0x0002c
#define K3D_LINE_Y_STS_ID_OFFSET 24
#define K3D_LINE_Y_STS_ID_MASK 0x7F000000
#define K3D_LINE_Y_STS_MAX_OFFSET 0
#define K3D_LINE_Y_STS_MAX_MASK 0x0003FFFF

//-----------------------------------
#define CFG_K3D_Y_STS1_ADDR 0x00030
#define K3D_PIC_Y_STS_OFFSET 0
#define K3D_PIC_Y_STS_MASK 0x01FFFFFF

//HW module read/write macro
#define K3D_READ_REG(addr) SOC_READ_REG(K3D_BASEADDR + addr)
#define K3D_WRITE_REG(addr,value) SOC_WRITE_REG(K3D_BASEADDR + addr,value)