//----------------------------------- #define CFG_TIMER0_ADDR 0x0000 #define CFG_RCG_TIMER_OFFSET 16 #define CFG_RCG_TIMER_MASK 0xFFFF0000 #define CFG_CMG_TIMER_OFFSET 0 #define CFG_CMG_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER1_ADDR 0x0004 #define CFG_RIFS_TIMER_OFFSET 16 #define CFG_RIFS_TIMER_MASK 0xFFFF0000 #define CFG_CIFS_TIMER_OFFSET 0 #define CFG_CIFS_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER2_ADDR 0x0008 #define CFG_TX_DELAY_OFFSET 22 #define CFG_TX_DELAY_MASK 0xFFC00000 #define CFG_RX_SHORT_DELAY_OFFSET 11 #define CFG_RX_SHORT_DELAY_MASK 0x003FF800 #define CFG_RX_LONG_DELAY_OFFSET 0 #define CFG_RX_LONG_DELAY_MASK 0x000007FF //----------------------------------- #define CFG_TIMER10_ADDR 0x000c #define CFG_FC_LEN_TIMER3_OFFSET 16 #define CFG_FC_LEN_TIMER3_MASK 0xFFFF0000 #define CFG_FC_LEN_TIMER2_OFFSET 0 #define CFG_FC_LEN_TIMER2_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER4_ADDR 0x0010 #define CFG_FC_LEN_TIMER1_OFFSET 16 #define CFG_FC_LEN_TIMER1_MASK 0xFFFF0000 #define CFG_FC_LEN_TIMER0_OFFSET 0 #define CFG_FC_LEN_TIMER0_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER5_ADDR 0x0014 #define CFG_TX_BIFS_TIMER_OFFSET 16 #define CFG_TX_BIFS_TIMER_MASK 0xFFFF0000 #define CFG_EIFS_TIMER_OFFSET 0 #define CFG_EIFS_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER6_ADDR 0x0018 #define CFG_AIFS_TIMER_OFFSET 16 #define CFG_AIFS_TIMER_MASK 0xFFFF0000 #define CFG_B2BIFS_TIMER_OFFSET 0 #define CFG_B2BIFS_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER7_ADDR 0x001c #define CFG_RX_BIFS_TIMER_OFFSET 16 #define CFG_RX_BIFS_TIMER_MASK 0xFFFF0000 #define CFG_PRS_SLOT_TIMER_OFFSET 0 #define CFG_PRS_SLOT_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER8_ADDR 0x0020 #define CFG_SLOT_TIMER_CAP1_OFFSET 16 #define CFG_SLOT_TIMER_CAP1_MASK 0xFFFF0000 #define CFG_SLOT_TIMER_CAP0_OFFSET 0 #define CFG_SLOT_TIMER_CAP0_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER9_ADDR 0x0024 #define CFG_DELIMITER_TIMER3_OFFSET 16 #define CFG_DELIMITER_TIMER3_MASK 0xFFFF0000 #define CFG_DELIMITER_TIMER2_OFFSET 0 #define CFG_DELIMITER_TIMER2_MASK 0x0000FFFF //----------------------------------- #define CFG_TIMER3_ADDR 0x0028 #define CFG_DELIMITER_TIMER1_OFFSET 16 #define CFG_DELIMITER_TIMER1_MASK 0xFFFF0000 #define CFG_DELIMITER_TIMER0_OFFSET 0 #define CFG_DELIMITER_TIMER0_MASK 0x0000FFFF //----------------------------------- #define CFG_SG_TIMER0_ADDR 0x002c #define CFG_SG_CIFS_TIMER_OFFSET 16 #define CFG_SG_CIFS_TIMER_MASK 0xFFFF0000 #define CFG_SG_EIFS_TIMER_OFFSET 0 #define CFG_SG_EIFS_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_SG_TIMER1_ADDR 0x0030 #define CFG_SG_RIFS_TIMER_OFFSET 0 #define CFG_SG_RIFS_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_SG_TIMER2_ADDR 0x0034 #define CFG_SG_TX_DELAY_OFFSET 0 #define CFG_SG_TX_DELAY_MASK 0x000003FF //----------------------------------- #define CFG_SG_TIMER3_ADDR 0x0038 #define CFG_SG_RX_SHORT_DELAY_OFFSET 0 #define CFG_SG_RX_SHORT_DELAY_MASK 0x000007FF //----------------------------------- #define CFG_SG_TIMER4_ADDR 0x003C #define CFG_SG_RX_LONG_DELAY_OFFSET 0 #define CFG_SG_RX_LONG_DELAY_MASK 0x000007FF //----------------------------------- #define CFG_SG_TMR_DUMMY0_ADDR 0x0040 #define CFG_SLOT_TIMER_CAP3_OFFSET 16 #define CFG_SLOT_TIMER_CAP3_MASK 0xFFFF0000 #define CFG_SLOT_TIMER_CAP2_OFFSET 0 #define CFG_SLOT_TIMER_CAP2_MASK 0x0000FFFF //----------------------------------- #define CFG_SG_TMR_DUMMY1_ADDR 0x0044 //----------------------------------- #define CFG_SG_TIMER7_ADDR 0x0048 #define CFG_SG_FC_LEN_TIMER_1_OFFSET 16 #define CFG_SG_FC_LEN_TIMER_1_MASK 0xFFFF0000 #define CFG_SG_FC_LEN_TIMER_0_OFFSET 0 #define CFG_SG_FC_LEN_TIMER_0_MASK 0x0000FFFF //----------------------------------- #define CFG_SG_TIMER8_ADDR 0x004c #define CFG_SG_FC_LEN_TIMER_3_OFFSET 16 #define CFG_SG_FC_LEN_TIMER_3_MASK 0xFFFF0000 #define CFG_SG_FC_LEN_TIMER_2_OFFSET 0 #define CFG_SG_FC_LEN_TIMER_2_MASK 0x0000FFFF //----------------------------------- #define CFG_SG_TIMER9_ADDR 0x0050 #define CFG_SG_B2BIFS_TIMER_OFFSET 0 #define CFG_SG_B2BIFS_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_SG_DUMMY1_ADDR 0x0054 //----------------------------------- #define CFG_TMR_CTRL_ADDR 0x0058 #define CFG_SG_SACK_CIFS_TIMER_OFFSET 1 #define CFG_SG_SACK_CIFS_TIMER_MASK 0x0001FFFE #define CFG_EIFS_SELECT_OFFSET 0 #define CFG_EIFS_SELECT_MASK 0x00000001 //----------------------------------- #define CFG_VCS_CNT_ADDR 0x0060 #define CFG_VCS_TRACK_USE_FC_RCV_DONE_OFFSET 17 #define CFG_VCS_TRACK_USE_FC_RCV_DONE_MASK 0x00020000 #define CFG_VCS_INIT_VALUE_OFFSET 1 #define CFG_VCS_INIT_VALUE_MASK 0x0001FFFE #define CFG_VCS_INIT_LOAD_TRIG_OFFSET 0 #define CFG_VCS_INIT_LOAD_TRIG_MASK 0x00000001 //----------------------------------- #define CFG_VCS_CTRL_ADDR 0x0064 #define CFG_CTS_VCS_UPDATE_OFFSET 4 #define CFG_CTS_VCS_UPDATE_MASK 0x00000010 #define CFG_RX_CTS_ERR_EN_OFFSET 3 #define CFG_RX_CTS_ERR_EN_MASK 0x00000008 #define CFG_RTS_CTS_VCS_MODIFY_OFFSET 2 #define CFG_RTS_CTS_VCS_MODIFY_MASK 0x00000004 #define CFG_TX_CIFS_VCS_EN_OFFSET 1 #define CFG_TX_CIFS_VCS_EN_MASK 0x00000002 #define CFG_RX_CIFS_VCS_EN_OFFSET 0 #define CFG_RX_CIFS_VCS_EN_MASK 0x00000001 //----------------------------------- #define CFG_TX_FC_CTRL_ADDR 0x0068 #define CFG_TX_FC_COOSTART_SW_OFFSET 5 #define CFG_TX_FC_COOSTART_SW_MASK 0x00000020 #define CFG_TX_FL_LEN_SW_OFFSET 4 #define CFG_TX_FL_LEN_SW_MASK 0x00000010 #define CFG_TX_FC_MFSCMD_BY_SW_OFFSET 3 #define CFG_TX_FC_MFSCMD_BY_SW_MASK 0x00000008 #define CFG_TX_FC_FL_BY_SW_OFFSET 2 #define CFG_TX_FC_FL_BY_SW_MASK 0x00000004 #define CFG_TX_FC_PBNUM_BY_SW_OFFSET 1 #define CFG_TX_FC_PBNUM_BY_SW_MASK 0x00000002 #define CFG_TX_FC_SYMBNUM_BY_SW_OFFSET 0 #define CFG_TX_FC_SYMBNUM_BY_SW_MASK 0x00000001 //----------------------------------- #define CFG_NTB_COMM_INT0_VAL_ADDR 0x006c #define CFG_NTB_COMM_INT0_VAL_OFFSET 0 #define CFG_NTB_COMM_INT0_VAL_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NTB_COMM_INT1_VAL_ADDR 0x0070 #define CFG_NTB_COMM_INT1_VAL_OFFSET 0 #define CFG_NTB_COMM_INT1_VAL_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NTB_COMM_INT2_VAL_ADDR 0x0074 #define CFG_NTB_COMM_INT2_VAL_OFFSET 0 #define CFG_NTB_COMM_INT2_VAL_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NTB_COMM_INT3_VAL_ADDR 0x0078 #define CFG_NTB_COMM_INT3_VAL_OFFSET 0 #define CFG_NTB_COMM_INT3_VAL_MASK 0xFFFFFFFF //----------------------------------- #define CFG_NTB_COMM_INT_CTRL_ADDR 0x007c #define CFG_NTB_COMM_INT3_EN_OFFSET 3 #define CFG_NTB_COMM_INT3_EN_MASK 0x00000008 #define CFG_NTB_COMM_INT2_EN_OFFSET 2 #define CFG_NTB_COMM_INT2_EN_MASK 0x00000004 #define CFG_NTB_COMM_INT1_EN_OFFSET 1 #define CFG_NTB_COMM_INT1_EN_MASK 0x00000002 #define CFG_NTB_COMM_INT0_EN_OFFSET 0 #define CFG_NTB_COMM_INT0_EN_MASK 0x00000001 //----------------------------------- #define CFG_TX_TIMEOUT_0_ADDR 0x0080 #define CFG_TX_BUF_TIMEOUT_EN_OFFSET 25 #define CFG_TX_BUF_TIMEOUT_EN_MASK 0x02000000 #define CFG_TX_BUF_TIMEOUT_OFFSET 0 #define CFG_TX_BUF_TIMEOUT_MASK 0x01FFFFFF //----------------------------------- #define CFG_TX_TIMEOUT_1_ADDR 0x0084 #define CFG_TX_PB_DESC_TIMEOUT_OFFSET 1 #define CFG_TX_PB_DESC_TIMEOUT_MASK 0x03FFFFFE #define CFG_TX_PB_DESC_TIMEOUT_EN_OFFSET 0 #define CFG_TX_PB_DESC_TIMEOUT_EN_MASK 0x00000001 //----------------------------------- #define CFG_TX_TIMEOUT_2_ADDR 0x0088 #define CFG_TX_AES_KEY_TIMEOUT_OFFSET 1 #define CFG_TX_AES_KEY_TIMEOUT_MASK 0x03FFFFFE #define CFG_TX_AES_KEY_TIMEOUT_EN_OFFSET 0 #define CFG_TX_AES_KEY_TIMEOUT_EN_MASK 0x00000001 //----------------------------------- #define CFG_PHY_TX_TIMEOUT_ADDR 0x008c #define CFG_TX_IDLE_ALIGN_EN_OFFSET 26 #define CFG_TX_IDLE_ALIGN_EN_MASK 0x04000000 #define CFG_PHY_TX_TIMEOUT_EN_OFFSET 25 #define CFG_PHY_TX_TIMEOUT_EN_MASK 0x02000000 #define CFG_PHY_TX_TIMEOUT_OFFSET 0 #define CFG_PHY_TX_TIMEOUT_MASK 0x01FFFFFF //----------------------------------- #define CFG_SG_DELI_R0B0_ADDR 0x0090 #define CFG_SG_DELIMITER_TIMER_R0B0_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R0B0_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R1B0_ADDR 0x0094 #define CFG_SG_DELIMITER_TIMER_R1B0_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R1B0_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R2B0_ADDR 0x0098 #define CFG_SG_DELIMITER_TIMER_R2B0_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R2B0_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R0B1_ADDR 0x009c #define CFG_SG_DELIMITER_TIMER_R0B1_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R0B1_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R1B1_ADDR 0x00a0 #define CFG_SG_DELIMITER_TIMER_R1B1_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R1B1_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R2B1_ADDR 0x00a4 #define CFG_SG_DELIMITER_TIMER_R2B1_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R2B1_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R0B2_ADDR 0x00a8 #define CFG_SG_DELIMITER_TIMER_R0B2_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R0B2_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R1B2_ADDR 0x00ac #define CFG_SG_DELIMITER_TIMER_R1B2_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R1B2_MASK 0x000FFFFF //----------------------------------- #define CFG_SG_DELI_R2B2_ADDR 0x00b0 #define CFG_SG_DELIMITER_TIMER_R2B2_OFFSET 0 #define CFG_SG_DELIMITER_TIMER_R2B2_MASK 0x000FFFFF //----------------------------------- #define CFG_BUG_FIX_ADDR 0x00b4 #define CFG_FIX_NTB_INT_WRAP_OFFSET 0 #define CFG_FIX_NTB_INT_WRAP_MASK 0x00000001 //----------------------------------- #define CFG_RIFS_MARGIN_ADDR 0x00b8 #define CFG_TX_RIFS_TIMER_MARGIN_OFFSET 16 #define CFG_TX_RIFS_TIMER_MARGIN_MASK 0xFFFF0000 #define CFG_RX_RIFS_TIMER_MARGIN_OFFSET 0 #define CFG_RX_RIFS_TIMER_MARGIN_MASK 0x0000FFFF //----------------------------------- #define CFG_NTB_CFG_ADDR 0x00bc #define CFG_DMA_CLK_SEL_OFFSET 1 #define CFG_DMA_CLK_SEL_MASK 0x00000002 #define CFG_MAC_CLK_OFFSET 0 #define CFG_MAC_CLK_MASK 0x00000001 //----------------------------------- #define CFG_NTB_HW_ADJUST_ADDR 0x00c0 #define CFG_FREE_TMR_CHOS_OFFSET 17 #define CFG_FREE_TMR_CHOS_MASK 0x00020000 #define CFG_NTB_ADJUST_USE_HW_OFFSET 16 #define CFG_NTB_ADJUST_USE_HW_MASK 0x00010000 #define CFG_SW_PPM_OFFSET 0 #define CFG_SW_PPM_MASK 0x0000FFFF //----------------------------------- #define CFG_RESP_TMR_CTRL_ADDR 0x00c4 #define CFG_RESP_WAIT_TIMER_CHOS_OFFSET 0 #define CFG_RESP_WAIT_TIMER_CHOS_MASK 0x00000001 //----------------------------------- #define CFG_VCS_PRS_TX_GAP_ADDR 0x00c8 #define CFG_TX_PRS_PRE_GAP_OFFSET 16 #define CFG_TX_PRS_PRE_GAP_MASK 0xFFFF0000 #define CFG_RX_PRS_DETECT_GAP_OFFSET 0 #define CFG_RX_PRS_DETECT_GAP_MASK 0x0000FFFF //----------------------------------- #define CFG_VCS_PRS_TRX_CTRL_ADDR 0x00cc #define CFG_RX_PRS_DETECT_CHOS_OFFSET 1 #define CFG_RX_PRS_DETECT_CHOS_MASK 0x00000002 #define CFG_TX_PRS_CHOS_OFFSET 0 #define CFG_TX_PRS_CHOS_MASK 0x00000001 //----------------------------------- #define CFG_PHY_TD_END_GI_OFFSET_CTRL_ADDR 0x00d0 #define CFG_GP_PB_RCV_DONE_GI_DELTA_EN_OFFSET 3 #define CFG_GP_PB_RCV_DONE_GI_DELTA_EN_MASK 0x00000008 #define CFG_GP_FC_RCV_DONE_GI_DELTA_EN_OFFSET 2 #define CFG_GP_FC_RCV_DONE_GI_DELTA_EN_MASK 0x00000004 #define CFG_SG_PB_RCV_DONE_GI_DELTA_EN_OFFSET 1 #define CFG_SG_PB_RCV_DONE_GI_DELTA_EN_MASK 0x00000002 #define CFG_SG_FC_RCV_DONE_GI_DELTA_EN_OFFSET 0 #define CFG_SG_FC_RCV_DONE_GI_DELTA_EN_MASK 0x00000001 //----------------------------------- #define CFG_PHY_SG_TD_END_GI_OFFSET_VALUE_ADDR 0x00d4 #define CFG_SG_PB_RCV_DONE_GI_DELTA_VALUE_OFFSET 16 #define CFG_SG_PB_RCV_DONE_GI_DELTA_VALUE_MASK 0xFFFF0000 #define CFG_SG_FC_RCV_DONE_GI_DELTA_VALUE_OFFSET 0 #define CFG_SG_FC_RCV_DONE_GI_DELTA_VALUE_MASK 0x0000FFFF //----------------------------------- #define CFG_PHY_GP_TD_END_GI_OFFSET_VALUE_0_ADDR 0x00d8 #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_567_OFFSET 16 #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_567_MASK 0xFFFF0000 #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_417_OFFSET 0 #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_417_MASK 0x0000FFFF //----------------------------------- #define CFG_PHY_GP_TD_END_GI_OFFSET_VALUE_1_ADDR 0x00dc #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_3534_OFFSET 16 #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_3534_MASK 0xFFFF0000 #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_TMAP_OFFSET 0 #define CFG_GP_PB_RCV_DONE_GI_DELTA_VALUE_TMAP_MASK 0x0000FFFF //----------------------------------- #define CFG_PHY_GP_TD_END_GI_OFFSET_VALUE_2_ADDR 0x00e0 #define CFG_GP_FC_RCV_DONE_GI_DELTA_VALUE_OFFSET 0 #define CFG_GP_FC_RCV_DONE_GI_DELTA_VALUE_MASK 0x0000FFFF //----------------------------------- #define CFG_RO_VCS_STS_ADDR 0x00e4 #define RO_VCS_STATUS_OFFSET 0 #define RO_VCS_STATUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RTS_BCMC_TIMER_ADDR 0x00e8 #define CFG_RTS_BCMC_EN_OFFSET 16 #define CFG_RTS_BCMC_EN_MASK 0x00010000 #define CFG_RTS_BCMC_TIMER_OFFSET 0 #define CFG_RTS_BCMC_TIMER_MASK 0x0000FFFF //----------------------------------- #define CFG_CTR_COMPENSATE_CTRL_ADDR 0x00ec #define CFG_CTS_DUR_SW_COMPENSATE_OFFSET 0 #define CFG_CTS_DUR_SW_COMPENSATE_MASK 0x00003FFF //HW module read/write macro #define RGF_TMR_READ_REG(addr) SOC_READ_REG(RGF_TMR_BASEADDR + addr) #define RGF_TMR_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_TMR_BASEADDR + addr,value)