//----------------------------------- #define CFG_AHB_RVER_ADDR 0x0000 #define AHB_RF_VER_OFFSET 0 #define AHB_RF_VER_MASK 0x0000FFFF //----------------------------------- #define CFG_AHB_REG0_ADDR 0x0004 #define FFT_SOFT_RST_OFFSET 31 #define FFT_SOFT_RST_MASK 0x80000000 #define GMAC_SOFT_RST_OFFSET 29 #define GMAC_SOFT_RST_MASK 0x20000000 #define RFPLC_MAC_SOFT_RST_OFFSET 28 #define RFPLC_MAC_SOFT_RST_MASK 0x10000000 #define RFPLC_MAC_REG_SOFT_RST_OFFSET 27 #define RFPLC_MAC_REG_SOFT_RST_MASK 0x08000000 #define RFPLC_PHY_SOFT_RST_OFFSET 26 #define RFPLC_PHY_SOFT_RST_MASK 0x04000000 #define RFPLC_PHY_REG_SOFT_RST_OFFSET 25 #define RFPLC_PHY_REG_SOFT_RST_MASK 0x02000000 #define RFPLC_ANA_SOFT_RST_OFFSET 24 #define RFPLC_ANA_SOFT_RST_MASK 0x01000000 #define FDMA_SLV_SOFT_RST_OFFSET 22 #define FDMA_SLV_SOFT_RST_MASK 0x00400000 #define RFPLL_SDM_SOFT_RST_OFFSET 21 #define RFPLL_SDM_SOFT_RST_MASK 0x00200000 #define SW_DMA2_SOFT_RST_OFFSET 20 #define SW_DMA2_SOFT_RST_MASK 0x00100000 #define MAC_SOFT_RST_OFFSET 19 #define MAC_SOFT_RST_MASK 0x00080000 #define MAC_REG_SOFT_RST_OFFSET 18 #define MAC_REG_SOFT_RST_MASK 0x00040000 #define PHY_SOFT_RST_OFFSET 17 #define PHY_SOFT_RST_MASK 0x00020000 #define PHY_REG_SOFT_RST_OFFSET 16 #define PHY_REG_SOFT_RST_MASK 0x00010000 #define PHY_ANA_SOFT_RST_OFFSET 15 #define PHY_ANA_SOFT_RST_MASK 0x00008000 #define ADA_SOFT_RST_OFFSET 14 #define ADA_SOFT_RST_MASK 0x00004000 #define SW_DMA1_SOFT_RST_OFFSET 13 #define SW_DMA1_SOFT_RST_MASK 0x00002000 #define SW_DMA0_SOFT_RST_OFFSET 12 #define SW_DMA0_SOFT_RST_MASK 0x00001000 #define EMC_SOFT_RST_OFFSET 11 #define EMC_SOFT_RST_MASK 0x00000800 #define SEC_AES_SOFT_RST_OFFSET 10 #define SEC_AES_SOFT_RST_MASK 0x00000400 #define SEC0_SOFT_RST_OFFSET 9 #define SEC0_SOFT_RST_MASK 0x00000200 #define DCACHE1_SOFT_RST_OFFSET 8 #define DCACHE1_SOFT_RST_MASK 0x00000100 #define DCACHE0_SOFT_RST_OFFSET 7 #define DCACHE0_SOFT_RST_MASK 0x00000080 #define ICACHE2_SOFT_RST_OFFSET 6 #define ICACHE2_SOFT_RST_MASK 0x00000040 #define ICACHE1_SOFT_RST_OFFSET 5 #define ICACHE1_SOFT_RST_MASK 0x00000020 #define ICACHE0_SOFT_RST_OFFSET 4 #define ICACHE0_SOFT_RST_MASK 0x00000010 #define SEC_SM4_SOFT_RST_OFFSET 3 #define SEC_SM4_SOFT_RST_MASK 0x00000008 #define CORE2_SOFT_RST_OFFSET 2 #define CORE2_SOFT_RST_MASK 0x00000004 #define CORE1_SOFT_RST_OFFSET 1 #define CORE1_SOFT_RST_MASK 0x00000002 #define CORE0_SOFT_RST_OFFSET 0 #define CORE0_SOFT_RST_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG1_ADDR 0x0008 #define FFT_EB_OFFSET 31 #define FFT_EB_MASK 0x80000000 #define USB_EB_OFFSET 30 #define USB_EB_MASK 0x40000000 #define GMAC_EB_OFFSET 29 #define GMAC_EB_MASK 0x20000000 #define RFPLC_MAC_EB_OFFSET 28 #define RFPLC_MAC_EB_MASK 0x10000000 #define RFPLC_MAC_REG_EB_OFFSET 27 #define RFPLC_MAC_REG_EB_MASK 0x08000000 #define RFPLC_PHY_EB_OFFSET 26 #define RFPLC_PHY_EB_MASK 0x04000000 #define RFPLC_PHY_REG_EB_OFFSET 25 #define RFPLC_PHY_REG_EB_MASK 0x02000000 #define RFPLC_ANA_EB_OFFSET 24 #define RFPLC_ANA_EB_MASK 0x01000000 #define FDMA_SLV_EB_OFFSET 22 #define FDMA_SLV_EB_MASK 0x00400000 #define RFPLL_SDM_EB_OFFSET 21 #define RFPLL_SDM_EB_MASK 0x00200000 #define SW_DMA2_EB_OFFSET 20 #define SW_DMA2_EB_MASK 0x00100000 #define PLC_MAC_EB_OFFSET 19 #define PLC_MAC_EB_MASK 0x00080000 #define PLC_MAC_REG_EB_OFFSET 18 #define PLC_MAC_REG_EB_MASK 0x00040000 #define PLC_PHY_EB_OFFSET 17 #define PLC_PHY_EB_MASK 0x00020000 #define PLC_PHY_REG_EB_OFFSET 16 #define PLC_PHY_REG_EB_MASK 0x00010000 #define PLC_ANA_EB_OFFSET 15 #define PLC_ANA_EB_MASK 0x00008000 #define ADA_EB_OFFSET 14 #define ADA_EB_MASK 0x00004000 #define SW_DMA1_EB_OFFSET 13 #define SW_DMA1_EB_MASK 0x00002000 #define SW_DMA0_EB_OFFSET 12 #define SW_DMA0_EB_MASK 0x00001000 #define EMC_EB_OFFSET 11 #define EMC_EB_MASK 0x00000800 #define SEC_AES_EB_OFFSET 10 #define SEC_AES_EB_MASK 0x00000400 #define SEC0_EB_OFFSET 9 #define SEC0_EB_MASK 0x00000200 #define DCACHE1_EB_OFFSET 8 #define DCACHE1_EB_MASK 0x00000100 #define DCACHE0_EB_OFFSET 7 #define DCACHE0_EB_MASK 0x00000080 #define ICACHE2_EB_OFFSET 6 #define ICACHE2_EB_MASK 0x00000040 #define ICACHE1_EB_OFFSET 5 #define ICACHE1_EB_MASK 0x00000020 #define ICACHE0_EB_OFFSET 4 #define ICACHE0_EB_MASK 0x00000010 #define SEC_SM4_EB_OFFSET 3 #define SEC_SM4_EB_MASK 0x00000008 #define CORE2_EB_OFFSET 2 #define CORE2_EB_MASK 0x00000004 #define CORE1_EB_OFFSET 1 #define CORE1_EB_MASK 0x00000002 #define CORE0_EB_OFFSET 0 #define CORE0_EB_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG2_ADDR 0x000C #define USB_SYS_SOFT_RST_OFFSET 4 #define USB_SYS_SOFT_RST_MASK 0x00000010 #define USB_MAC_SOFT_RST_OFFSET 3 #define USB_MAC_SOFT_RST_MASK 0x00000008 #define USB_MAC_UTMI_SOFT_RST_OFFSET 2 #define USB_MAC_UTMI_SOFT_RST_MASK 0x00000004 #define USB_PHY_UTMI_SOFT_RST_OFFSET 1 #define USB_PHY_UTMI_SOFT_RST_MASK 0x00000002 #define USB_PHY_SOFT_RST_OFFSET 0 #define USB_PHY_SOFT_RST_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG_LOCK_ADDR 0x001C #define AHB_REG3_UNLOCK_OFFSET 3 #define AHB_REG3_UNLOCK_MASK 0x00000008 #define AHB_REG2_UNLOCK_OFFSET 2 #define AHB_REG2_UNLOCK_MASK 0x00000004 #define AHB_REG1_UNLOCK_OFFSET 1 #define AHB_REG1_UNLOCK_MASK 0x00000002 #define AHB_REG0_UNLOCK_OFFSET 0 #define AHB_REG0_UNLOCK_MASK 0x00000001 //----------------------------------- #define CFG_CPU0_START_PC_ADDR 0x0020 #define CORE0_START_PC_OFFSET 0 #define CORE0_START_PC_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CPU1_START_PC_ADDR 0x0024 #define CORE1_START_PC_OFFSET 0 #define CORE1_START_PC_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CPU2_START_PC_ADDR 0x0028 #define CORE2_START_PC_OFFSET 0 #define CORE2_START_PC_MASK 0xFFFFFFFF //----------------------------------- #define CFG_FLASH_AES_KEY0_ADDR 0x0030 #define FLASH_AES_KEY0_OFFSET 0 #define FLASH_AES_KEY0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_FLASH_AES_KEY1_ADDR 0x0034 #define FLASH_AES_KEY1_OFFSET 0 #define FLASH_AES_KEY1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_FLASH_AES_KEY2_ADDR 0x0038 #define FLASH_AES_KEY2_OFFSET 0 #define FLASH_AES_KEY2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_FLASH_AES_KEY3_ADDR 0x003C #define FLASH_AES_KEY3_OFFSET 0 #define FLASH_AES_KEY3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_DBG_CFG_ADDR 0x0040 #define CLK_TEST_DIV_OFFSET 18 #define CLK_TEST_DIV_MASK 0x003C0000 #define CLK_TEST_SEL_OFFSET 14 #define CLK_TEST_SEL_MASK 0x0003C000 #define CHIP_DBG_BUS_SHIFT_OFFSET 8 #define CHIP_DBG_BUS_SHIFT_MASK 0x00003F00 #define CHIP_DBG_BUS_SEL1_OFFSET 4 #define CHIP_DBG_BUS_SEL1_MASK 0x000000F0 #define CHIP_DBG_BUS_SEL0_OFFSET 0 #define CHIP_DBG_BUS_SEL0_MASK 0x0000000F //----------------------------------- #define CFG_AHB_DBG_BUS_ADDR 0x0044 #define CHIP_STATUS_OUT32_OFFSET 0 #define CHIP_STATUS_OUT32_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_CORE0_CFG0_ADDR 0x0048 #define CORE0_WFI_CLK_ENA_OFFSET 10 #define CORE0_WFI_CLK_ENA_MASK 0x00000400 #define CORE0_D_EXP_MASK_OFFSET 4 #define CORE0_D_EXP_MASK_MASK 0x000003F0 #define CORE0_I_EXP_MASK_OFFSET 3 #define CORE0_I_EXP_MASK_MASK 0x00000008 #define CORE0_SIMD_EB_OFFSET 2 #define CORE0_SIMD_EB_MASK 0x00000004 #define CORE0_BTB_EB_OFFSET 1 #define CORE0_BTB_EB_MASK 0x00000002 #define CORE0_BIU_PATCH_EN_OFFSET 0 #define CORE0_BIU_PATCH_EN_MASK 0x00000001 //----------------------------------- #define CFG_AHB_CORE0_CFG1_ADDR 0x004C #define CORE0_D_ACCESS_EN_OFFSET 16 #define CORE0_D_ACCESS_EN_MASK 0xFFFF0000 #define CORE0_I_ACCESS_EN_OFFSET 0 #define CORE0_I_ACCESS_EN_MASK 0x0000FFFF //----------------------------------- #define CFG_AHB_CORE1_CFG0_ADDR 0x0050 #define CORE1_WFI_CLK_ENA_OFFSET 10 #define CORE1_WFI_CLK_ENA_MASK 0x00000400 #define CORE1_D_EXP_MASK_OFFSET 4 #define CORE1_D_EXP_MASK_MASK 0x000003F0 #define CORE1_I_EXP_MASK_OFFSET 3 #define CORE1_I_EXP_MASK_MASK 0x00000008 #define CORE1_SIMD_EB_OFFSET 2 #define CORE1_SIMD_EB_MASK 0x00000004 #define CORE1_BTB_EB_OFFSET 1 #define CORE1_BTB_EB_MASK 0x00000002 #define CORE1_BIU_PATCH_EN_OFFSET 0 #define CORE1_BIU_PATCH_EN_MASK 0x00000001 //----------------------------------- #define CFG_AHB_CORE1_CFG1_ADDR 0x0054 #define CORE1_D_ACCESS_EN_OFFSET 16 #define CORE1_D_ACCESS_EN_MASK 0xFFFF0000 #define CORE1_I_ACCESS_EN_OFFSET 0 #define CORE1_I_ACCESS_EN_MASK 0x0000FFFF //----------------------------------- #define CFG_AHB_CORE2_CFG0_ADDR 0x0058 #define CORE2_WFI_CLK_ENA_OFFSET 10 #define CORE2_WFI_CLK_ENA_MASK 0x00000400 #define CORE2_D_EXP_MASK_OFFSET 4 #define CORE2_D_EXP_MASK_MASK 0x000003F0 #define CORE2_I_EXP_MASK_OFFSET 3 #define CORE2_I_EXP_MASK_MASK 0x00000008 #define CORE2_SIMD_EB_OFFSET 2 #define CORE2_SIMD_EB_MASK 0x00000004 #define CORE2_BTB_EB_OFFSET 1 #define CORE2_BTB_EB_MASK 0x00000002 #define CORE2_BIU_PATCH_EN_OFFSET 0 #define CORE2_BIU_PATCH_EN_MASK 0x00000001 //----------------------------------- #define CFG_AHB_CORE2_CFG1_ADDR 0x005c #define CORE2_D_ACCESS_EN_OFFSET 16 #define CORE2_D_ACCESS_EN_MASK 0xFFFF0000 #define CORE2_I_ACCESS_EN_OFFSET 0 #define CORE2_I_ACCESS_EN_MASK 0x0000FFFF //----------------------------------- #define CFG_AHB_AP_CLK_CFG_ADDR 0x0060 #define D_MDLL_COUT_FRC_EN_OFFSET 22 #define D_MDLL_COUT_FRC_EN_MASK 0x00400000 #define D_MDLL_ENLOOP_OFFSET 21 #define D_MDLL_ENLOOP_MASK 0x00200000 #define D_MDLL_EN_DIGCLK_OFFSET 20 #define D_MDLL_EN_DIGCLK_MASK 0x00100000 #define CLK_APB_FORCE_ON_OFFSET 19 #define CLK_APB_FORCE_ON_MASK 0x00080000 #define CLK_AHB_FORCE_ON_OFFSET 18 #define CLK_AHB_FORCE_ON_MASK 0x00040000 #define PLC_CLK_GEN_FORCE_ON_OFFSET 17 #define PLC_CLK_GEN_FORCE_ON_MASK 0x00020000 #define CLK_RFPLC_WAFE_MCLK_SEL_OFFSET 16 #define CLK_RFPLC_WAFE_MCLK_SEL_MASK 0x00010000 #define CLK_SOC_FORCE_OFF_OFFSET 15 #define CLK_SOC_FORCE_OFF_MASK 0x00008000 #define CLK_PTP_REF_GMAC_DIV_OFFSET 13 #define CLK_PTP_REF_GMAC_DIV_MASK 0x00006000 #define CLK_RMII_GMAC_SEL_OFFSET 12 #define CLK_RMII_GMAC_SEL_MASK 0x00001000 #define CLK_APB_SEL_OFFSET 9 #define CLK_APB_SEL_MASK 0x00000200 #define CLK_APB_DIV_OFFSET 6 #define CLK_APB_DIV_MASK 0x000001C0 #define CLK_AHB_SEL_OFFSET 2 #define CLK_AHB_SEL_MASK 0x0000000C //----------------------------------- #define CFG_AHB_ANA_PIN_CFG_ADDR 0x0064 #define EN_DIGPAD1_OFFSET 1 #define EN_DIGPAD1_MASK 0x00000002 #define EN_DIGPAD0_OFFSET 0 #define EN_DIGPAD0_MASK 0x00000001 //----------------------------------- #define CFG_AHB_FDMA_SLV_CFG_ADDR 0x0068 #define FDMA_SLV_RST_CPU_EN_OFFSET 0 #define FDMA_SLV_RST_CPU_EN_MASK 0x00000001 //----------------------------------- #define CFG_EMC_PHY_CFG_ADDR 0x006c #define SFC_IO_FROM_GPIO_MTX_OFFSET 26 #define SFC_IO_FROM_GPIO_MTX_MASK 0x04000000 #define SFC_SO_BAK_PAD_ENA_OFFSET 25 #define SFC_SO_BAK_PAD_ENA_MASK 0x02000000 #define SFC_SI_BAK_PAD_ENA_OFFSET 24 #define SFC_SI_BAK_PAD_ENA_MASK 0x01000000 #define SMC_CLK_PAD_SEL_OFFSET 21 #define SMC_CLK_PAD_SEL_MASK 0x00E00000 #define SFC_CLK_PAD_SEL_OFFSET 17 #define SFC_CLK_PAD_SEL_MASK 0x001E0000 #define SMC_PHY_ENA_OFFSET 9 #define SMC_PHY_ENA_MASK 0x0001FE00 #define SFC_PHY_ENA_OFFSET 0 #define SFC_PHY_ENA_MASK 0x000001FF //----------------------------------- #define CFG_SCRATCH0_ADDR 0x70 #define SCRATCH0_OFFSET 0 #define SCRATCH0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SCRATCH1_ADDR 0x74 #define SCRATCH1_OFFSET 0 #define SCRATCH1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SCRATCH2_ADDR 0x78 #define SCRATCH2_OFFSET 0 #define SCRATCH2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SCRATCH3_ADDR 0x7c #define SCRATCH3_OFFSET 0 #define SCRATCH3_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SCRATCH4_ADDR 0x80 #define SCRATCH4_OFFSET 0 #define SCRATCH4_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SCRATCH5_ADDR 0x84 #define SCRATCH5_OFFSET 0 #define SCRATCH5_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE0_RNMI_INT_VECTOR_ADDR 0x90 #define CORE0_RNMI_INT_VECTOR_OFFSET 0 #define CORE0_RNMI_INT_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE0_RNIM_EXP_VECTOR_ADDR 0x94 #define CORE0_RNMI_EXP_VECTOR_OFFSET 0 #define CORE0_RNMI_EXP_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE0_UNMI_INT_VECTOR_ADDR 0x98 #define CORE0_UNMI_INT_VECTOR_OFFSET 0 #define CORE0_UNMI_INT_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE0_UNIM_EXP_VECTOR_ADDR 0x9c #define CORE0_UNMI_EXP_VECTOR_OFFSET 0 #define CORE0_UNMI_EXP_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE1_RNMI_INT_VECTOR_ADDR 0xA0 #define CORE1_RNMI_INT_VECTOR_OFFSET 0 #define CORE1_RNMI_INT_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE1_RNIM_EXP_VECTOR_ADDR 0xA4 #define CORE1_RNMI_EXP_VECTOR_OFFSET 0 #define CORE1_RNMI_EXP_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE1_UNMI_INT_VECTOR_ADDR 0xA8 #define CORE1_UNMI_INT_VECTOR_OFFSET 0 #define CORE1_UNMI_INT_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE1_UNIM_EXP_VECTOR_ADDR 0xAc #define CORE1_UNMI_EXP_VECTOR_OFFSET 0 #define CORE1_UNMI_EXP_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE2_RNMI_INT_VECTOR_ADDR 0xB0 #define CORE2_RNMI_INT_VECTOR_OFFSET 0 #define CORE2_RNMI_INT_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE2_RNIM_EXP_VECTOR_ADDR 0xB4 #define CORE2_RNMI_EXP_VECTOR_OFFSET 0 #define CORE2_RNMI_EXP_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE2_UNMI_INT_VECTOR_ADDR 0xB8 #define CORE2_UNMI_INT_VECTOR_OFFSET 0 #define CORE2_UNMI_INT_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CORE2_UNIM_EXP_VECTOR_ADDR 0xBc #define CORE2_UNMI_EXP_VECTOR_OFFSET 0 #define CORE2_UNMI_EXP_VECTOR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DIG_TOP_ADA_DUMP_MUX_ADDR 0x0100 #define SW_DIG_TOP_ADA_DUMP_SEL_OFFSET 0 #define SW_DIG_TOP_ADA_DUMP_SEL_MASK 0x0000000F //----------------------------------- #define CFG_DCACHE1_MEM_CTRL_ADDR 0x104 #define DCACHE1_RAM_MODE_OFFSET 0 #define DCACHE1_RAM_MODE_MASK 0x00000001 //----------------------------------- #define CFG_MEM_CFG_ADDR 0x0108 #define MEM_PARA_RELOAD_SW_OFFSET 25 #define MEM_PARA_RELOAD_SW_MASK 0x02000000 #define MEM_PARA_RELOAD_SEL_OFFSET 24 #define MEM_PARA_RELOAD_SEL_MASK 0x01000000 #define ROM_TEST1_OFFSET 21 #define ROM_TEST1_MASK 0x00200000 #define ROM_RM_OFFSET 17 #define ROM_RM_MASK 0x001E0000 #define ROM_RME_OFFSET 16 #define ROM_RME_MASK 0x00010000 #define RAM_TEST1_OFFSET 13 #define RAM_TEST1_MASK 0x00002000 #define RAM_RM_OFFSET 9 #define RAM_RM_MASK 0x00001E00 #define RAM_RME_OFFSET 8 #define RAM_RME_MASK 0x00000100 #define RAM_RA_OFFSET 6 #define RAM_RA_MASK 0x000000C0 #define RAM_WA_OFFSET 3 #define RAM_WA_MASK 0x00000038 #define RAM_WPULSE_OFFSET 0 #define RAM_WPULSE_MASK 0x00000007 //----------------------------------- #define CFG_AHB_MISC_CLK_CFG_ADDR 0x0110 #define CLK_EFUSE_DIV_OFFSET 24 #define CLK_EFUSE_DIV_MASK 0x3F000000 #define CLK_PWM_SEL_OFFSET 20 #define CLK_PWM_SEL_MASK 0x00100000 #define CLK_32K_SEL_OFFSET 19 #define CLK_32K_SEL_MASK 0x00080000 #define CLK_32K_DIV_OFFSET 8 #define CLK_32K_DIV_MASK 0x0007FF00 #define SW_SYSPLL_CLK_EN_OFFSET 5 #define SW_SYSPLL_CLK_EN_MASK 0x00000020 #define CLK_SOC_DIV_OFFSET 0 #define CLK_SOC_DIV_MASK 0x0000001F //----------------------------------- #define CFG_CHIP_PAD_STRAP_STATUS0_ADDR 0x0114 #define CHIP_PAD_STRAP_STATUS0_OFFSET 0 #define CHIP_PAD_STRAP_STATUS0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CHIP_PAD_STRAP_STATUS1_ADDR 0x0118 #define CHIP_PAD_STRAP_STATUS1_OFFSET 0 #define CHIP_PAD_STRAP_STATUS1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CHIP_PAD_STRAP_STATUS2_ADDR 0x011C #define CHIP_PAD_STRAP_STATUS2_OFFSET 0 #define CHIP_PAD_STRAP_STATUS2_MASK 0xFFFFFFFF //----------------------------------- #define CFG_PLC_RFPLC_CLK_CFG_ADDR 0x0120 #define SW_PLC_MST_BRG_F2S_OFFSET 13 #define SW_PLC_MST_BRG_F2S_MASK 0x00002000 #define SW_PLC_SLV_BRG_F2S_OFFSET 12 #define SW_PLC_SLV_BRG_F2S_MASK 0x00001000 #define SW_RFPLC_MST_BRG_F2S_OFFSET 11 #define SW_RFPLC_MST_BRG_F2S_MASK 0x00000800 #define SW_RFPLC_SLV_BRG_F2S_OFFSET 10 #define SW_RFPLC_SLV_BRG_F2S_MASK 0x00000400 #define SW_RFPLC_MST_BRG_ASYNC_OFFSET 9 #define SW_RFPLC_MST_BRG_ASYNC_MASK 0x00000200 #define SW_RFPLC_SLV_BRG_ASYNC_OFFSET 8 #define SW_RFPLC_SLV_BRG_ASYNC_MASK 0x00000100 #define PLC_MST_BRG_F2S_OVER_ON_OFFSET 5 #define PLC_MST_BRG_F2S_OVER_ON_MASK 0x00000020 #define PLC_SLV_BRG_F2S_OVER_ON_OFFSET 4 #define PLC_SLV_BRG_F2S_OVER_ON_MASK 0x00000010 #define RFPLC_MST_BRG_F2S_OVER_ON_OFFSET 3 #define RFPLC_MST_BRG_F2S_OVER_ON_MASK 0x00000008 #define RFPLC_SLV_BRG_F2S_OVER_ON_OFFSET 2 #define RFPLC_SLV_BRG_F2S_OVER_ON_MASK 0x00000004 #define RFPLC_MST_BRG_ASYNC_OVER_ON_OFFSET 1 #define RFPLC_MST_BRG_ASYNC_OVER_ON_MASK 0x00000002 #define RFPLC_SLV_BRG_ASYNC_OVER_ON_OFFSET 0 #define RFPLC_SLV_BRG_ASYNC_OVER_ON_MASK 0x00000001 //----------------------------------- #define CFG_AHB_ROM_PATCH_MAGIC_ADDR 0x0124 #define ROM_PATCH_MAGIC_NUM_OFFSET 0 #define ROM_PATCH_MAGIC_NUM_MASK 0x000000FF //----------------------------------- #define CFG_AHB_ROM_PATCH0_INDEX_ADDR 0x0128 #define ROM_PATCH0_VLD_FLAG_OFFSET 20 #define ROM_PATCH0_VLD_FLAG_MASK 0x00100000 #define ROM_PATCH0_INDEX_OFFSET 0 #define ROM_PATCH0_INDEX_MASK 0x000FFFFF //----------------------------------- #define CFG_AHB_ROM_PATCH1_INDEX_ADDR 0x012C #define ROM_PATCH1_VLD_FLAG_OFFSET 20 #define ROM_PATCH1_VLD_FLAG_MASK 0x00100000 #define ROM_PATCH1_INDEX_OFFSET 0 #define ROM_PATCH1_INDEX_MASK 0x000FFFFF //----------------------------------- #define CFG_AHB_ROM_PATCH2_INDEX_ADDR 0x0130 #define ROM_PATCH2_VLD_FLAG_OFFSET 20 #define ROM_PATCH2_VLD_FLAG_MASK 0x00100000 #define ROM_PATCH2_INDEX_OFFSET 0 #define ROM_PATCH2_INDEX_MASK 0x000FFFFF //----------------------------------- #define CFG_AHB_ROM_PATCH3_INDEX_ADDR 0x0134 #define ROM_PATCH3_VLD_FLAG_OFFSET 20 #define ROM_PATCH3_VLD_FLAG_MASK 0x00100000 #define ROM_PATCH3_INDEX_OFFSET 0 #define ROM_PATCH3_INDEX_MASK 0x000FFFFF //----------------------------------- #define CFG_AHB_ROM_PATCH0_CONTENT_ADDR 0x0138 #define ROM_PATCH0_CONTENT_OFFSET 0 #define ROM_PATCH0_CONTENT_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_ROM_PATCH1_CONTENT_ADDR 0x013C #define ROM_PATCH1_CONTENT_OFFSET 0 #define ROM_PATCH1_CONTENT_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_ROM_PATCH2_CONTENT_ADDR 0x0140 #define ROM_PATCH2_CONTENT_OFFSET 0 #define ROM_PATCH2_CONTENT_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_ROM_PATCH3_CONTENT_ADDR 0x0144 #define ROM_PATCH3_CONTENT_OFFSET 0 #define ROM_PATCH3_CONTENT_MASK 0xFFFFFFFF //HW module read/write macro #define AHB_REG_LITE0_READ_REG(addr) SOC_READ_REG(AHB_REG_LITE_BASEADDR + addr) #define AHB_REG_LITE0_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_REG_LITE_BASEADDR + addr,value) #define AHB_REG_LITE1_READ_REG(addr) SOC_READ_REG(AHB_REG_LITE_SET_BASEADDR + addr) #define AHB_REG_LITE1_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_REG_LITE_SET_BASEADDR + addr,value) #define AHB_REG_LITE2_READ_REG(addr) SOC_READ_REG(AHB_REG_LITE_CLR_BASEADDR + addr) #define AHB_REG_LITE2_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_REG_LITE_CLR_BASEADDR + addr,value)