//-----------------------------------
#define CFG_I2C_RVER_ADDR 0x0000
#define I2C_RF_VER_OFFSET 0
#define I2C_RF_VER_MASK 0x000000FF

//-----------------------------------
#define CFG_I2C_MODE_ADDR 0x0004
#define I2C_TRANS_STOP_OFFSET 5
#define I2C_TRANS_STOP_MASK 0x00000020
#define I2C_READ_MODE_OFFSET 4
#define I2C_READ_MODE_MASK 0x00000010
#define I2C_BUSRT_MODE_OFFSET 2
#define I2C_BUSRT_MODE_MASK 0x0000000C
#define IIC_RD_OFFSET 1
#define IIC_RD_MASK 0x00000002
#define IIC_WR_OFFSET 0
#define IIC_WR_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_STATUS_ADDR 0x0008
#define TX_RD_PTR_OFFSET 21
#define TX_RD_PTR_MASK 0x01E00000
#define TX_WR_PTR_OFFSET 17
#define TX_WR_PTR_MASK 0x001E0000
#define RX_RD_PTR_OFFSET 13
#define RX_RD_PTR_MASK 0x0001E000
#define RX_WR_PTR_OFFSET 9
#define RX_WR_PTR_MASK 0x00001E00
#define NACK_ST_OFFSET 6
#define NACK_ST_MASK 0x000001C0
#define I2C_INT_OFFSET 5
#define I2C_INT_MASK 0x00000020
#define NACK_INT_OFFSET 4
#define NACK_INT_MASK 0x00000010
#define RX_FIFO_FULL_OFFSET 3
#define RX_FIFO_FULL_MASK 0x00000008
#define RX_FIFO_EMPTY_OFFSET 2
#define RX_FIFO_EMPTY_MASK 0x00000004
#define TX_FIFO_FULL_OFFSET 1
#define TX_FIFO_FULL_MASK 0x00000002
#define TX_FIFO_EMPTY_OFFSET 0
#define TX_FIFO_EMPTY_MASK 0x00000001

//-----------------------------------
#define CFG_CLOCK_DIV_ADDR 0x000C
#define CLK_DIV_OFFSET 0
#define CLK_DIV_MASK 0x00000FFF

//-----------------------------------
#define CFG_WAIT_NACK_MAX_ADDR 0x0010
#define WAIT_NACK_MAX_OFFSET 0
#define WAIT_NACK_MAX_MASK 0x00003FFF

//-----------------------------------
#define CFG_CLR_INT_ADDR 0x0014
#define I2C_TXFIFO_CLR_OFFSET 3
#define I2C_TXFIFO_CLR_MASK 0x00000008
#define I2C_RXFIFO_CLR_OFFSET 2
#define I2C_RXFIFO_CLR_MASK 0x00000004
#define I2C_INT_CLR_OFFSET 1
#define I2C_INT_CLR_MASK 0x00000002
#define NACK_INT_CLR_OFFSET 0
#define NACK_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_DATA_NUM_CONF_ADDR 0x0018
#define SEND_NUM_OFFSET 8
#define SEND_NUM_MASK 0x0000FF00
#define REC_NUM_OFFSET 0
#define REC_NUM_MASK 0x000000FF

//-----------------------------------
#define CFG_START_ADDR 0x001C
#define I2C_START_OFFSET 0
#define I2C_START_MASK 0x00000001

//-----------------------------------
#define CFG_RX_FIFO_DATA_ADDR 0x0020
#define RX_FIFO_RDATA_OFFSET 0
#define RX_FIFO_RDATA_MASK 0x000000FF

//-----------------------------------
#define CFG_I2C_TX_FIFO_WDATA_ADDR 0x0024
#define TX_FIFO_WDATA_OFFSET 0
#define TX_FIFO_WDATA_MASK 0x000000FF

//-----------------------------------
#define CFG_I2C_RX_FIFO_RDATA_ADDR 0x0028
#define RX_FIFO_WE_OFFSET 0
#define RX_FIFO_WE_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_MASTER_FIFO_CFG_ADDR 0x002C
#define RX_FIFO_DATA_NUM_OFFSET 15
#define RX_FIFO_DATA_NUM_MASK 0x000F8000
#define TX_FIFO_DATA_NUM_OFFSET 10
#define TX_FIFO_DATA_NUM_MASK 0x00007C00
#define I2C_RXFIFO_THRS_OFFSET 5
#define I2C_RXFIFO_THRS_MASK 0x000003E0
#define I2C_TXFIFO_THRS_OFFSET 0
#define I2C_TXFIFO_THRS_MASK 0x0000001F

//-----------------------------------
#define CFG_I2C_MASTER_INT_RAW_ADDR 0x0030
#define I2C_M_NACK_INT_RAW_OFFSET 5
#define I2C_M_NACK_INT_RAW_MASK 0x00000020
#define I2C_M_TX_EMP_INT_RAW_OFFSET 4
#define I2C_M_TX_EMP_INT_RAW_MASK 0x00000010
#define I2C_M_RX_FULL_INT_RAW_OFFSET 3
#define I2C_M_RX_FULL_INT_RAW_MASK 0x00000008
#define I2C_M_TX_UNDERFLOW_INT_RAW_OFFSET 2
#define I2C_M_TX_UNDERFLOW_INT_RAW_MASK 0x00000004
#define I2C_M_RX_OVERFLOW_INT_RAW_OFFSET 1
#define I2C_M_RX_OVERFLOW_INT_RAW_MASK 0x00000002
#define I2C_M_DONE_INT_RAW_OFFSET 0
#define I2C_M_DONE_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_MASTER_INT_ST_ADDR 0x0034
#define I2C_M_NACK_INT_ST_OFFSET 5
#define I2C_M_NACK_INT_ST_MASK 0x00000020
#define I2C_M_TX_EMP_INT_ST_OFFSET 4
#define I2C_M_TX_EMP_INT_ST_MASK 0x00000010
#define I2C_M_RX_FULL_INT_ST_OFFSET 3
#define I2C_M_RX_FULL_INT_ST_MASK 0x00000008
#define I2C_M_TX_UNDERFLOW_INT_ST_OFFSET 2
#define I2C_M_TX_UNDERFLOW_INT_ST_MASK 0x00000004
#define I2C_M_RX_OVERFLOW_INT_ST_OFFSET 1
#define I2C_M_RX_OVERFLOW_INT_ST_MASK 0x00000002
#define I2C_M_DONE_INT_ST_OFFSET 0
#define I2C_M_DONE_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_MASTER_INT_ENA_ADDR 0x0038
#define I2C_M_NACK_INT_ENA_OFFSET 5
#define I2C_M_NACK_INT_ENA_MASK 0x00000020
#define I2C_M_TX_EMP_INT_ENA_OFFSET 4
#define I2C_M_TX_EMP_INT_ENA_MASK 0x00000010
#define I2C_M_RX_FULL_INT_ENA_OFFSET 3
#define I2C_M_RX_FULL_INT_ENA_MASK 0x00000008
#define I2C_M_TX_UNDERFLOW_INT_ENA_OFFSET 2
#define I2C_M_TX_UNDERFLOW_INT_ENA_MASK 0x00000004
#define I2C_M_RX_OVERFLOW_INT_ENA_OFFSET 1
#define I2C_M_RX_OVERFLOW_INT_ENA_MASK 0x00000002
#define I2C_M_DONE_INT_ENA_OFFSET 0
#define I2C_M_DONE_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_MASTER_INT_CLR_ADDR 0x003C
#define I2C_M_NACK_INT_CLR_OFFSET 5
#define I2C_M_NACK_INT_CLR_MASK 0x00000020
#define I2C_M_TX_EMP_INT_CLR_OFFSET 4
#define I2C_M_TX_EMP_INT_CLR_MASK 0x00000010
#define I2C_M_RX_FULL_INT_CLR_OFFSET 3
#define I2C_M_RX_FULL_INT_CLR_MASK 0x00000008
#define I2C_M_TX_UNDERFLOW_INT_CLR_OFFSET 2
#define I2C_M_TX_UNDERFLOW_INT_CLR_MASK 0x00000004
#define I2C_M_RX_OVERFLOW_INT_CLR_OFFSET 1
#define I2C_M_RX_OVERFLOW_INT_CLR_MASK 0x00000002
#define I2C_M_DONE_INT_CLR_OFFSET 0
#define I2C_M_DONE_INT_CLR_MASK 0x00000001

//HW module read/write macro
#define I2C_MASTER0_READ_REG(addr) SOC_READ_REG(I2C_M0_REG_BASEADDR + addr)
#define I2C_MASTER0_WRITE_REG(addr,value) SOC_WRITE_REG(I2C_M0_REG_BASEADDR + addr,value)

#define I2C_MASTER1_READ_REG(addr) SOC_READ_REG(I2C_M1_REG_BASEADDR + addr)
#define I2C_MASTER1_WRITE_REG(addr,value) SOC_WRITE_REG(I2C_M1_REG_BASEADDR + addr,value)

#define I2C_MASTER2_READ_REG(addr) SOC_READ_REG(I2C_M2_REG_BASEADDR + addr)
#define I2C_MASTER2_WRITE_REG(addr,value) SOC_WRITE_REG(I2C_M2_REG_BASEADDR + addr,value)

#define I2C_MASTER3_READ_REG(addr) SOC_READ_REG(I2C_M3_REG_BASEADDR + addr)
#define I2C_MASTER3_WRITE_REG(addr,value) SOC_WRITE_REG(I2C_M3_REG_BASEADDR + addr,value)