#source [file join [file dirname [string map {"\\" "/"} [info script]]] openocd_jtag.cfg] source [find /opt/riscv/share/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg] adapter_khz 1000 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 gdb_port 3333 proc disable_watchdog {} { echo "Disabling watchdog..." halt mww 0x40040080 0x57444750 mww 0x40040008 0 mww 0x40040080 0 mww 0x40041080 0x57444750 mww 0x40041008 0 mww 0x40041080 0 mww 0x40042080 0x57444750 mww 0x40042008 0 mww 0x40042080 0 # mww 0x012c0080 0x57444750 # mww 0x012c0008 0 # mww 0x012c0080 0 # mww 0x108C0080 0x57444750 # mww 0x108C0008 0 # mww 0x108C0080 0 # mww 0x10B00080 0x57444750 # mww 0x10B00008 0 # mww 0x10B00080 0 # mww 0x208C0080 0x57444750 # mww 0x208C0008 0 # mww 0x208C0080 0 # mww 0x0194F080 0x57444750 # mww 0x0194F008 0 # mww 0x0194F080 0 } # mrw: "memory read word", returns value of $reg proc mrw {reg} { set value "" mem2array value 32 $reg 1 return $value(0) } # core 0 set _TARGETNAME0 $_CHIPNAME.cpu0 target create $_TARGETNAME0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 $_TARGETNAME0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 $_TARGETNAME0 configure -event reset-init disable_watchdog $_TARGETNAME0 configure -event examine-end { echo "start core 1 & core 2" halt # core 1 & 2 clk # mww 0x10800010 0x00000900 mww 0x50019400 0x00000006 # core 1 start pc mww 0x10030000 0x0000006F mww 0x50019024 0x10030000 # core 2 start pc mww 0x10060000 0x0000006F mww 0x50019028 0x10060000 # core 1 enable mww 0x50019004 [expr [mrw 0x50019004] & 0x2] # core 2 enable mww 0x50019004 [expr [mrw 0x50019004] & 0x4] # # core 1 & 2 clk # mww 0x10800010 0x00000900 # # # core 1 start pc # mww 0x1023EFF0 0x0000006F # mww 0x10800040 0x1023EFF0 # # core 2 start pc # mww 0x1023EFF4 0x0000006F # mww 0x10800044 0x1023EFF4 # # core 1 enable # mww 0x01200160 [expr [mrw 0x01200160] | 0x20] # # core 2 enable # mww 0x01200160 [expr [mrw 0x01200160] | 0x40] sleep 100 } # core 1 set _TARGETNAME1 $_CHIPNAME.cpu1 target create $_TARGETNAME1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 $_TARGETNAME1 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 $_TARGETNAME1 configure -event examine-end halt # core 2 set _TARGETNAME2 $_CHIPNAME.cpu2 target create $_TARGETNAME2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 $_TARGETNAME2 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 $_TARGETNAME2 configure -event examine-end halt