//-----------------------------------
#define CFG_APB_RVER_ADDR 0x0000
#define APB_RF_VER_OFFSET 0
#define APB_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_APB_GLB_GEN0_ADDR 0x0004
#define CAN_EB_OFFSET 14
#define CAN_EB_MASK 0x00004000
#define WDG_EB_OFFSET 13
#define WDG_EB_MASK 0x00002000
#define STMR_EB_OFFSET 12
#define STMR_EB_MASK 0x00001000
#define SPI_S0_EB_OFFSET 11
#define SPI_S0_EB_MASK 0x00000800
#define SPI_M1_EB_OFFSET 10
#define SPI_M1_EB_MASK 0x00000400
#define SPI_M0_EB_OFFSET 9
#define SPI_M0_EB_MASK 0x00000200
#define CLKEB_OFFSET 8
#define CLKEB_MASK 0x00000100
#define GTMR1_EB_OFFSET 7
#define GTMR1_EB_MASK 0x00000080
#define PINEB_OFFSET 6
#define PINEB_MASK 0x00000040
#define UART_2_EB_OFFSET 5
#define UART_2_EB_MASK 0x00000020
#define UART_1_EB_OFFSET 4
#define UART_1_EB_MASK 0x00000010
#define INTC_EB_OFFSET 3
#define INTC_EB_MASK 0x00000008
#define GTMR0_EB_OFFSET 2
#define GTMR0_EB_MASK 0x00000004
#define GPIO_EB_OFFSET 1
#define GPIO_EB_MASK 0x00000002
#define UART_0_EB_OFFSET 0
#define UART_0_EB_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GLB_GRST0_ADDR 0x0008
#define CAN_SOFT_RST_OFFSET 14
#define CAN_SOFT_RST_MASK 0x00004000
#define WDG_SOFT_RST_OFFSET 13
#define WDG_SOFT_RST_MASK 0x00002000
#define STMR_SOFT_RST_OFFSET 12
#define STMR_SOFT_RST_MASK 0x00001000
#define SPI_S0_SOFT_RST_OFFSET 11
#define SPI_S0_SOFT_RST_MASK 0x00000800
#define SPI_M1_SOFT_RST_OFFSET 10
#define SPI_M1_SOFT_RST_MASK 0x00000400
#define SPI_M0_SOFT_RST_OFFSET 9
#define SPI_M0_SOFT_RST_MASK 0x00000200
#define CLKSOFT_RST_OFFSET 8
#define CLKSOFT_RST_MASK 0x00000100
#define GTMR1_SOFT_RST_OFFSET 7
#define GTMR1_SOFT_RST_MASK 0x00000080
#define PINSOFT_RST_OFFSET 6
#define PINSOFT_RST_MASK 0x00000040
#define UART_2_SOFT_RST_OFFSET 5
#define UART_2_SOFT_RST_MASK 0x00000020
#define UART_1_SOFT_RST_OFFSET 4
#define UART_1_SOFT_RST_MASK 0x00000010
#define INTC_SOFT_RST_OFFSET 3
#define INTC_SOFT_RST_MASK 0x00000008
#define GTMR0_SOFT_RST_OFFSET 2
#define GTMR0_SOFT_RST_MASK 0x00000004
#define GPIO_SOFT_RST_OFFSET 1
#define GPIO_SOFT_RST_MASK 0x00000002
#define UART_0_SOFT_RST_OFFSET 0
#define UART_0_SOFT_RST_MASK 0x00000001

//-----------------------------------
#define CFG_APB_GPIO_CFG_ADDR 0x000c
#define GPIO_ENA_CFG_OFFSET 0
#define GPIO_ENA_CFG_MASK 0x000001FF

//-----------------------------------
#define CFG_APB_GLB_CTRL_ADDR 0x0010
#define GLB_CTRL0_OFFSET 0
#define GLB_CTRL0_MASK 0xFFFFFFFF

//HW module read/write macro
#define APB_GLB_READ_REG(addr) SOC_READ_REG(APB_GLB_BASEADDR + addr)
#define APB_GLB_WRITE_REG(addr,value) SOC_WRITE_REG(APB_GLB_BASEADDR + addr,value)