#define SNAPSHOT_RF_BASEADDR 0x55000000
#define ADA_BASEADDR 0x53200000
#define AHB_RF_BASEADDR 0x50000000
#define EFUSE_DIG_BASEADDR 0x44011000
#define INTC_BASEADDR 0x44004000
#define INTC1_BASEADDR 0x4401e000
#define RGF_HWQ_BASEADDR 0x51000800
#define RGF_RAW_BASEADDR 0x51001000
#define RGF_RX_BASEADDR 0x51000C00
#define RGF_MAC_BASEADDR 0x51000000
#define RGF_TMR_BASEADDR 0x51000400
#define PHY_RXTD_BASEADDR 0x51A00000
#define PHY_TX_BASEADDR 0x51900000
#define SEC_SYS_RF_BASEADDR 0x60000000
#define SFC_RF_BASEADDR 0x52000100
#define SMC_RF_BASEADDR 0x52000200
#define SPI_MST_BASEADDR 0x4400A000
#define APB_UART_BASEADDR 0x44001000
#define APB_UART1_BASEADDR 0x44005000
#define APB_UART2_BASEADDR 0x44006000
#define APB_UART3_BASEADDR 0x44010000
#define WDG_BASEADDR 0x4400e000
#define WDG1_BASEADDR 0x44023000
#define PHY_BASEADDR 0x51800000
#define GTMR_BASEADDR 0x44003000
#define GTMR1_BASEADDR 0x44008000
#define APB_GLB_BASEADDR 0x44000000
#define DMA_BASEADDR 0x44012000
#define DMA1_BASEADDR 0x44013000
#define DMA2_BASEADDR 0x44014000
#define DMA3_BASEADDR 0x44015000
#define DMA4_BASEADDR 0x44016000
#define DMA5_BASEADDR 0x44017000
#define DMA6_BASEADDR 0x44018000
#define DMA7_BASEADDR 0x44019000
#define DMA8_BASEADDR 0x4401A000
#define DMA9_BASEADDR 0x4401B000
#define DMA10_BASEADDR 0x4401C000
#define PHY_RX_FD_BASEADDR 0x51B00000
#define PHY_DFE_BASEADDR 0x51C00000
#define SPI_MST_BASEADDR 0x4400A000
#define GPIO_MTX_BASEADDR 0x44020000
#define PIN_RF_BASEADDR 0x44007000
#define SW_DMA_REG0_BASEADDR 0x70000000
#define SW_DMA_REG1_BASEADDR 0x71000000