//----------------------------------- #define CFG_SADC1_RVER_ADDR 0x0000 #define SADC0_RF_VER_OFFSET 0 #define SADC0_RF_VER_MASK 0x0000FFFF //----------------------------------- #define CFG_SADC1_CHN_CFG_ADDR 0x0004 #define CHN2_TOP_SOFT_RST_OFFSET 31 #define CHN2_TOP_SOFT_RST_MASK 0x80000000 #define CHN2_PHASE3_3_KEEP_RAW_REGDATA_OFFSET 30 #define CHN2_PHASE3_3_KEEP_RAW_REGDATA_MASK 0x40000000 #define CHN2_PHASE3_2_KEEP_RAW_REGDATA_OFFSET 29 #define CHN2_PHASE3_2_KEEP_RAW_REGDATA_MASK 0x20000000 #define CHN2_PHASE3_1_KEEP_RAW_REGDATA_OFFSET 28 #define CHN2_PHASE3_1_KEEP_RAW_REGDATA_MASK 0x10000000 #define CHN2_PHASE3_0_KEEP_RAW_REGDATA_OFFSET 27 #define CHN2_PHASE3_0_KEEP_RAW_REGDATA_MASK 0x08000000 #define CHN2_PHASE2_KEEP_RAW_REGDATA_OFFSET 26 #define CHN2_PHASE2_KEEP_RAW_REGDATA_MASK 0x04000000 #define CHN2_PHASE1_KEEP_RAW_REGDATA_OFFSET 25 #define CHN2_PHASE1_KEEP_RAW_REGDATA_MASK 0x02000000 #define CHN2_PHASE0_KEEP_RAW_REGDATA_OFFSET 24 #define CHN2_PHASE0_KEEP_RAW_REGDATA_MASK 0x01000000 #define CHN2_START_SEL_OFFSET 23 #define CHN2_START_SEL_MASK 0x00800000 #define CHN2_PHASE3_3_KEEP_RAW_DATA_OFFSET 22 #define CHN2_PHASE3_3_KEEP_RAW_DATA_MASK 0x00400000 #define CHN2_PHASE3_2_KEEP_RAW_DATA_OFFSET 21 #define CHN2_PHASE3_2_KEEP_RAW_DATA_MASK 0x00200000 #define CHN2_PHASE3_1_KEEP_RAW_DATA_OFFSET 20 #define CHN2_PHASE3_1_KEEP_RAW_DATA_MASK 0x00100000 #define CHN2_PHASE3_0_KEEP_RAW_DATA_OFFSET 19 #define CHN2_PHASE3_0_KEEP_RAW_DATA_MASK 0x00080000 #define CHN2_PHASE2_KEEP_RAW_DATA_OFFSET 18 #define CHN2_PHASE2_KEEP_RAW_DATA_MASK 0x00040000 #define CHN2_PHASE1_KEEP_RAW_DATA_OFFSET 17 #define CHN2_PHASE1_KEEP_RAW_DATA_MASK 0x00020000 #define CHN2_PHASE0_KEEP_RAW_DATA_OFFSET 16 #define CHN2_PHASE0_KEEP_RAW_DATA_MASK 0x00010000 #define CHN2_HIGH_PREC_SINGLE_PHASE_MOD_OFFSET 15 #define CHN2_HIGH_PREC_SINGLE_PHASE_MOD_MASK 0x00008000 #define CHN2_FILTER_CLK_FRC_ON_OFFSET 14 #define CHN2_FILTER_CLK_FRC_ON_MASK 0x00004000 #define CHN2_WAIT_ANA_SAT_TIME_OFFSET 6 #define CHN2_WAIT_ANA_SAT_TIME_MASK 0x00003FC0 #define CHN2_SINGLE_PHASE_SETTING_OFFSET 4 #define CHN2_SINGLE_PHASE_SETTING_MASK 0x00000030 #define CHN2_SDM_SAT_BYPASS_OFFSET 3 #define CHN2_SDM_SAT_BYPASS_MASK 0x00000008 #define CHN2_STOP_OFFSET 2 #define CHN2_STOP_MASK 0x00000004 #define CHN2_START_OFFSET 1 #define CHN2_START_MASK 0x00000002 //----------------------------------- #define CFG_SADC1_CHN_MUX_SEL_CFG_ADDR 0x0008 #define CHN2_PHASE3_3_SEL_MUX_OFFSET 28 #define CHN2_PHASE3_3_SEL_MUX_MASK 0xF0000000 #define CHN2_PHASE3_2_SEL_MUX_OFFSET 24 #define CHN2_PHASE3_2_SEL_MUX_MASK 0x0F000000 #define CHN2_PHASE3_1_SEL_MUX_OFFSET 20 #define CHN2_PHASE3_1_SEL_MUX_MASK 0x00F00000 #define CHN2_PHASE3_0_SEL_MUX_OFFSET 16 #define CHN2_PHASE3_0_SEL_MUX_MASK 0x000F0000 #define CHN2_PHASE2_SEL_MUX_OFFSET 8 #define CHN2_PHASE2_SEL_MUX_MASK 0x00000F00 #define CHN2_PHASE1_SEL_MUX_OFFSET 4 #define CHN2_PHASE1_SEL_MUX_MASK 0x000000F0 #define CHN2_PHASE0_SEL_MUX_OFFSET 0 #define CHN2_PHASE0_SEL_MUX_MASK 0x0000000F //----------------------------------- #define CFG_SADC1_CHN_SAMPLE_TIME_ADDR 0x000C #define CHN2_SUB_PHASE3_SETTING_OFFSET 30 #define CHN2_SUB_PHASE3_SETTING_MASK 0xC0000000 #define CHN2_PHASE3_3_CLR_AUTO_EN_OFFSET 29 #define CHN2_PHASE3_3_CLR_AUTO_EN_MASK 0x20000000 #define CHN2_PHASE3_2_CLR_AUTO_EN_OFFSET 28 #define CHN2_PHASE3_2_CLR_AUTO_EN_MASK 0x10000000 #define CHN2_PHASE3_1_CLR_AUTO_EN_OFFSET 27 #define CHN2_PHASE3_1_CLR_AUTO_EN_MASK 0x08000000 #define CHN2_PHASE3_0_CLR_AUTO_EN_OFFSET 26 #define CHN2_PHASE3_0_CLR_AUTO_EN_MASK 0x04000000 #define CHN2_PHASE2_CLR_AUTO_EN_OFFSET 25 #define CHN2_PHASE2_CLR_AUTO_EN_MASK 0x02000000 #define CHN2_PHASE1_CLR_AUTO_EN_OFFSET 24 #define CHN2_PHASE1_CLR_AUTO_EN_MASK 0x01000000 #define CHN2_PHASE0_CLR_AUTO_EN_OFFSET 23 #define CHN2_PHASE0_CLR_AUTO_EN_MASK 0x00800000 #define CHN2_WAIT_SDM_SAT_TIME_OFFSET 16 #define CHN2_WAIT_SDM_SAT_TIME_MASK 0x000F0000 #define CHN2_SAMPLE_DATA_3RD_NUM_OFFSET 12 #define CHN2_SAMPLE_DATA_3RD_NUM_MASK 0x0000F000 #define CHN2_SAMPLE_DATA_2ND_NUM_OFFSET 4 #define CHN2_SAMPLE_DATA_2ND_NUM_MASK 0x00000FF0 #define CHN2_SAMPLE_DATA_1ST_NUM_OFFSET 0 #define CHN2_SAMPLE_DATA_1ST_NUM_MASK 0x0000000F //----------------------------------- #define CFG_SADC1_CHN_FILTER_CFG_ADDR 0x0010 #define CHN2_PHASE3_3_FILTER_CNT_LIMIT_OFFSET 28 #define CHN2_PHASE3_3_FILTER_CNT_LIMIT_MASK 0x30000000 #define CHN2_PHASE3_2_FILTER_CNT_LIMIT_OFFSET 26 #define CHN2_PHASE3_2_FILTER_CNT_LIMIT_MASK 0x0C000000 #define CHN2_PHASE3_1_FILTER_CNT_LIMIT_OFFSET 24 #define CHN2_PHASE3_1_FILTER_CNT_LIMIT_MASK 0x03000000 #define CHN2_PHASE3_0_FILTER_CNT_LIMIT_OFFSET 22 #define CHN2_PHASE3_0_FILTER_CNT_LIMIT_MASK 0x00C00000 #define CHN2_PHASE2_FILTER_CNT_LIMIT_OFFSET 20 #define CHN2_PHASE2_FILTER_CNT_LIMIT_MASK 0x00300000 #define CHN2_PHASE1_FILTER_CNT_LIMIT_OFFSET 18 #define CHN2_PHASE1_FILTER_CNT_LIMIT_MASK 0x000C0000 #define CHN2_PHASE0_FILTER_CNT_LIMIT_OFFSET 16 #define CHN2_PHASE0_FILTER_CNT_LIMIT_MASK 0x00030000 #define METER_ADC_CHN2_DO_ORDER_OFFSET 10 #define METER_ADC_CHN2_DO_ORDER_MASK 0x00000400 #define CHN2_SINC_CNT_LIMIT_OFFSET 5 #define CHN2_SINC_CNT_LIMIT_MASK 0x000003E0 #define METER_ADC_CHN2_DO3_INV_OFFSET 4 #define METER_ADC_CHN2_DO3_INV_MASK 0x00000010 #define METER_ADC_CHN2_DO2_INV_OFFSET 3 #define METER_ADC_CHN2_DO2_INV_MASK 0x00000008 #define METER_ADC_CHN2_DO1_INV_OFFSET 2 #define METER_ADC_CHN2_DO1_INV_MASK 0x00000004 #define METER_ADC_CHN2_DO_SEL_OFFSET 0 #define METER_ADC_CHN2_DO_SEL_MASK 0x00000003 //----------------------------------- #define CFG_SADC1_PHASE0_THRS_CFG_ADDR 0x0014 #define ADC1_PHASE0_THRS_OFFSET 0 #define ADC1_PHASE0_THRS_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE1_THRS_CFG_ADDR 0x0018 #define ADC1_PHASE1_THRS_OFFSET 0 #define ADC1_PHASE1_THRS_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE2_THRS_CFG_ADDR 0x001C #define ADC1_PHASE2_THRS_OFFSET 0 #define ADC1_PHASE2_THRS_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_0_THRS_CFG_ADDR 0x0020 #define ADC1_PHASE3_0_THRS_OFFSET 0 #define ADC1_PHASE3_0_THRS_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_1_THRS_CFG_ADDR 0x0024 #define ADC1_PHASE3_1_THRS_OFFSET 0 #define ADC1_PHASE3_1_THRS_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_2_THRS_CFG_ADDR 0x0028 #define ADC1_PHASE3_2_THRS_OFFSET 0 #define ADC1_PHASE3_2_THRS_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_3_THRS_CFG_ADDR 0x002C #define ADC1_PHASE3_3_THRS_OFFSET 0 #define ADC1_PHASE3_3_THRS_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE_DATA_CLR_ADDR 0x0030 #define ADC1_PHASE3_3_CLR_OFFSET 6 #define ADC1_PHASE3_3_CLR_MASK 0x00000040 #define ADC1_PHASE3_2_CLR_OFFSET 5 #define ADC1_PHASE3_2_CLR_MASK 0x00000020 #define ADC1_PHASE3_1_CLR_OFFSET 4 #define ADC1_PHASE3_1_CLR_MASK 0x00000010 #define ADC1_PHASE3_0_CLR_OFFSET 3 #define ADC1_PHASE3_0_CLR_MASK 0x00000008 #define ADC1_PHASE2_CLR_OFFSET 2 #define ADC1_PHASE2_CLR_MASK 0x00000004 #define ADC1_PHASE1_CLR_OFFSET 1 #define ADC1_PHASE1_CLR_MASK 0x00000002 #define ADC1_PHASE0_CLR_OFFSET 0 #define ADC1_PHASE0_CLR_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_PHASE0_RDATA_ADDR 0x0034 #define ADC1_PHASE0_DATA_VALID_OFFSET 24 #define ADC1_PHASE0_DATA_VALID_MASK 0x01000000 #define ADC1_PHASE0_DATA_OFFSET 0 #define ADC1_PHASE0_DATA_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE1_RDATA_ADDR 0x0038 #define ADC1_PHASE1_DATA_VALID_OFFSET 24 #define ADC1_PHASE1_DATA_VALID_MASK 0x01000000 #define ADC1_PHASE1_DATA_OFFSET 0 #define ADC1_PHASE1_DATA_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE2_RDATA_ADDR 0x003C #define ADC1_PHASE2_DATA_VALID_OFFSET 24 #define ADC1_PHASE2_DATA_VALID_MASK 0x01000000 #define ADC1_PHASE2_DATA_OFFSET 0 #define ADC1_PHASE2_DATA_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_0_RDATA_ADDR 0x0040 #define ADC1_PHASE3_0_DATA_VALID_OFFSET 24 #define ADC1_PHASE3_0_DATA_VALID_MASK 0x01000000 #define ADC1_PHASE3_0_DATA_OFFSET 0 #define ADC1_PHASE3_0_DATA_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_1_RDATA_ADDR 0x0044 #define ADC1_PHASE3_1_DATA_VALID_OFFSET 24 #define ADC1_PHASE3_1_DATA_VALID_MASK 0x01000000 #define ADC1_PHASE3_1_DATA_OFFSET 0 #define ADC1_PHASE3_1_DATA_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_2_RDATA_ADDR 0x0048 #define ADC1_PHASE3_2_DATA_VALID_OFFSET 24 #define ADC1_PHASE3_2_DATA_VALID_MASK 0x01000000 #define ADC1_PHASE3_2_DATA_OFFSET 0 #define ADC1_PHASE3_2_DATA_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_PHASE3_3_RDATA_ADDR 0x004C #define ADC1_PHASE3_3_DATA_VALID_OFFSET 24 #define ADC1_PHASE3_3_DATA_VALID_MASK 0x01000000 #define ADC1_PHASE3_3_DATA_OFFSET 0 #define ADC1_PHASE3_3_DATA_MASK 0x00FFFFFF //----------------------------------- #define CFG_SADC1_VCM_CH1_SEL_MUX_ADDR 0x0054 #define CHN2_PHASE3_3_SEL_VCM_OFFSET 19 #define CHN2_PHASE3_3_SEL_VCM_MASK 0x00080000 #define CHN2_PHASE3_2_SEL_VCM_OFFSET 18 #define CHN2_PHASE3_2_SEL_VCM_MASK 0x00040000 #define CHN2_PHASE3_1_SEL_VCM_OFFSET 17 #define CHN2_PHASE3_1_SEL_VCM_MASK 0x00020000 #define CHN2_PHASE3_0_SEL_VCM_OFFSET 16 #define CHN2_PHASE3_0_SEL_VCM_MASK 0x00010000 #define CHN2_PHASE2_SEL_VCM_OFFSET 2 #define CHN2_PHASE2_SEL_VCM_MASK 0x00000004 #define CHN2_PHASE1_SEL_VCM_OFFSET 1 #define CHN2_PHASE1_SEL_VCM_MASK 0x00000002 #define CHN2_PHASE0_SEL_VCM_OFFSET 0 #define CHN2_PHASE0_SEL_VCM_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_RST_CH1_ADDR 0x0058 #define CHN2_PHASE3_3_RST_OFFSET 19 #define CHN2_PHASE3_3_RST_MASK 0x00080000 #define CHN2_PHASE3_2_RST_OFFSET 18 #define CHN2_PHASE3_2_RST_MASK 0x00040000 #define CHN2_PHASE3_1_RST_OFFSET 17 #define CHN2_PHASE3_1_RST_MASK 0x00020000 #define CHN2_PHASE3_0_RST_OFFSET 16 #define CHN2_PHASE3_0_RST_MASK 0x00010000 #define CHN2_PHASE2_RST_OFFSET 2 #define CHN2_PHASE2_RST_MASK 0x00000004 #define CHN2_PHASE1_RST_OFFSET 1 #define CHN2_PHASE1_RST_MASK 0x00000002 #define CHN2_PHASE0_RST_OFFSET 0 #define CHN2_PHASE0_RST_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_IFRED_CH1_EN_ADDR 0x005C #define CHN2_PHASE3_3_TSW_IFRED_EN_OFFSET 19 #define CHN2_PHASE3_3_TSW_IFRED_EN_MASK 0x00080000 #define CHN2_PHASE3_2_TSW_IFRED_EN_OFFSET 18 #define CHN2_PHASE3_2_TSW_IFRED_EN_MASK 0x00040000 #define CHN2_PHASE3_1_TSW_IFRED_EN_OFFSET 17 #define CHN2_PHASE3_1_TSW_IFRED_EN_MASK 0x00020000 #define CHN2_PHASE3_0_TSW_IFRED_EN_OFFSET 16 #define CHN2_PHASE3_0_TSW_IFRED_EN_MASK 0x00010000 #define CHN2_PHASE2_TSW_IFRED_EN_OFFSET 2 #define CHN2_PHASE2_TSW_IFRED_EN_MASK 0x00000004 #define CHN2_PHASE1_TSW_IFRED_EN_OFFSET 1 #define CHN2_PHASE1_TSW_IFRED_EN_MASK 0x00000002 #define CHN2_PHASE0_TSW_IFRED_EN_OFFSET 0 #define CHN2_PHASE0_TSW_IFRED_EN_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_ECG_INPDR_ADDR 0x0060 #define CHN2_PHASE3_3_TSW_ECG_INPDR_OFFSET 19 #define CHN2_PHASE3_3_TSW_ECG_INPDR_MASK 0x00080000 #define CHN2_PHASE3_2_TSW_ECG_INPDR_OFFSET 18 #define CHN2_PHASE3_2_TSW_ECG_INPDR_MASK 0x00040000 #define CHN2_PHASE3_1_TSW_ECG_INPDR_OFFSET 17 #define CHN2_PHASE3_1_TSW_ECG_INPDR_MASK 0x00020000 #define CHN2_PHASE3_0_TSW_ECG_INPDR_OFFSET 16 #define CHN2_PHASE3_0_TSW_ECG_INPDR_MASK 0x00010000 #define CHN2_PHASE2_TSW_ECG_INPDR_OFFSET 2 #define CHN2_PHASE2_TSW_ECG_INPDR_MASK 0x00000004 #define CHN2_PHASE1_TSW_ECG_INPDR_OFFSET 1 #define CHN2_PHASE1_TSW_ECG_INPDR_MASK 0x00000002 #define CHN2_PHASE0_TSW_ECG_INPDR_OFFSET 0 #define CHN2_PHASE0_TSW_ECG_INPDR_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_ECG_INPDL_ADDR 0x0064 #define CHN2_PHASE3_3_TSW_ECG_INPDL_OFFSET 19 #define CHN2_PHASE3_3_TSW_ECG_INPDL_MASK 0x00080000 #define CHN2_PHASE3_2_TSW_ECG_INPDL_OFFSET 18 #define CHN2_PHASE3_2_TSW_ECG_INPDL_MASK 0x00040000 #define CHN2_PHASE3_1_TSW_ECG_INPDL_OFFSET 17 #define CHN2_PHASE3_1_TSW_ECG_INPDL_MASK 0x00020000 #define CHN2_PHASE3_0_TSW_ECG_INPDL_OFFSET 16 #define CHN2_PHASE3_0_TSW_ECG_INPDL_MASK 0x00010000 #define CHN2_PHASE2_TSW_ECG_INPDL_OFFSET 2 #define CHN2_PHASE2_TSW_ECG_INPDL_MASK 0x00000004 #define CHN2_PHASE1_TSW_ECG_INPDL_OFFSET 1 #define CHN2_PHASE1_TSW_ECG_INPDL_MASK 0x00000002 #define CHN2_PHASE0_TSW_ECG_INPDL_OFFSET 0 #define CHN2_PHASE0_TSW_ECG_INPDL_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_ECG_SENS_ADDR 0x0068 #define CHN2_PHASE3_3_TSW_ECG_SENS_OFFSET 19 #define CHN2_PHASE3_3_TSW_ECG_SENS_MASK 0x00080000 #define CHN2_PHASE3_2_TSW_ECG_SENS_OFFSET 18 #define CHN2_PHASE3_2_TSW_ECG_SENS_MASK 0x00040000 #define CHN2_PHASE3_1_TSW_ECG_SENS_OFFSET 17 #define CHN2_PHASE3_1_TSW_ECG_SENS_MASK 0x00020000 #define CHN2_PHASE3_0_TSW_ECG_SENS_OFFSET 16 #define CHN2_PHASE3_0_TSW_ECG_SENS_MASK 0x00010000 #define CHN2_PHASE2_TSW_ECG_SENS_OFFSET 2 #define CHN2_PHASE2_TSW_ECG_SENS_MASK 0x00000004 #define CHN2_PHASE1_TSW_ECG_SENS_OFFSET 1 #define CHN2_PHASE1_TSW_ECG_SENS_MASK 0x00000002 #define CHN2_PHASE0_TSW_ECG_SENS_OFFSET 0 #define CHN2_PHASE0_TSW_ECG_SENS_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_ECG_GAIN_CTL_ADDR 0x006C #define CHN2_PHASE3_3_TSW_ECG_GAIN_CTL_OFFSET 25 #define CHN2_PHASE3_3_TSW_ECG_GAIN_CTL_MASK 0x0E000000 #define CHN2_PHASE3_2_TSW_ECG_GAIN_CTL_OFFSET 22 #define CHN2_PHASE3_2_TSW_ECG_GAIN_CTL_MASK 0x01C00000 #define CHN2_PHASE3_1_TSW_ECG_GAIN_CTL_OFFSET 19 #define CHN2_PHASE3_1_TSW_ECG_GAIN_CTL_MASK 0x00380000 #define CHN2_PHASE3_0_TSW_ECG_GAIN_CTL_OFFSET 16 #define CHN2_PHASE3_0_TSW_ECG_GAIN_CTL_MASK 0x00070000 #define CHN2_PHASE2_TSW_ECG_GAIN_CTL_OFFSET 6 #define CHN2_PHASE2_TSW_ECG_GAIN_CTL_MASK 0x000001C0 #define CHN2_PHASE1_TSW_ECG_GAIN_CTL_OFFSET 3 #define CHN2_PHASE1_TSW_ECG_GAIN_CTL_MASK 0x00000038 #define CHN2_PHASE0_TSW_ECG_GAIN_CTL_OFFSET 0 #define CHN2_PHASE0_TSW_ECG_GAIN_CTL_MASK 0x00000007 //----------------------------------- #define CFG_SADC1_SCLR_CTRL_ADDR 0x0070 #define CHN2_PHASE3_3_SCLR_CTRL_OFFSET 22 #define CHN2_PHASE3_3_SCLR_CTRL_MASK 0x00C00000 #define CHN2_PHASE3_2_SCLR_CTRL_OFFSET 20 #define CHN2_PHASE3_2_SCLR_CTRL_MASK 0x00300000 #define CHN2_PHASE3_1_SCLR_CTRL_OFFSET 18 #define CHN2_PHASE3_1_SCLR_CTRL_MASK 0x000C0000 #define CHN2_PHASE3_0_SCLR_CTRL_OFFSET 16 #define CHN2_PHASE3_0_SCLR_CTRL_MASK 0x00030000 #define CHN2_PHASE2_SCLR_CTRL_OFFSET 4 #define CHN2_PHASE2_SCLR_CTRL_MASK 0x00000030 #define CHN2_PHASE1_SCLR_CTRL_OFFSET 2 #define CHN2_PHASE1_SCLR_CTRL_MASK 0x0000000C #define CHN2_PHASE0_SCLR_CTRL_OFFSET 0 #define CHN2_PHASE0_SCLR_CTRL_MASK 0x00000003 //----------------------------------- #define CFG_SADC1_EXTEMP_SENS_EN_ADDR 0x0074 #define CHN2_PHASE3_3_TSW_EXTEMP_SENS_EN_OFFSET 19 #define CHN2_PHASE3_3_TSW_EXTEMP_SENS_EN_MASK 0x00080000 #define CHN2_PHASE3_2_TSW_EXTEMP_SENS_EN_OFFSET 18 #define CHN2_PHASE3_2_TSW_EXTEMP_SENS_EN_MASK 0x00040000 #define CHN2_PHASE3_1_TSW_EXTEMP_SENS_EN_OFFSET 17 #define CHN2_PHASE3_1_TSW_EXTEMP_SENS_EN_MASK 0x00020000 #define CHN2_PHASE3_0_TSW_EXTEMP_SENS_EN_OFFSET 16 #define CHN2_PHASE3_0_TSW_EXTEMP_SENS_EN_MASK 0x00010000 #define CHN2_PHASE2_TSW_EXTEMP_SENS_EN_OFFSET 2 #define CHN2_PHASE2_TSW_EXTEMP_SENS_EN_MASK 0x00000004 #define CHN2_PHASE1_TSW_EXTEMP_SENS_EN_OFFSET 1 #define CHN2_PHASE1_TSW_EXTEMP_SENS_EN_MASK 0x00000002 #define CHN2_PHASE0_TSW_EXTEMP_SENS_EN_OFFSET 0 #define CHN2_PHASE0_TSW_EXTEMP_SENS_EN_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_SUB_DC_THRS_ADDR 0x0078 #define CHN2_PHASE3_3_DC_EN_OFFSET 24 #define CHN2_PHASE3_3_DC_EN_MASK 0x01000000 #define CHN2_PHASE3_3_DC_THRS_OFFSET 0 #define CHN2_PHASE3_3_DC_THRS_MASK 0x000FFFFF //----------------------------------- #define CFG_SADC1_DBG_BUS0_ADDR 0x007C #define CHN2_SIG_DBG_BUS_OFFSET 0 #define CHN2_SIG_DBG_BUS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SADC1_INT_RAW_ADDR 0x0100 #define ADC1_FIFO_FULL_INT_RAW_OFFSET 8 #define ADC1_FIFO_FULL_INT_RAW_MASK 0x00000100 #define ADC1_PHASE3_3_EXCEED_THRS_INT_RAW_OFFSET 6 #define ADC1_PHASE3_3_EXCEED_THRS_INT_RAW_MASK 0x00000040 #define ADC1_PHASE3_2_EXCEED_THRS_INT_RAW_OFFSET 5 #define ADC1_PHASE3_2_EXCEED_THRS_INT_RAW_MASK 0x00000020 #define ADC1_PHASE3_1_EXCEED_THRS_INT_RAW_OFFSET 4 #define ADC1_PHASE3_1_EXCEED_THRS_INT_RAW_MASK 0x00000010 #define ADC1_PHASE3_0_EXCEED_THRS_INT_RAW_OFFSET 3 #define ADC1_PHASE3_0_EXCEED_THRS_INT_RAW_MASK 0x00000008 #define ADC1_PHASE2_EXCEED_THRS_INT_RAW_OFFSET 2 #define ADC1_PHASE2_EXCEED_THRS_INT_RAW_MASK 0x00000004 #define ADC1_PHASE1_EXCEED_THRS_INT_RAW_OFFSET 1 #define ADC1_PHASE1_EXCEED_THRS_INT_RAW_MASK 0x00000002 #define ADC1_PHASE0_EXCEED_THRS_INT_RAW_OFFSET 0 #define ADC1_PHASE0_EXCEED_THRS_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_INT_ST_ADDR 0x0104 #define ADC1_FIFO_FULL_INT_ST_OFFSET 8 #define ADC1_FIFO_FULL_INT_ST_MASK 0x00000100 #define ADC1_PHASE3_3_EXCEED_THRS_INT_ST_OFFSET 6 #define ADC1_PHASE3_3_EXCEED_THRS_INT_ST_MASK 0x00000040 #define ADC1_PHASE3_2_EXCEED_THRS_INT_ST_OFFSET 5 #define ADC1_PHASE3_2_EXCEED_THRS_INT_ST_MASK 0x00000020 #define ADC1_PHASE3_1_EXCEED_THRS_INT_ST_OFFSET 4 #define ADC1_PHASE3_1_EXCEED_THRS_INT_ST_MASK 0x00000010 #define ADC1_PHASE3_0_EXCEED_THRS_INT_ST_OFFSET 3 #define ADC1_PHASE3_0_EXCEED_THRS_INT_ST_MASK 0x00000008 #define ADC1_PHASE2_EXCEED_THRS_INT_ST_OFFSET 2 #define ADC1_PHASE2_EXCEED_THRS_INT_ST_MASK 0x00000004 #define ADC1_PHASE1_EXCEED_THRS_INT_ST_OFFSET 1 #define ADC1_PHASE1_EXCEED_THRS_INT_ST_MASK 0x00000002 #define ADC1_PHASE0_EXCEED_THRS_INT_ST_OFFSET 0 #define ADC1_PHASE0_EXCEED_THRS_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_INT_ENA_ADDR 0x0108 #define ADC1_FIFO_FULL_INT_ENA_OFFSET 8 #define ADC1_FIFO_FULL_INT_ENA_MASK 0x00000100 #define ADC1_PHASE3_3_EXCEED_THRS_INT_ENA_OFFSET 6 #define ADC1_PHASE3_3_EXCEED_THRS_INT_ENA_MASK 0x00000040 #define ADC1_PHASE3_2_EXCEED_THRS_INT_ENA_OFFSET 5 #define ADC1_PHASE3_2_EXCEED_THRS_INT_ENA_MASK 0x00000020 #define ADC1_PHASE3_1_EXCEED_THRS_INT_ENA_OFFSET 4 #define ADC1_PHASE3_1_EXCEED_THRS_INT_ENA_MASK 0x00000010 #define ADC1_PHASE3_0_EXCEED_THRS_INT_ENA_OFFSET 3 #define ADC1_PHASE3_0_EXCEED_THRS_INT_ENA_MASK 0x00000008 #define ADC1_PHASE2_EXCEED_THRS_INT_ENA_OFFSET 2 #define ADC1_PHASE2_EXCEED_THRS_INT_ENA_MASK 0x00000004 #define ADC1_PHASE1_EXCEED_THRS_INT_ENA_OFFSET 1 #define ADC1_PHASE1_EXCEED_THRS_INT_ENA_MASK 0x00000002 #define ADC1_PHASE0_EXCEED_THRS_INT_ENA_OFFSET 0 #define ADC1_PHASE0_EXCEED_THRS_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_INT_CLR_ADDR 0x010C #define ADC1_FIFO_FULL_INT_CLR_OFFSET 8 #define ADC1_FIFO_FULL_INT_CLR_MASK 0x00000100 #define ADC1_PHASE3_3_EXCEED_THRS_INT_CLR_OFFSET 6 #define ADC1_PHASE3_3_EXCEED_THRS_INT_CLR_MASK 0x00000040 #define ADC1_PHASE3_2_EXCEED_THRS_INT_CLR_OFFSET 5 #define ADC1_PHASE3_2_EXCEED_THRS_INT_CLR_MASK 0x00000020 #define ADC1_PHASE3_1_EXCEED_THRS_INT_CLR_OFFSET 4 #define ADC1_PHASE3_1_EXCEED_THRS_INT_CLR_MASK 0x00000010 #define ADC1_PHASE3_0_EXCEED_THRS_INT_CLR_OFFSET 3 #define ADC1_PHASE3_0_EXCEED_THRS_INT_CLR_MASK 0x00000008 #define ADC1_PHASE2_EXCEED_THRS_INT_CLR_OFFSET 2 #define ADC1_PHASE2_EXCEED_THRS_INT_CLR_MASK 0x00000004 #define ADC1_PHASE1_EXCEED_THRS_INT_CLR_OFFSET 1 #define ADC1_PHASE1_EXCEED_THRS_INT_CLR_MASK 0x00000002 #define ADC1_PHASE0_EXCEED_THRS_INT_CLR_OFFSET 0 #define ADC1_PHASE0_EXCEED_THRS_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_PHASE_EXTHRS_SEL_ADDR 0x0110 #define SADC1_PHASE3_3_EXTHRS_SEL_OFFSET 6 #define SADC1_PHASE3_3_EXTHRS_SEL_MASK 0x00000040 #define SADC1_PHASE3_2_EXTHRS_SEL_OFFSET 5 #define SADC1_PHASE3_2_EXTHRS_SEL_MASK 0x00000020 #define SADC1_PHASE3_1_EXTHRS_SEL_OFFSET 4 #define SADC1_PHASE3_1_EXTHRS_SEL_MASK 0x00000010 #define SADC1_PHASE3_0_EXTHRS_SEL_OFFSET 3 #define SADC1_PHASE3_0_EXTHRS_SEL_MASK 0x00000008 #define SADC1_PHASE2_EXTHRS_SEL_OFFSET 2 #define SADC1_PHASE2_EXTHRS_SEL_MASK 0x00000004 #define SADC1_PHASE1_EXTHRS_SEL_OFFSET 1 #define SADC1_PHASE1_EXTHRS_SEL_MASK 0x00000002 #define SADC1_PHASE0_EXTHRS_SEL_OFFSET 0 #define SADC1_PHASE0_EXTHRS_SEL_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_PHASE_DMA_OUT_CFG_ADDR 0x0114 #define SADC1_PHASE3_3_DMA_OUT_EB_OFFSET 6 #define SADC1_PHASE3_3_DMA_OUT_EB_MASK 0x00000040 #define SADC1_PHASE3_2_DMA_OUT_EB_OFFSET 5 #define SADC1_PHASE3_2_DMA_OUT_EB_MASK 0x00000020 #define SADC1_PHASE3_1_DMA_OUT_EB_OFFSET 4 #define SADC1_PHASE3_1_DMA_OUT_EB_MASK 0x00000010 #define SADC1_PHASE3_0_DMA_OUT_EB_OFFSET 3 #define SADC1_PHASE3_0_DMA_OUT_EB_MASK 0x00000008 #define SADC1_PHASE2_DMA_OUT_EB_OFFSET 2 #define SADC1_PHASE2_DMA_OUT_EB_MASK 0x00000004 #define SADC1_PHASE1_DMA_OUT_EB_OFFSET 1 #define SADC1_PHASE1_DMA_OUT_EB_MASK 0x00000002 #define SADC1_PHASE0_DMA_OUT_EB_OFFSET 0 #define SADC1_PHASE0_DMA_OUT_EB_MASK 0x00000001 //----------------------------------- #define CFG_SADC1_CHN_CFG1_ADDR 0x0118 #define SADC1_SINC5_SHIFT_NUM_OFFSET 3 #define SADC1_SINC5_SHIFT_NUM_MASK 0x000000F8 #define CHN2_PHASE_MODE_OFFSET 0 #define CHN2_PHASE_MODE_MASK 0x00000007 //----------------------------------- #define CFG_SADC1_DBG_CFG_ADDR 0x0140 #define SADC1_DBG_SEL_OFFSET 1 #define SADC1_DBG_SEL_MASK 0x00000006 #define SADC1_DBG_MODE_OFFSET 0 #define SADC1_DBG_MODE_MASK 0x00000001 //HW module read/write macro #define SADC1_READ_REG(addr) SOC_READ_REG(SADC1_BASEADDR + addr) #define SADC1_WRITE_REG(addr,value) SOC_WRITE_REG(SADC1_BASEADDR + addr,value)