/****************************************************************************

Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/
#include "os_types.h"
#include "sec_glb.h"
#if 0
#include "hw_reg_api.h"

#include "sec_glb_rf.h"

void sec_glb_enable(uint32_t module)
{
    volatile uint32_t delay = 100;
    uint32_t i = 0;
    uint32_t tmp;

    //read moudle's status;
    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
    if(tmp & (1<< module))
        return;

    //enable module;
    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
    tmp |= (1<< module);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);

    //soft reset module;
    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
    tmp |= (1<< module);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);

    //delay
    for(i = 0; i < delay; i++);

    //reset done
    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
    tmp &= ~(1<< module);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);
}

void sec_glb_disable(uint32_t module)
{
    uint32_t tmp;

    //disable module;
    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
    tmp &= ~(1<< module);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);
}

void sec_glb_chip_rst()
{
    uint32_t tmp;
    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
    REG_FIELD_SET(CHIP_SOFT_RST, tmp, 1);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);
}

void sec_glb_core1_enable(void)
{
    uint32_t tmp;

    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
    REG_FIELD_SET(RV5_CORE1_EB, tmp, 1);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);

}

void sec_glb_core1_disable(void)
{
    uint32_t tmp;

    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
    REG_FIELD_SET(RV5_CORE1_EB, tmp, 0);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);
}


void sec_glb_core1_reset(uint8_t reset)
{
    uint32_t tmp;

    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_RST_ADDR);
    REG_FIELD_SET(RV5_CORE1_SOFT_RST_P, tmp, reset);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_RST_ADDR, tmp);
}

void sec_glb_core1_set_start(uint32_t addr)
{
    uint32_t tmp;

    tmp = SEC_GLB_RF_READ_REG(CFG_CPU1_START_PC_ADDR);
    REG_FIELD_SET(CORE1_START_PC, tmp, addr);
    SEC_GLB_RF_WRITE_REG(CFG_CPU1_START_PC_ADDR, tmp);
}

void sec_glb_core1_branch_pred_enable(bool_t enable)
{
    uint32_t tmp;
    tmp = SEC_GLB_RF_READ_REG(CFG_SEC_GLB_ENA_ADDR);
    REG_FIELD_SET(RV5_CORE1_BTB_EB, tmp, enable);
    SEC_GLB_RF_WRITE_REG(CFG_SEC_GLB_ENA_ADDR, tmp);

}

void sec_glb_mtx_mst_acc(uint8_t master, uint8_t slave, bool_t enable)
{
    uint32_t tmp;
    tmp = SEC_GLB_RF_READ_REG(CFG_MTX_MST0_ACC_ADDR + master * 4);

    if(enable)
        tmp |= 1 << slave;
    else
        tmp &= ~(1 << slave);

    SEC_GLB_RF_WRITE_REG(CFG_MTX_MST0_ACC_ADDR + master * 4, tmp);

}
#endif

void sec_glb_enable(uint32_t module)
{

}

void sec_glb_disable(uint32_t module)
{

}

void sec_glb_core1_reset(uint8_t reset)
{

}

void sec_glb_core1_set_start(uint32_t addr)
{

}

void sec_glb_core1_disable(void)
{

}

void sec_glb_core1_enable(void)
{

}

void sec_glb_core1_branch_pred_enable(bool_t enable)
{

}

void sec_glb_mtx_mst_acc(uint8_t master, uint8_t slave, bool_t enable)
{

}