/****************************************************************************
 *
 * Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
 *
 * This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
 * be copied by any method or incorporated into another program without
 * the express written consent of Aerospace C.Power. This Information or any portion
 * thereof remains the property of Aerospace C.Power. The Information contained herein
 * is believed to be accurate and Aerospace C.Power assumes no responsibility or
 * liability for its use in any way and conveys no license or title under
 * any patent or copyright and makes no representation or warranty that this
 * Information is free from patent or copyright infringement.
 *
 * ****************************************************************************/

#include "chip_reg_base.h"
#include "hw_reg_api.h"
#include "hw_ada.h"
#include "clk.h"
#include "os_mem.h"
#include "ahb_rf.h"
#include "gp_timer.h"

void dtest_platform_ada_pre_init()
{
    uint32_t tmp = 0;
#if HW_PLATFORM == HW_PLATFORM_FPGA
    /* FPGA change clk to 75M */
    clk_core_freq_set(CPU_FREQ_75M);
#else
    /* change clk to 150M */
    clk_core_freq_set(CPU_FREQ_150M);
#endif

    tmp = AHB_RF_READ_REG(CFG_AHB_REG1_ADDR);
    REG_FIELD_SET(DVP0_EB, tmp, 1);
    REG_FIELD_SET(AI_EB, tmp, 1);
    REG_FIELD_SET(ADA_EB, tmp, 1);
    REG_FIELD_SET(MAC_EB, tmp, 1);
    AHB_RF_WRITE_REG(CFG_AHB_REG1_ADDR, tmp);

    gp_timer_enable(0, 0, 0);

    /* init dtest mem */
    os_mem_init((uint8_t *)0xffffc00,0x400);
}