//-----------------------------------
#define CFG_ADA_RVER_ADDR 0x0000
#define ADA_RF_VER_OFFSET 0
#define ADA_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_ADC_CFG0_ADDR 0x0004
#define ADC_MST_DONE_OFFSET 31
#define ADC_MST_DONE_MASK 0x80000000
#define ADA_DUMP_32B_MODE_OFFSET 16
#define ADA_DUMP_32B_MODE_MASK 0x00010000
#define ADA_DUMP_DDR_MODE_OFFSET 7
#define ADA_DUMP_DDR_MODE_MASK 0x00000080
#define ADA_CLK_RATIO_OFFSET 6
#define ADA_CLK_RATIO_MASK 0x00000040
#define ADC_DMSB_INV_OFFSET 5
#define ADC_DMSB_INV_MASK 0x00000020
#define ADC_MEM_CLK_SW_OFFSET 4
#define ADC_MEM_CLK_SW_MASK 0x00000010
#define ADA_POWER_ON_OFFSET 3
#define ADA_POWER_ON_MASK 0x00000008
#define ADC_SAMPLE_DONE_OFFSET 2
#define ADC_SAMPLE_DONE_MASK 0x00000004
#define ADC_TRIG_OFFSET 1
#define ADC_TRIG_MASK 0x00000002
#define SOC_ADC_EN_OFFSET 0
#define SOC_ADC_EN_MASK 0x00000001

//-----------------------------------
#define CFG_ADC_CFG1_ADDR 0x0008
#define ADC_BUF_SIZE_OFFSET 0
#define ADC_BUF_SIZE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_DAC_CFG0_ADDR 0x000c
#define DAC_MST_DONE_OFFSET 31
#define DAC_MST_DONE_MASK 0x80000000
#define DAC_BUF_SIZE_OFFSET 11
#define DAC_BUF_SIZE_MASK 0x7FFFF800
#define DAC_SIGNED_UNSIGNED_SEL_OFFSET 5
#define DAC_SIGNED_UNSIGNED_SEL_MASK 0x00000020
#define SW_DAC_READ_SPEED_OFFSET 3
#define SW_DAC_READ_SPEED_MASK 0x00000018
#define SW_DAC_BYTES_SELECT_OFFSET 1
#define SW_DAC_BYTES_SELECT_MASK 0x00000006
#define SOC_DAC_EN_OFFSET 0
#define SOC_DAC_EN_MASK 0x00000001

//-----------------------------------
#define CFG_DAC_CFG1_ADDR 0x0010
#define DAC_MUX_OFFSET 17
#define DAC_MUX_MASK 0x00020000
#define TONE_MODE_OFFSET 16
#define TONE_MODE_MASK 0x00010000
#define TONE_NUMBER_OFFSET 0
#define TONE_NUMBER_MASK 0x000007FF

//-----------------------------------
#define CFG_ADC_CFG2_ADDR 0x0014
#define DAC_CLK_INV_OFFSET 25
#define DAC_CLK_INV_MASK 0x02000000
#define ADC_CLK_INV_OFFSET 24
#define ADC_CLK_INV_MASK 0x01000000
#define ADC_TRIG_FROM_PHY_OFFSET 18
#define ADC_TRIG_FROM_PHY_MASK 0x00040000
#define ADC_FORCE_MODE_OFFSET 17
#define ADC_FORCE_MODE_MASK 0x00020000
#define ADC_AUTO_MODE_OFFSET 16
#define ADC_AUTO_MODE_MASK 0x00010000
#define ADC_THR_VAL_OFFSET 0
#define ADC_THR_VAL_MASK 0x0000FFFF

//-----------------------------------
#define CFG_ADC_CFG3_ADDR 0x0018
#define ADC_SAMPLE_SIZE_OFFSET 0
#define ADC_SAMPLE_SIZE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADC_STS0_ADDR 0x001c
#define ADC_TRIG_ADDR_OFFSET 0
#define ADC_TRIG_ADDR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_ADC_DUMP_CTRL_ADDR 0x0020
#define SW_ADC_TRIG_PHY_OFFSET 11
#define SW_ADC_TRIG_PHY_MASK 0x00000800
#define SW_ADC_TRIG_AUTO_OFFSET 10
#define SW_ADC_TRIG_AUTO_MASK 0x00000400
#define SW_ADC_1BYTE_EN_OFFSET 9
#define SW_ADC_1BYTE_EN_MASK 0x00000200
#define SW_ADC_SHIFT_BIT_OFFSET 5
#define SW_ADC_SHIFT_BIT_MASK 0x000001E0
#define SW_ADC_DUMP_SPEED_OFFSET 2
#define SW_ADC_DUMP_SPEED_MASK 0x0000001C
#define SW_ADC_BYTES_SELECT_OFFSET 0
#define SW_ADC_BYTES_SELECT_MASK 0x00000003

//-----------------------------------
#define CFG_DAC_CFG2_ADDR 0x002c
#define DAC_INIT_OFFSET 0
#define DAC_INIT_MASK 0x00000001

//-----------------------------------
#define CFG_DAC_CFG3_ADDR 0x0030
#define DAC_RAM_READ_SADDR_OFFSET 1
#define DAC_RAM_READ_SADDR_MASK 0x001FFFFE
#define DAC_RAM_READ_DONE_OFFSET 0
#define DAC_RAM_READ_DONE_MASK 0x00000001

//-----------------------------------
#define CFG_PSRAM_BUF_PTR_ADDR 0x0034
#define ADA_DATA_BUF_PTR_OFFSET 0
#define ADA_DATA_BUF_PTR_MASK 0xFFFFFFFF

//HW module read/write macro
#define ADA_READ_REG(addr) SOC_READ_REG(ADA_BASEADDR + addr)
#define ADA_WRITE_REG(addr,value) SOC_WRITE_REG(ADA_BASEADDR + addr,value)