//----------------------------------- #define CFG_AHB_RVER_ADDR 0x0000 #define AHB_RF_VER_OFFSET 0 #define AHB_RF_VER_MASK 0x0000FFFF //----------------------------------- #define CFG_AHB_REG0_ADDR 0x0004 #define MPRXCSI3_SOFT_RST_OFFSET 31 #define MPRXCSI3_SOFT_RST_MASK 0x80000000 #define MPRXCSI2_SOFT_RST_OFFSET 30 #define MPRXCSI2_SOFT_RST_MASK 0x40000000 #define MPRXCSI1_SOFT_RST_OFFSET 29 #define MPRXCSI1_SOFT_RST_MASK 0x20000000 #define MPRXCSI0_SOFT_RST_OFFSET 28 #define MPRXCSI0_SOFT_RST_MASK 0x10000000 #define SDIO0_SOFT_RST_OFFSET 27 #define SDIO0_SOFT_RST_MASK 0x08000000 #define SNAP_SHOT_SOFT_RST_OFFSET 26 #define SNAP_SHOT_SOFT_RST_MASK 0x04000000 #define SW_DMA1_SOFT_RST_OFFSET 25 #define SW_DMA1_SOFT_RST_MASK 0x02000000 #define SW_DMA0_SOFT_RST_OFFSET 24 #define SW_DMA0_SOFT_RST_MASK 0x01000000 #define PHY_ANA_SOFT_RST_OFFSET 23 #define PHY_ANA_SOFT_RST_MASK 0x00800000 #define PHY_REG_SOFT_RST_OFFSET 22 #define PHY_REG_SOFT_RST_MASK 0x00400000 #define PHY_SOFT_RST_OFFSET 21 #define PHY_SOFT_RST_MASK 0x00200000 #define MAC_REG_SOFT_RST_OFFSET 20 #define MAC_REG_SOFT_RST_MASK 0x00100000 #define MTX_TRANS_SOFT_RST_OFFSET 19 #define MTX_TRANS_SOFT_RST_MASK 0x00080000 #define MPTX_SOFT_RST_OFFSET 18 #define MPTX_SOFT_RST_MASK 0x00040000 #define RV5_CORE2_SOFT_RST_OFFSET 17 #define RV5_CORE2_SOFT_RST_MASK 0x00020000 #define RV5_CORE0_SOFT_RST_OFFSET 16 #define RV5_CORE0_SOFT_RST_MASK 0x00010000 #define DMC_SOFT_RST_OFFSET 15 #define DMC_SOFT_RST_MASK 0x00008000 #define DVP3_SOFT_RST_OFFSET 14 #define DVP3_SOFT_RST_MASK 0x00004000 #define DVP2_SOFT_RST_OFFSET 13 #define DVP2_SOFT_RST_MASK 0x00002000 #define DVP1_SOFT_RST_OFFSET 12 #define DVP1_SOFT_RST_MASK 0x00001000 #define DVP0_SOFT_RST_OFFSET 11 #define DVP0_SOFT_RST_MASK 0x00000800 #define FISHEYE_SOFT_RST_OFFSET 10 #define FISHEYE_SOFT_RST_MASK 0x00000400 #define ITR_SOFT_RST_OFFSET 9 #define ITR_SOFT_RST_MASK 0x00000200 #define AI_SOFT_RST_OFFSET 7 #define AI_SOFT_RST_MASK 0x00000080 #define GMACG_SOFT_RST_OFFSET 6 #define GMACG_SOFT_RST_MASK 0x00000040 #define GMAC_SOFT_RST_OFFSET 5 #define GMAC_SOFT_RST_MASK 0x00000020 #define DCACHE_SOFT_RST_OFFSET 4 #define DCACHE_SOFT_RST_MASK 0x00000010 #define ICACHE_SOFT_RST_OFFSET 3 #define ICACHE_SOFT_RST_MASK 0x00000008 #define NDFC_SOFT_RST_OFFSET 2 #define NDFC_SOFT_RST_MASK 0x00000004 #define ADA_SOFT_RST_OFFSET 1 #define ADA_SOFT_RST_MASK 0x00000002 #define MAC_SOFT_RST_OFFSET 0 #define MAC_SOFT_RST_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG1_ADDR 0x0008 #define MPRXCSI3_EB_OFFSET 31 #define MPRXCSI3_EB_MASK 0x80000000 #define MPRXCSI2_EB_OFFSET 30 #define MPRXCSI2_EB_MASK 0x40000000 #define MPRXCSI1_EB_OFFSET 29 #define MPRXCSI1_EB_MASK 0x20000000 #define MPRXCSI0_EB_OFFSET 28 #define MPRXCSI0_EB_MASK 0x10000000 #define SDIO0_EB_OFFSET 27 #define SDIO0_EB_MASK 0x08000000 #define SNAP_SHOT_EB_OFFSET 26 #define SNAP_SHOT_EB_MASK 0x04000000 #define SW_DMA1_EB_OFFSET 25 #define SW_DMA1_EB_MASK 0x02000000 #define SW_DMA0_EB_OFFSET 24 #define SW_DMA0_EB_MASK 0x01000000 #define ITR_EB_OFFSET 22 #define ITR_EB_MASK 0x00400000 #define MPTX_EB_OFFSET 21 #define MPTX_EB_MASK 0x00200000 #define PHY_EB_OFFSET 20 #define PHY_EB_MASK 0x00100000 #define PERI_SYS_EB_OFFSET 19 #define PERI_SYS_EB_MASK 0x00080000 #define AHB_SYS_ENA_OFFSET 18 #define AHB_SYS_ENA_MASK 0x00040000 #define RV5_CORE2_EB_OFFSET 17 #define RV5_CORE2_EB_MASK 0x00020000 #define RV5_CORE0_EB_OFFSET 16 #define RV5_CORE0_EB_MASK 0x00010000 #define DMC_EB_OFFSET 15 #define DMC_EB_MASK 0x00008000 #define DVP3_EB_OFFSET 14 #define DVP3_EB_MASK 0x00004000 #define DVP2_EB_OFFSET 13 #define DVP2_EB_MASK 0x00002000 #define DVP1_EB_OFFSET 12 #define DVP1_EB_MASK 0x00001000 #define DVP0_EB_OFFSET 11 #define DVP0_EB_MASK 0x00000800 #define FISHEYE_EB_OFFSET 10 #define FISHEYE_EB_MASK 0x00000400 #define MTXTRANS_EB_OFFSET 9 #define MTXTRANS_EB_MASK 0x00000200 #define AI_EB_OFFSET 7 #define AI_EB_MASK 0x00000080 #define GMACG_EB_OFFSET 6 #define GMACG_EB_MASK 0x00000040 #define GMAC_EB_OFFSET 5 #define GMAC_EB_MASK 0x00000020 #define DCACHE_EB_OFFSET 4 #define DCACHE_EB_MASK 0x00000010 #define ICACHE_EB_OFFSET 3 #define ICACHE_EB_MASK 0x00000008 #define NDFC_EB_OFFSET 2 #define NDFC_EB_MASK 0x00000004 #define ADA_EB_OFFSET 1 #define ADA_EB_MASK 0x00000002 #define MAC_EB_OFFSET 0 #define MAC_EB_MASK 0x00000001 //----------------------------------- #define CFG_AHB_CTR0_ADDR 0x000c #define ICACHE_MODE_OFFSET 25 #define ICACHE_MODE_MASK 0x02000000 #define DCACHE_WR_AUTO_LOAD_OFFSET 24 #define DCACHE_WR_AUTO_LOAD_MASK 0x01000000 #define ICACHE_WR_AUTO_LOAD_OFFSET 23 #define ICACHE_WR_AUTO_LOAD_MASK 0x00800000 #define DCACHE_FLUSH_INVALID_MODE_OFFSET 22 #define DCACHE_FLUSH_INVALID_MODE_MASK 0x00400000 #define ICACHE_FLUSH_INVALID_MODE_OFFSET 21 #define ICACHE_FLUSH_INVALID_MODE_MASK 0x00200000 #define DCACHE_DMC_MODE_OFFSET 20 #define DCACHE_DMC_MODE_MASK 0x00100000 #define ICACHE_DMC_MODE_OFFSET 19 #define ICACHE_DMC_MODE_MASK 0x00080000 #define DCACHE_HIT_ERR_OFFSET 18 #define DCACHE_HIT_ERR_MASK 0x00040000 #define ICACHE_HIT_ERR_OFFSET 17 #define ICACHE_HIT_ERR_MASK 0x00020000 #define DCACHE_MODE_OFFSET 16 #define DCACHE_MODE_MASK 0x00010000 #define DCACHE_FSM_ST_OFFSET 12 #define DCACHE_FSM_ST_MASK 0x0000F000 #define ICACHE_FSM_ST_OFFSET 8 #define ICACHE_FSM_ST_MASK 0x00000F00 #define DCACHE_CLEAR_DONE_OFFSET 7 #define DCACHE_CLEAR_DONE_MASK 0x00000080 #define ICACHE_CLEAR_DONE_OFFSET 6 #define ICACHE_CLEAR_DONE_MASK 0x00000040 #define DCACHE_FLUSH_DONE_OFFSET 5 #define DCACHE_FLUSH_DONE_MASK 0x00000020 #define ICACHE_FLUSH_DONE_OFFSET 4 #define ICACHE_FLUSH_DONE_MASK 0x00000010 #define DCACHE_CLEAR_ENA_OFFSET 3 #define DCACHE_CLEAR_ENA_MASK 0x00000008 #define ICACHE_CLEAR_ENA_OFFSET 2 #define ICACHE_CLEAR_ENA_MASK 0x00000004 #define DCACHE_FLUSH_ENA_OFFSET 1 #define DCACHE_FLUSH_ENA_MASK 0x00000002 #define ICACHE_FLUSH_ENA_OFFSET 0 #define ICACHE_FLUSH_ENA_MASK 0x00000001 //----------------------------------- #define CFG_DBG_CTR_ADDR 0x0010 #define BB_ADC_SCALE_SEL_OFFSET 8 #define BB_ADC_SCALE_SEL_MASK 0x00000F00 #define BB_DAC_SCALE_SEL_OFFSET 2 #define BB_DAC_SCALE_SEL_MASK 0x0000003C //----------------------------------- #define CFG_BOND_OPTION_ADDR 0x0014 #define ROM_FAST_BOOT_MODE_OFFSET 4 #define ROM_FAST_BOOT_MODE_MASK 0x00000010 #define DIG_PKG_TYPE_OFFSET 2 #define DIG_PKG_TYPE_MASK 0x0000000C #define DIG_BOOT_FROM_MODE_OFFSET 1 #define DIG_BOOT_FROM_MODE_MASK 0x00000002 #define DIG_BOOT_SEC_MODE_OFFSET 0 #define DIG_BOOT_SEC_MODE_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG_LOCK_ADDR 0x0018 #define AHB_REG3_UNLOCK_OFFSET 3 #define AHB_REG3_UNLOCK_MASK 0x00000008 #define AHB_REG2_UNLOCK_OFFSET 2 #define AHB_REG2_UNLOCK_MASK 0x00000004 #define AHB_REG1_UNLOCK_OFFSET 1 #define AHB_REG1_UNLOCK_MASK 0x00000002 #define AHB_REG0_UNLOCK_OFFSET 0 #define AHB_REG0_UNLOCK_MASK 0x00000001 //----------------------------------- #define CFG_GMAC_REG1_ADDR 0x001c #define GMAC_PTP_TIMESTMAP_L_OFFSET 0 #define GMAC_PTP_TIMESTMAP_L_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GMAC_REG2_ADDR 0x0020 #define GMAC_PTP_TIMESTMAP_H_OFFSET 0 #define GMAC_PTP_TIMESTMAP_H_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_LP_CTRL_ADDR 0x0030 #define RV5_CORE2_SOFT_RST_LEN_OFFSET 25 #define RV5_CORE2_SOFT_RST_LEN_MASK 0xFE000000 #define RV5_CORE2_SOFT_RST_P_OFFSET 24 #define RV5_CORE2_SOFT_RST_P_MASK 0x01000000 #define RV5_CORE0_SOFT_RST_LEN_OFFSET 17 #define RV5_CORE0_SOFT_RST_LEN_MASK 0x00FE0000 #define RV5_CORE0_SOFT_RST_P_OFFSET 16 #define RV5_CORE0_SOFT_RST_P_MASK 0x00010000 #define CORE2_INT_MASK_OFFSET 7 #define CORE2_INT_MASK_MASK 0x00000080 #define CORE0_INT_MASK_OFFSET 6 #define CORE0_INT_MASK_MASK 0x00000040 #define FORCE_RV5_CORE2_STOP_OFFSET 5 #define FORCE_RV5_CORE2_STOP_MASK 0x00000020 #define FORCE_RV5_CORE0_STOP_OFFSET 4 #define FORCE_RV5_CORE0_STOP_MASK 0x00000010 #define RV5_CORE2_SLEEP_ENA_OFFSET 3 #define RV5_CORE2_SLEEP_ENA_MASK 0x00000008 #define RV5_CORE0_SLEEP_ENA_OFFSET 2 #define RV5_CORE0_SLEEP_ENA_MASK 0x00000004 #define FORCE_AP_DEEP_SLEEP_OFFSET 1 #define FORCE_AP_DEEP_SLEEP_MASK 0x00000002 #define AP_DEEP_SLEEP_ENA_OFFSET 0 #define AP_DEEP_SLEEP_ENA_MASK 0x00000001 //----------------------------------- #define CFG_AHB_MEM_CTRL_ADDR 0x0034 #define IIS3_RAM_FORCE_ON_OFFSET 31 #define IIS3_RAM_FORCE_ON_MASK 0x80000000 #define IIS2_RAM_FORCE_ON_OFFSET 30 #define IIS2_RAM_FORCE_ON_MASK 0x40000000 #define IIS1_RAM_FORCE_ON_OFFSET 29 #define IIS1_RAM_FORCE_ON_MASK 0x20000000 #define MPTX_FORCE_ON_OFFSET 28 #define MPTX_FORCE_ON_MASK 0x10000000 #define DCAM_FORCE_ON_OFFSET 27 #define DCAM_FORCE_ON_MASK 0x08000000 #define GMACG_1000M_RX_BUF_FORCE_ON_OFFSET 26 #define GMACG_1000M_RX_BUF_FORCE_ON_MASK 0x04000000 #define GMACG_1000M_TX_BUF_FORCE_ON_OFFSET 25 #define GMACG_1000M_TX_BUF_FORCE_ON_MASK 0x02000000 #define IIS0_RAM_FORCE_ON_OFFSET 24 #define IIS0_RAM_FORCE_ON_MASK 0x01000000 #define HRAM3_ADC_MODE_OFFSET 23 #define HRAM3_ADC_MODE_MASK 0x00800000 #define HRAM2_ADC_MODE_OFFSET 22 #define HRAM2_ADC_MODE_MASK 0x00400000 #define HRAM1_ADC_MODE_OFFSET 21 #define HRAM1_ADC_MODE_MASK 0x00200000 #define HRAM0_ADC_MODE_OFFSET 20 #define HRAM0_ADC_MODE_MASK 0x00100000 #define UART_RAM_FORCE_ON_OFFSET 19 #define UART_RAM_FORCE_ON_MASK 0x00080000 #define GMAC_RX_BUF_FORCE_ON_OFFSET 18 #define GMAC_RX_BUF_FORCE_ON_MASK 0x00040000 #define GMAC_TX_BUF_FORCE_ON_OFFSET 17 #define GMAC_TX_BUF_FORCE_ON_MASK 0x00020000 #define EMC_BUF_FORCE_ON_OFFSET 16 #define EMC_BUF_FORCE_ON_MASK 0x00010000 #define DCACHE_DMEM3_FORCE_ON_OFFSET 15 #define DCACHE_DMEM3_FORCE_ON_MASK 0x00008000 #define DCACHE_DMEM2_FORCE_ON_OFFSET 14 #define DCACHE_DMEM2_FORCE_ON_MASK 0x00004000 #define DCACHE_DMEM1_FORCE_ON_OFFSET 13 #define DCACHE_DMEM1_FORCE_ON_MASK 0x00002000 #define DCACHE_DMEM0_FORCE_ON_OFFSET 12 #define DCACHE_DMEM0_FORCE_ON_MASK 0x00001000 #define DCACHE_TMEM1_FORCE_ON_OFFSET 11 #define DCACHE_TMEM1_FORCE_ON_MASK 0x00000800 #define DCACHE_TMEM0_FORCE_ON_OFFSET 10 #define DCACHE_TMEM0_FORCE_ON_MASK 0x00000400 #define ICACHE_DMEM1_FORCE_ON_OFFSET 9 #define ICACHE_DMEM1_FORCE_ON_MASK 0x00000200 #define ICACHE_DMEM0_FORCE_ON_OFFSET 8 #define ICACHE_DMEM0_FORCE_ON_MASK 0x00000100 #define ICACHE_TMEM_FORCE_ON_OFFSET 7 #define ICACHE_TMEM_FORCE_ON_MASK 0x00000080 #define HROM_FORCE_ON_OFFSET 5 #define HROM_FORCE_ON_MASK 0x00000020 #define SEC_RAM_FORCE_ON_OFFSET 4 #define SEC_RAM_FORCE_ON_MASK 0x00000010 #define HRAM3_FORCE_ON_OFFSET 3 #define HRAM3_FORCE_ON_MASK 0x00000008 #define HRAM2_FORCE_ON_OFFSET 2 #define HRAM2_FORCE_ON_MASK 0x00000004 #define HRAM1_FORCE_ON_OFFSET 1 #define HRAM1_FORCE_ON_MASK 0x00000002 #define HRAM0_FORCE_ON_OFFSET 0 #define HRAM0_FORCE_ON_MASK 0x00000001 //----------------------------------- #define CFG_DBG_CTR1_ADDR 0x0048 #define MAC_PAUSE_DBG_OFFSET 24 #define MAC_PAUSE_DBG_MASK 0x01000000 #define CHIP_DBG_SIG_SEL_OFFSET 16 #define CHIP_DBG_SIG_SEL_MASK 0x00FF0000 #define CHIP_DBG_BUS_SEL_OFFSET 8 #define CHIP_DBG_BUS_SEL_MASK 0x0000FF00 #define DBG_BUS_TEST_OFFSET 0 #define DBG_BUS_TEST_MASK 0x00000001 //----------------------------------- #define CFG_CPU0_START_PC_ADDR 0x004c #define CORE0_START_PC_OFFSET 0 #define CORE0_START_PC_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RST_FLAG_ADDR 0x0050 #define CORE2_SOFT_RST_FLAG_CLR_OFFSET 30 #define CORE2_SOFT_RST_FLAG_CLR_MASK 0x40000000 #define WDG2_FULLRST_FLAG_CLR_OFFSET 29 #define WDG2_FULLRST_FLAG_CLR_MASK 0x20000000 #define WDG2_CPURST_FLAG_CLR_OFFSET 28 #define WDG2_CPURST_FLAG_CLR_MASK 0x10000000 #define CHIP_SOFT_RST_FLAG_CLR_OFFSET 27 #define CHIP_SOFT_RST_FLAG_CLR_MASK 0x08000000 #define CORE1_SOFT_RST_FLAG_CLR_OFFSET 26 #define CORE1_SOFT_RST_FLAG_CLR_MASK 0x04000000 #define CORE0_SOFT_RST_FLAG_CLR_OFFSET 25 #define CORE0_SOFT_RST_FLAG_CLR_MASK 0x02000000 #define DEBUG1_IO_FULLRESET_FLAG_CLR_OFFSET 24 #define DEBUG1_IO_FULLRESET_FLAG_CLR_MASK 0x01000000 #define DEBUG0_IO_FULLRESET_FLAG_CLR_OFFSET 23 #define DEBUG0_IO_FULLRESET_FLAG_CLR_MASK 0x00800000 #define DEBUG1_IO_NDRESET_FLAG_CLR_OFFSET 22 #define DEBUG1_IO_NDRESET_FLAG_CLR_MASK 0x00400000 #define DEBUG0_IO_NDRESET_FLAG_CLR_OFFSET 21 #define DEBUG0_IO_NDRESET_FLAG_CLR_MASK 0x00200000 #define WDG1_FULLRST_FLAG_CLR_OFFSET 20 #define WDG1_FULLRST_FLAG_CLR_MASK 0x00100000 #define WDG0_FULLRST_FLAG_CLR_OFFSET 19 #define WDG0_FULLRST_FLAG_CLR_MASK 0x00080000 #define WDG1_CPURST_FLAG_CLR_OFFSET 18 #define WDG1_CPURST_FLAG_CLR_MASK 0x00040000 #define WDG0_CPURST_FLAG_CLR_OFFSET 17 #define WDG0_CPURST_FLAG_CLR_MASK 0x00020000 #define POR_RST_FLAG_CLR_OFFSET 16 #define POR_RST_FLAG_CLR_MASK 0x00010000 #define CORE2_SOFT_RST_FLAG_OFFSET 14 #define CORE2_SOFT_RST_FLAG_MASK 0x00004000 #define WDG2_FULLRST_FLAG_OFFSET 13 #define WDG2_FULLRST_FLAG_MASK 0x00002000 #define WDG2_CPURST_FLAG_OFFSET 12 #define WDG2_CPURST_FLAG_MASK 0x00001000 #define CHIP_SOFT_RST_FLAG_OFFSET 11 #define CHIP_SOFT_RST_FLAG_MASK 0x00000800 #define CORE1_SOFT_RST_FLAG_OFFSET 10 #define CORE1_SOFT_RST_FLAG_MASK 0x00000400 #define CORE0_SOFT_RST_FLAG_OFFSET 9 #define CORE0_SOFT_RST_FLAG_MASK 0x00000200 #define DEBUG1_IO_FULLRESET_FLAG_OFFSET 8 #define DEBUG1_IO_FULLRESET_FLAG_MASK 0x00000100 #define DEBUG0_IO_FULLRESET_FLAG_OFFSET 7 #define DEBUG0_IO_FULLRESET_FLAG_MASK 0x00000080 #define DEBUG1_IO_NDRESET_FLAG_OFFSET 6 #define DEBUG1_IO_NDRESET_FLAG_MASK 0x00000040 #define DEBUG0_IO_NDRESET_FLAG_OFFSET 5 #define DEBUG0_IO_NDRESET_FLAG_MASK 0x00000020 #define WDG1_FULLRST_FLAG_OFFSET 4 #define WDG1_FULLRST_FLAG_MASK 0x00000010 #define WDG0_FULLRST_FLAG_OFFSET 3 #define WDG0_FULLRST_FLAG_MASK 0x00000008 #define WDG1_CPURST_FLAG_OFFSET 2 #define WDG1_CPURST_FLAG_MASK 0x00000004 #define WDG0_CPURST_FLAG_OFFSET 1 #define WDG0_CPURST_FLAG_MASK 0x00000002 #define POR_RST_FLAG_OFFSET 0 #define POR_RST_FLAG_MASK 0x00000001 //----------------------------------- #define CFG_CPU_EXPT_EN_ADDR 0x0068 #define CPU1_INST_AF_EXPT_EN_OFFSET 20 #define CPU1_INST_AF_EXPT_EN_MASK 0x00100000 #define CPU1_DATA_LD_AM_EXPT_EN_OFFSET 19 #define CPU1_DATA_LD_AM_EXPT_EN_MASK 0x00080000 #define CPU1_DATA_LD_AF_EXPT_EN_OFFSET 18 #define CPU1_DATA_LD_AF_EXPT_EN_MASK 0x00040000 #define CPU1_DATA_ST_AM_EXPT_EN_OFFSET 17 #define CPU1_DATA_ST_AM_EXPT_EN_MASK 0x00020000 #define CPU1_DATA_ST_AF_EXPT_EN_OFFSET 16 #define CPU1_DATA_ST_AF_EXPT_EN_MASK 0x00010000 #define CPU0_INST_AF_EXPT_EN_OFFSET 4 #define CPU0_INST_AF_EXPT_EN_MASK 0x00000010 #define CPU0_DATA_LD_AM_EXPT_EN_OFFSET 3 #define CPU0_DATA_LD_AM_EXPT_EN_MASK 0x00000008 #define CPU0_DATA_LD_AF_EXPT_EN_OFFSET 2 #define CPU0_DATA_LD_AF_EXPT_EN_MASK 0x00000004 #define CPU0_DATA_ST_AM_EXPT_EN_OFFSET 1 #define CPU0_DATA_ST_AM_EXPT_EN_MASK 0x00000002 #define CPU0_DATA_ST_AF_EXPT_EN_OFFSET 0 #define CPU0_DATA_ST_AF_EXPT_EN_MASK 0x00000001 //----------------------------------- #define CFG_AHB_SCRATCH_R0_ADDR 0x0084 #define AHB_SCRATCH_REG0_OFFSET 0 #define AHB_SCRATCH_REG0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_SCRATCH_R1_ADDR 0x0088 #define AHB_SCRATCH_REG1_OFFSET 0 #define AHB_SCRATCH_REG1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CACHE_VALID_SPACE_ADDR 0x008c #define SMC_SPACE_OFFSET 8 #define SMC_SPACE_MASK 0x00007F00 #define SFC_SPACE_OFFSET 0 #define SFC_SPACE_MASK 0x0000007F //----------------------------------- #define CFG_GMACG_REG1_ADDR 0x0090 #define GMACG_PHY_INTF_SEL_OFFSET 0 #define GMACG_PHY_INTF_SEL_MASK 0x00000007 //----------------------------------- #define CFG_GMACG_REG2_ADDR 0x0094 #define GMACG_PTP_TIMESTMAP_L_OFFSET 0 #define GMACG_PTP_TIMESTMAP_L_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GMACG_REG3_ADDR 0x0098 #define GMACG_PTP_TIMESTMAP_H_OFFSET 0 #define GMACG_PTP_TIMESTMAP_H_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TEMP_REG_ADDR 0x009c #define TEMP_REG_OFFSET 0 #define TEMP_REG_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE_FLUSH_SADDR_ADDR 0x00A0 #define IC_FLUSH_SADDR_OFFSET 0 #define IC_FLUSH_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE_FLUSH_EADDR_ADDR 0x00A4 #define IC_FLUSH_EADDR_OFFSET 0 #define IC_FLUSH_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DCACHE_FLUSH_SADDR_ADDR 0x00A8 #define DC_FLUSH_SADDR_OFFSET 0 #define DC_FLUSH_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DCACHE_FLUSH_EADDR_ADDR 0x00AC #define DC_FLUSH_EADDR_OFFSET 0 #define DC_FLUSH_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_CPU2_START_PC_ADDR 0x00B0 #define CORE2_START_PC_OFFSET 0 #define CORE2_START_PC_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_REG2_ADDR 0x00B4 #define USB_EB_OFFSET 11 #define USB_EB_MASK 0x00000800 #define AFFT1_EB_OFFSET 10 #define AFFT1_EB_MASK 0x00000400 #define CHOL1_EB_OFFSET 9 #define CHOL1_EB_MASK 0x00000200 #define EIG1_EB_OFFSET 8 #define EIG1_EB_MASK 0x00000100 #define CMM1_EB_OFFSET 7 #define CMM1_EB_MASK 0x00000080 #define PHY_ANA_EB_OFFSET 6 #define PHY_ANA_EB_MASK 0x00000040 #define AFFT0_EB_OFFSET 5 #define AFFT0_EB_MASK 0x00000020 #define CHOL0_EB_OFFSET 4 #define CHOL0_EB_MASK 0x00000010 #define EIG0_EB_OFFSET 3 #define EIG0_EB_MASK 0x00000008 #define CMM0_EB_OFFSET 2 #define CMM0_EB_MASK 0x00000004 #define EPARSER_EB_OFFSET 1 #define EPARSER_EB_MASK 0x00000002 #define BUSMON_EB_OFFSET 0 #define BUSMON_EB_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG3_ADDR 0x00B8 #define USB_SOFT_RST_OFFSET 11 #define USB_SOFT_RST_MASK 0x00000800 #define AFFT1_SOFT_RST_OFFSET 10 #define AFFT1_SOFT_RST_MASK 0x00000400 #define CHOL1_SOFT_RST_OFFSET 9 #define CHOL1_SOFT_RST_MASK 0x00000200 #define EIG1_SOFT_RST_OFFSET 8 #define EIG1_SOFT_RST_MASK 0x00000100 #define CMM1_SOFT_RST_OFFSET 7 #define CMM1_SOFT_RST_MASK 0x00000080 #define AFFT0_SOFT_RST_OFFSET 5 #define AFFT0_SOFT_RST_MASK 0x00000020 #define CHOL0_SOFT_RST_OFFSET 4 #define CHOL0_SOFT_RST_MASK 0x00000010 #define EIG0_SOFT_RST_OFFSET 3 #define EIG0_SOFT_RST_MASK 0x00000008 #define CMM0_SOFT_RST_OFFSET 2 #define CMM0_SOFT_RST_MASK 0x00000004 #define EPARSER_SOFT_RST_OFFSET 1 #define EPARSER_SOFT_RST_MASK 0x00000002 #define BUSMON_SOFT_RST_OFFSET 0 #define BUSMON_SOFT_RST_MASK 0x00000001 //----------------------------------- #define CFG_SMC_IO_SEL_REG_ADDR 0x00BC #define SMC_IO_SEL_OFFSET 0 #define SMC_IO_SEL_MASK 0x00000001 //----------------------------------- #define CFG_DMC_CACHE_FLUSH_SADDR_ADDR 0x00C0 #define DMC_C_FLUSH_SADDR_OFFSET 0 #define DMC_C_FLUSH_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMC_CACHE_FLUSH_EADDR_ADDR 0x00C4 #define DMC_C_FLUSH_EADDR_OFFSET 0 #define DMC_C_FLUSH_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMC_CACHE_CTRL_ADDR 0x00C8 #define DMC_C_MODE_OFFSET 20 #define DMC_C_MODE_MASK 0x00100000 #define DMC_C_WR_AUTO_LOAD_OFFSET 19 #define DMC_C_WR_AUTO_LOAD_MASK 0x00080000 #define DMC_C_SOFT_RST_OFFSET 18 #define DMC_C_SOFT_RST_MASK 0x00040000 #define DMC_C_EB_OFFSET 17 #define DMC_C_EB_MASK 0x00020000 #define DMC_C_FLUSH_INVALID_MODE_OFFSET 16 #define DMC_C_FLUSH_INVALID_MODE_MASK 0x00010000 #define DMC_C_FSM_ST_OFFSET 8 #define DMC_C_FSM_ST_MASK 0x00000F00 #define DMC_C_CLEAR_DONE_OFFSET 5 #define DMC_C_CLEAR_DONE_MASK 0x00000020 #define DMC_C_FLUSH_DONE_OFFSET 4 #define DMC_C_FLUSH_DONE_MASK 0x00000010 #define DMC_C_CLEAR_ENA_OFFSET 1 #define DMC_C_CLEAR_ENA_MASK 0x00000002 #define DMC_C_FLUSH_ENA_OFFSET 0 #define DMC_C_FLUSH_ENA_MASK 0x00000001 //----------------------------------- #define CFG_ICACHE1_FLUSH_SADDR_ADDR 0x00CC #define IC1_FLUSH_SADDR_OFFSET 0 #define IC1_FLUSH_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE1_FLUSH_EADDR_ADDR 0x00D0 #define IC1_FLUSH_EADDR_OFFSET 0 #define IC1_FLUSH_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE1_CTRL_ADDR 0x00D8 #define ICACHE1_MODE_OFFSET 22 #define ICACHE1_MODE_MASK 0x00400000 #define ICACHE1_HIT_ERR_OFFSET 21 #define ICACHE1_HIT_ERR_MASK 0x00200000 #define ICACHE1_DMC_MODE_OFFSET 20 #define ICACHE1_DMC_MODE_MASK 0x00100000 #define ICACHE1_WR_AUTO_LOAD_OFFSET 19 #define ICACHE1_WR_AUTO_LOAD_MASK 0x00080000 #define ICACHE1_SOFT_RST_OFFSET 18 #define ICACHE1_SOFT_RST_MASK 0x00040000 #define ICACHE1_EB_OFFSET 17 #define ICACHE1_EB_MASK 0x00020000 #define ICACHE1_FLUSH_INVALID_MODE_OFFSET 16 #define ICACHE1_FLUSH_INVALID_MODE_MASK 0x00010000 #define ICACHE1_FSM_ST_OFFSET 8 #define ICACHE1_FSM_ST_MASK 0x00000F00 #define ICACHE1_CLEAR_DONE_OFFSET 5 #define ICACHE1_CLEAR_DONE_MASK 0x00000020 #define ICACHE1_FLUSH_DONE_OFFSET 4 #define ICACHE1_FLUSH_DONE_MASK 0x00000010 #define ICACHE1_CLEAR_ENA_OFFSET 1 #define ICACHE1_CLEAR_ENA_MASK 0x00000002 #define ICACHE1_FLUSH_ENA_OFFSET 0 #define ICACHE1_FLUSH_ENA_MASK 0x00000001 //----------------------------------- #define CFG_AHB_LP_CTRL1_ADDR 0x00DC #define DTOP_WAKEUP_PMU_OFFSET 3 #define DTOP_WAKEUP_PMU_MASK 0x00000008 #define DTOP_ACCESS_PMU_OFFSET 2 #define DTOP_ACCESS_PMU_MASK 0x00000004 #define PD_DTOP_LIGHT_SLEEP_EB_OFFSET 1 #define PD_DTOP_LIGHT_SLEEP_EB_MASK 0x00000002 #define PD_DTOP_DEEP_SLEEP_EB_OFFSET 0 #define PD_DTOP_DEEP_SLEEP_EB_MASK 0x00000001 //----------------------------------- #define CFG_AHB_LP_STATUS_ADDR 0x00E0 #define RV5_CORE2_ENA_OFFSET 14 #define RV5_CORE2_ENA_MASK 0x00004000 #define RV5_CORE1_ENA_OFFSET 13 #define RV5_CORE1_ENA_MASK 0x00002000 #define RV5_CORE0_ENA_OFFSET 12 #define RV5_CORE0_ENA_MASK 0x00001000 #define AP_SYS_STOP_OFFSET 11 #define AP_SYS_STOP_MASK 0x00000800 #define SEC_SYS_STOP_OFFSET 10 #define SEC_SYS_STOP_MASK 0x00000400 #define RV5_CORE2_STOP_OFFSET 9 #define RV5_CORE2_STOP_MASK 0x00000200 #define RV5_CORE1_STOP_OFFSET 8 #define RV5_CORE1_STOP_MASK 0x00000100 #define RV5_CORE0_STOP_OFFSET 7 #define RV5_CORE0_STOP_MASK 0x00000080 #define BUS_STOP_OFFSET 6 #define BUS_STOP_MASK 0x00000040 #define AP_DEEP_SLEEP_OFFSET 5 #define AP_DEEP_SLEEP_MASK 0x00000020 #define SEC_DEEP_SLEEP_OFFSET 4 #define SEC_DEEP_SLEEP_MASK 0x00000010 #define SRC_CHIP_DEEP_SLEEP_OFFSET 3 #define SRC_CHIP_DEEP_SLEEP_MASK 0x00000008 #define CHIP_DEEP_SLEEP_OFFSET 2 #define CHIP_DEEP_SLEEP_MASK 0x00000004 #define CHIP_DEEP_SLEEP_IO_OFFSET 1 #define CHIP_DEEP_SLEEP_IO_MASK 0x00000002 #define CHIP_DEEP_SLEEP_WP_OFFSET 0 #define CHIP_DEEP_SLEEP_WP_MASK 0x00000001 //----------------------------------- #define CFG_AHB_MEM_CTRL1_ADDR 0x00E4 #define IIS4_RAM_FORCE_ON_OFFSET 0 #define IIS4_RAM_FORCE_ON_MASK 0x00000001 //----------------------------------- #define CFG_IC0_MISS_CNT_CFG_ADDR 0x00E8 #define IC0_MISS_CNT_CLR_OFFSET 29 #define IC0_MISS_CNT_CLR_MASK 0x20000000 #define IC0_MISS_CNT_ENA_OFFSET 28 #define IC0_MISS_CNT_ENA_MASK 0x10000000 #define IC0_MISS_CNT_OFFSET 0 #define IC0_MISS_CNT_MASK 0x0FFFFFFF //----------------------------------- #define CFG_IC1_MISS_CNT_CFG_ADDR 0x00EC #define IC1_MISS_CNT_CLR_OFFSET 29 #define IC1_MISS_CNT_CLR_MASK 0x20000000 #define IC1_MISS_CNT_ENA_OFFSET 28 #define IC1_MISS_CNT_ENA_MASK 0x10000000 #define IC1_MISS_CNT_OFFSET 0 #define IC1_MISS_CNT_MASK 0x0FFFFFFF //----------------------------------- #define CFG_DC_MISS_CNT_CFG_ADDR 0x00F0 #define DC_MISS_CNT_CLR_OFFSET 29 #define DC_MISS_CNT_CLR_MASK 0x20000000 #define DC_MISS_CNT_ENA_OFFSET 28 #define DC_MISS_CNT_ENA_MASK 0x10000000 #define DC_MISS_CNT_OFFSET 0 #define DC_MISS_CNT_MASK 0x0FFFFFFF //----------------------------------- #define CFG_DMC_CACHE1_FLUSH_SADDR_ADDR 0x00F4 #define DMC_C1_FLUSH_SADDR_OFFSET 0 #define DMC_C1_FLUSH_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMC_CACHE1_FLUSH_EADDR_ADDR 0x00F8 #define DMC_C1_FLUSH_EADDR_OFFSET 0 #define DMC_C1_FLUSH_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DMC_CACHE1_CTRL_ADDR 0x00FC #define DMC_C1_MODE_OFFSET 20 #define DMC_C1_MODE_MASK 0x00100000 #define DMC_C1_WR_AUTO_LOAD_OFFSET 19 #define DMC_C1_WR_AUTO_LOAD_MASK 0x00080000 #define DMC_C1_SOFT_RST_OFFSET 18 #define DMC_C1_SOFT_RST_MASK 0x00040000 #define DMC_C1_EB_OFFSET 17 #define DMC_C1_EB_MASK 0x00020000 #define DMC_C1_FLUSH_INVALID_MODE_OFFSET 16 #define DMC_C1_FLUSH_INVALID_MODE_MASK 0x00010000 #define DMC_C1_FSM_ST_OFFSET 8 #define DMC_C1_FSM_ST_MASK 0x00000F00 #define DMC_C1_CLEAR_DONE_OFFSET 5 #define DMC_C1_CLEAR_DONE_MASK 0x00000020 #define DMC_C1_FLUSH_DONE_OFFSET 4 #define DMC_C1_FLUSH_DONE_MASK 0x00000010 #define DMC_C1_CLEAR_ENA_OFFSET 1 #define DMC_C1_CLEAR_ENA_MASK 0x00000002 #define DMC_C1_FLUSH_ENA_OFFSET 0 #define DMC_C1_FLUSH_ENA_MASK 0x00000001 //----------------------------------- #define CFG_SLV_MON_CFG0_ADDR 0x0100 #define SLV_MON_SEL_OFFSET 8 #define SLV_MON_SEL_MASK 0x00000700 #define SLV_MON_ERR_RW_OFFSET 5 #define SLV_MON_ERR_RW_MASK 0x00000020 #define RAM4_MON_ENA_OFFSET 4 #define RAM4_MON_ENA_MASK 0x00000010 #define RAM3_MON_ENA_OFFSET 3 #define RAM3_MON_ENA_MASK 0x00000008 #define DC_MON_ENA_OFFSET 2 #define DC_MON_ENA_MASK 0x00000004 #define IC1_MON_ENA_OFFSET 1 #define IC1_MON_ENA_MASK 0x00000002 #define IC0_MON_ENA_OFFSET 0 #define IC0_MON_ENA_MASK 0x00000001 //----------------------------------- #define CFG_SLV_MON_STS1_ADDR 0x0104 #define SLV_MON_ERR_ADDR_OFFSET 0 #define SLV_MON_ERR_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SLV_MON_STS2_ADDR 0x0108 #define SLV_MON_ERR_MST_ID_OFFSET 0 #define SLV_MON_ERR_MST_ID_MASK 0xFFFFFFFF //----------------------------------- #define CFG_SLV_MON_INT_RAW_ADDR 0x010c #define RAM4_MON_ERR_INT_RAW_OFFSET 4 #define RAM4_MON_ERR_INT_RAW_MASK 0x00000010 #define RAM3_MON_ERR_INT_RAW_OFFSET 3 #define RAM3_MON_ERR_INT_RAW_MASK 0x00000008 #define DC_MON_ERR_INT_RAW_OFFSET 2 #define DC_MON_ERR_INT_RAW_MASK 0x00000004 #define IC1_MON_ERR_INT_RAW_OFFSET 1 #define IC1_MON_ERR_INT_RAW_MASK 0x00000002 #define IC0_MON_ERR_INT_RAW_OFFSET 0 #define IC0_MON_ERR_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_SLV_MON_INT_ENA_ADDR 0x0110 #define RAM4_MON_ERR_INT_ENA_OFFSET 4 #define RAM4_MON_ERR_INT_ENA_MASK 0x00000010 #define RAM3_MON_ERR_INT_ENA_OFFSET 3 #define RAM3_MON_ERR_INT_ENA_MASK 0x00000008 #define DC_MON_ERR_INT_ENA_OFFSET 2 #define DC_MON_ERR_INT_ENA_MASK 0x00000004 #define IC1_MON_ERR_INT_ENA_OFFSET 1 #define IC1_MON_ERR_INT_ENA_MASK 0x00000002 #define IC0_MON_ERR_INT_ENA_OFFSET 0 #define IC0_MON_ERR_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_SLV_MON_INT_STS_ADDR 0x0114 #define RAM4_MON_ERR_INT_STS_OFFSET 4 #define RAM4_MON_ERR_INT_STS_MASK 0x00000010 #define RAM3_MON_ERR_INT_STS_OFFSET 3 #define RAM3_MON_ERR_INT_STS_MASK 0x00000008 #define DC_MON_ERR_INT_STS_OFFSET 2 #define DC_MON_ERR_INT_STS_MASK 0x00000004 #define IC1_MON_ERR_INT_STS_OFFSET 1 #define IC1_MON_ERR_INT_STS_MASK 0x00000002 #define IC0_MON_ERR_INT_STS_OFFSET 0 #define IC0_MON_ERR_INT_STS_MASK 0x00000001 //----------------------------------- #define CFG_SLV_MON_INT_CLR_ADDR 0x0118 #define RAM4_MON_ERR_INT_CLR_OFFSET 4 #define RAM4_MON_ERR_INT_CLR_MASK 0x00000010 #define RAM3_MON_ERR_INT_CLR_OFFSET 3 #define RAM3_MON_ERR_INT_CLR_MASK 0x00000008 #define DC_MON_ERR_INT_CLR_OFFSET 2 #define DC_MON_ERR_INT_CLR_MASK 0x00000004 #define IC1_MON_ERR_INT_CLR_OFFSET 1 #define IC1_MON_ERR_INT_CLR_MASK 0x00000002 #define IC0_MON_ERR_INT_CLR_OFFSET 0 #define IC0_MON_ERR_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_RAM4_MON_SADDR_ADDR 0x0120 #define RAM4_MON_SADDR_OFFSET 0 #define RAM4_MON_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RAM4_MON_EADDR_ADDR 0x0124 #define RAM4_MON_EADDR_OFFSET 0 #define RAM4_MON_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RAM4_ACC_SADDR_ADDR 0x0128 #define RAM4_ACC_SADDR_OFFSET 0 #define RAM4_ACC_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RAM4_ACC_EADDR_ADDR 0x012c #define RAM4_ACC_EADDR_OFFSET 0 #define RAM4_ACC_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RAM3_MON_SADDR_ADDR 0x0130 #define RAM3_MON_SADDR_OFFSET 0 #define RAM3_MON_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RAM3_MON_EADDR_ADDR 0x0134 #define RAM3_MON_EADDR_OFFSET 0 #define RAM3_MON_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RAM3_ACC_SADDR_ADDR 0x0138 #define RAM3_ACC_SADDR_OFFSET 0 #define RAM3_ACC_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_RAM3_ACC_EADDR_ADDR 0x013c #define RAM3_ACC_EADDR_OFFSET 0 #define RAM3_ACC_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DCACHE_MON_SADDR_ADDR 0x0140 #define DC_MON_SADDR_OFFSET 0 #define DC_MON_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DCACHE_MON_EADDR_ADDR 0x0144 #define DC_MON_EADDR_OFFSET 0 #define DC_MON_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DCACHE_ACC_SADDR_ADDR 0x0148 #define DC_ACC_SADDR_OFFSET 0 #define DC_ACC_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_DCACHE_ACC_EADDR_ADDR 0x014c #define DC_ACC_EADDR_OFFSET 0 #define DC_ACC_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE1_MON_SADDR_ADDR 0x0150 #define IC1_MON_SADDR_OFFSET 0 #define IC1_MON_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE1_MON_EADDR_ADDR 0x0154 #define IC1_MON_EADDR_OFFSET 0 #define IC1_MON_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE1_ACC_SADDR_ADDR 0x0158 #define IC1_ACC_SADDR_OFFSET 0 #define IC1_ACC_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE1_ACC_EADDR_ADDR 0x015c #define IC1_ACC_EADDR_OFFSET 0 #define IC1_ACC_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE0_MON_SADDR_ADDR 0x0160 #define IC0_MON_SADDR_OFFSET 0 #define IC0_MON_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE0_MON_EADDR_ADDR 0x0164 #define IC0_MON_EADDR_OFFSET 0 #define IC0_MON_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE0_ACC_SADDR_ADDR 0x0168 #define IC0_ACC_SADDR_OFFSET 0 #define IC0_ACC_SADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_ICACHE0_ACC_EADDR_ADDR 0x016c #define IC0_ACC_EADDR_OFFSET 0 #define IC0_ACC_EADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_MTX_ERR_CTRL_ADDR 0x0170 #define MST_ERR_RW_OFFSET 8 #define MST_ERR_RW_MASK 0x00000100 #define MTX_MST_SEL_OFFSET 0 #define MTX_MST_SEL_MASK 0x0000001F //----------------------------------- #define CFG_AHB_MST_ERR_ADDR_ADDR 0x0174 #define MST_ERR_ADDR_OFFSET 0 #define MST_ERR_ADDR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_AHB_MST_ERR_INT_RAW_ADDR 0x00178 #define M31_ERR_INT_RAW_OFFSET 31 #define M31_ERR_INT_RAW_MASK 0x80000000 #define M30_ERR_INT_RAW_OFFSET 30 #define M30_ERR_INT_RAW_MASK 0x40000000 #define M29_ERR_INT_RAW_OFFSET 29 #define M29_ERR_INT_RAW_MASK 0x20000000 #define M28_ERR_INT_RAW_OFFSET 28 #define M28_ERR_INT_RAW_MASK 0x10000000 #define M27_ERR_INT_RAW_OFFSET 27 #define M27_ERR_INT_RAW_MASK 0x08000000 #define M26_ERR_INT_RAW_OFFSET 26 #define M26_ERR_INT_RAW_MASK 0x04000000 #define M25_ERR_INT_RAW_OFFSET 25 #define M25_ERR_INT_RAW_MASK 0x02000000 #define M24_ERR_INT_RAW_OFFSET 24 #define M24_ERR_INT_RAW_MASK 0x01000000 #define M23_ERR_INT_RAW_OFFSET 23 #define M23_ERR_INT_RAW_MASK 0x00800000 #define M22_ERR_INT_RAW_OFFSET 22 #define M22_ERR_INT_RAW_MASK 0x00400000 #define M21_ERR_INT_RAW_OFFSET 21 #define M21_ERR_INT_RAW_MASK 0x00200000 #define M20_ERR_INT_RAW_OFFSET 20 #define M20_ERR_INT_RAW_MASK 0x00100000 #define M19_ERR_INT_RAW_OFFSET 19 #define M19_ERR_INT_RAW_MASK 0x00080000 #define M18_ERR_INT_RAW_OFFSET 18 #define M18_ERR_INT_RAW_MASK 0x00040000 #define M17_ERR_INT_RAW_OFFSET 17 #define M17_ERR_INT_RAW_MASK 0x00020000 #define M16_ERR_INT_RAW_OFFSET 16 #define M16_ERR_INT_RAW_MASK 0x00010000 #define M15_ERR_INT_RAW_OFFSET 15 #define M15_ERR_INT_RAW_MASK 0x00008000 #define M14_ERR_INT_RAW_OFFSET 14 #define M14_ERR_INT_RAW_MASK 0x00004000 #define M13_ERR_INT_RAW_OFFSET 13 #define M13_ERR_INT_RAW_MASK 0x00002000 #define M12_ERR_INT_RAW_OFFSET 12 #define M12_ERR_INT_RAW_MASK 0x00001000 #define M11_ERR_INT_RAW_OFFSET 11 #define M11_ERR_INT_RAW_MASK 0x00000800 #define M10_ERR_INT_RAW_OFFSET 10 #define M10_ERR_INT_RAW_MASK 0x00000400 #define M9_ERR_INT_RAW_OFFSET 9 #define M9_ERR_INT_RAW_MASK 0x00000200 #define M8_ERR_INT_RAW_OFFSET 8 #define M8_ERR_INT_RAW_MASK 0x00000100 #define M7_ERR_INT_RAW_OFFSET 7 #define M7_ERR_INT_RAW_MASK 0x00000080 #define M6_ERR_INT_RAW_OFFSET 6 #define M6_ERR_INT_RAW_MASK 0x00000040 #define M5_ERR_INT_RAW_OFFSET 5 #define M5_ERR_INT_RAW_MASK 0x00000020 #define M4_ERR_INT_RAW_OFFSET 4 #define M4_ERR_INT_RAW_MASK 0x00000010 #define M3_ERR_INT_RAW_OFFSET 3 #define M3_ERR_INT_RAW_MASK 0x00000008 #define M2_ERR_INT_RAW_OFFSET 2 #define M2_ERR_INT_RAW_MASK 0x00000004 #define M1_ERR_INT_RAW_OFFSET 1 #define M1_ERR_INT_RAW_MASK 0x00000002 #define M0_ERR_INT_RAW_OFFSET 0 #define M0_ERR_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_AHB_MST_ERR_INT_ENA_ADDR 0x0017c #define M31_ERR_INT_ENA_OFFSET 31 #define M31_ERR_INT_ENA_MASK 0x80000000 #define M30_ERR_INT_ENA_OFFSET 30 #define M30_ERR_INT_ENA_MASK 0x40000000 #define M29_ERR_INT_ENA_OFFSET 29 #define M29_ERR_INT_ENA_MASK 0x20000000 #define M28_ERR_INT_ENA_OFFSET 28 #define M28_ERR_INT_ENA_MASK 0x10000000 #define M27_ERR_INT_ENA_OFFSET 27 #define M27_ERR_INT_ENA_MASK 0x08000000 #define M26_ERR_INT_ENA_OFFSET 26 #define M26_ERR_INT_ENA_MASK 0x04000000 #define M25_ERR_INT_ENA_OFFSET 25 #define M25_ERR_INT_ENA_MASK 0x02000000 #define M24_ERR_INT_ENA_OFFSET 24 #define M24_ERR_INT_ENA_MASK 0x01000000 #define M23_ERR_INT_ENA_OFFSET 23 #define M23_ERR_INT_ENA_MASK 0x00800000 #define M22_ERR_INT_ENA_OFFSET 22 #define M22_ERR_INT_ENA_MASK 0x00400000 #define M21_ERR_INT_ENA_OFFSET 21 #define M21_ERR_INT_ENA_MASK 0x00200000 #define M20_ERR_INT_ENA_OFFSET 20 #define M20_ERR_INT_ENA_MASK 0x00100000 #define M19_ERR_INT_ENA_OFFSET 19 #define M19_ERR_INT_ENA_MASK 0x00080000 #define M18_ERR_INT_ENA_OFFSET 18 #define M18_ERR_INT_ENA_MASK 0x00040000 #define M17_ERR_INT_ENA_OFFSET 17 #define M17_ERR_INT_ENA_MASK 0x00020000 #define M16_ERR_INT_ENA_OFFSET 16 #define M16_ERR_INT_ENA_MASK 0x00010000 #define M15_ERR_INT_ENA_OFFSET 15 #define M15_ERR_INT_ENA_MASK 0x00008000 #define M14_ERR_INT_ENA_OFFSET 14 #define M14_ERR_INT_ENA_MASK 0x00004000 #define M13_ERR_INT_ENA_OFFSET 13 #define M13_ERR_INT_ENA_MASK 0x00002000 #define M12_ERR_INT_ENA_OFFSET 12 #define M12_ERR_INT_ENA_MASK 0x00001000 #define M11_ERR_INT_ENA_OFFSET 11 #define M11_ERR_INT_ENA_MASK 0x00000800 #define M10_ERR_INT_ENA_OFFSET 10 #define M10_ERR_INT_ENA_MASK 0x00000400 #define M9_ERR_INT_ENA_OFFSET 9 #define M9_ERR_INT_ENA_MASK 0x00000200 #define M8_ERR_INT_ENA_OFFSET 8 #define M8_ERR_INT_ENA_MASK 0x00000100 #define M7_ERR_INT_ENA_OFFSET 7 #define M7_ERR_INT_ENA_MASK 0x00000080 #define M6_ERR_INT_ENA_OFFSET 6 #define M6_ERR_INT_ENA_MASK 0x00000040 #define M5_ERR_INT_ENA_OFFSET 5 #define M5_ERR_INT_ENA_MASK 0x00000020 #define M4_ERR_INT_ENA_OFFSET 4 #define M4_ERR_INT_ENA_MASK 0x00000010 #define M3_ERR_INT_ENA_OFFSET 3 #define M3_ERR_INT_ENA_MASK 0x00000008 #define M2_ERR_INT_ENA_OFFSET 2 #define M2_ERR_INT_ENA_MASK 0x00000004 #define M1_ERR_INT_ENA_OFFSET 1 #define M1_ERR_INT_ENA_MASK 0x00000002 #define M0_ERR_INT_ENA_OFFSET 0 #define M0_ERR_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_AHB_MST_ERR_INT_STS_ADDR 0x00180 #define M31_ERR_INT_STS_OFFSET 31 #define M31_ERR_INT_STS_MASK 0x80000000 #define M30_ERR_INT_STS_OFFSET 30 #define M30_ERR_INT_STS_MASK 0x40000000 #define M29_ERR_INT_STS_OFFSET 29 #define M29_ERR_INT_STS_MASK 0x20000000 #define M28_ERR_INT_STS_OFFSET 28 #define M28_ERR_INT_STS_MASK 0x10000000 #define M27_ERR_INT_STS_OFFSET 27 #define M27_ERR_INT_STS_MASK 0x08000000 #define M26_ERR_INT_STS_OFFSET 26 #define M26_ERR_INT_STS_MASK 0x04000000 #define M25_ERR_INT_STS_OFFSET 25 #define M25_ERR_INT_STS_MASK 0x02000000 #define M24_ERR_INT_STS_OFFSET 24 #define M24_ERR_INT_STS_MASK 0x01000000 #define M23_ERR_INT_STS_OFFSET 23 #define M23_ERR_INT_STS_MASK 0x00800000 #define M22_ERR_INT_STS_OFFSET 22 #define M22_ERR_INT_STS_MASK 0x00400000 #define M21_ERR_INT_STS_OFFSET 21 #define M21_ERR_INT_STS_MASK 0x00200000 #define M20_ERR_INT_STS_OFFSET 20 #define M20_ERR_INT_STS_MASK 0x00100000 #define M19_ERR_INT_STS_OFFSET 19 #define M19_ERR_INT_STS_MASK 0x00080000 #define M18_ERR_INT_STS_OFFSET 18 #define M18_ERR_INT_STS_MASK 0x00040000 #define M17_ERR_INT_STS_OFFSET 17 #define M17_ERR_INT_STS_MASK 0x00020000 #define M16_ERR_INT_STS_OFFSET 16 #define M16_ERR_INT_STS_MASK 0x00010000 #define M15_ERR_INT_STS_OFFSET 15 #define M15_ERR_INT_STS_MASK 0x00008000 #define M14_ERR_INT_STS_OFFSET 14 #define M14_ERR_INT_STS_MASK 0x00004000 #define M13_ERR_INT_STS_OFFSET 13 #define M13_ERR_INT_STS_MASK 0x00002000 #define M12_ERR_INT_STS_OFFSET 12 #define M12_ERR_INT_STS_MASK 0x00001000 #define M11_ERR_INT_STS_OFFSET 11 #define M11_ERR_INT_STS_MASK 0x00000800 #define M10_ERR_INT_STS_OFFSET 10 #define M10_ERR_INT_STS_MASK 0x00000400 #define M9_ERR_INT_STS_OFFSET 9 #define M9_ERR_INT_STS_MASK 0x00000200 #define M8_ERR_INT_STS_OFFSET 8 #define M8_ERR_INT_STS_MASK 0x00000100 #define M7_ERR_INT_STS_OFFSET 7 #define M7_ERR_INT_STS_MASK 0x00000080 #define M6_ERR_INT_STS_OFFSET 6 #define M6_ERR_INT_STS_MASK 0x00000040 #define M5_ERR_INT_STS_OFFSET 5 #define M5_ERR_INT_STS_MASK 0x00000020 #define M4_ERR_INT_STS_OFFSET 4 #define M4_ERR_INT_STS_MASK 0x00000010 #define M3_ERR_INT_STS_OFFSET 3 #define M3_ERR_INT_STS_MASK 0x00000008 #define M2_ERR_INT_STS_OFFSET 2 #define M2_ERR_INT_STS_MASK 0x00000004 #define M1_ERR_INT_STS_OFFSET 1 #define M1_ERR_INT_STS_MASK 0x00000002 #define M0_ERR_INT_STS_OFFSET 0 #define M0_ERR_INT_STS_MASK 0x00000001 //----------------------------------- #define CFG_AHB_MST_ERR_INT_CLR_ADDR 0x00184 #define M31_ERR_INT_CLR_OFFSET 31 #define M31_ERR_INT_CLR_MASK 0x80000000 #define M30_ERR_INT_CLR_OFFSET 30 #define M30_ERR_INT_CLR_MASK 0x40000000 #define M29_ERR_INT_CLR_OFFSET 29 #define M29_ERR_INT_CLR_MASK 0x20000000 #define M28_ERR_INT_CLR_OFFSET 28 #define M28_ERR_INT_CLR_MASK 0x10000000 #define M27_ERR_INT_CLR_OFFSET 27 #define M27_ERR_INT_CLR_MASK 0x08000000 #define M26_ERR_INT_CLR_OFFSET 26 #define M26_ERR_INT_CLR_MASK 0x04000000 #define M25_ERR_INT_CLR_OFFSET 25 #define M25_ERR_INT_CLR_MASK 0x02000000 #define M24_ERR_INT_CLR_OFFSET 24 #define M24_ERR_INT_CLR_MASK 0x01000000 #define M23_ERR_INT_CLR_OFFSET 23 #define M23_ERR_INT_CLR_MASK 0x00800000 #define M22_ERR_INT_CLR_OFFSET 22 #define M22_ERR_INT_CLR_MASK 0x00400000 #define M21_ERR_INT_CLR_OFFSET 21 #define M21_ERR_INT_CLR_MASK 0x00200000 #define M20_ERR_INT_CLR_OFFSET 20 #define M20_ERR_INT_CLR_MASK 0x00100000 #define M19_ERR_INT_CLR_OFFSET 19 #define M19_ERR_INT_CLR_MASK 0x00080000 #define M18_ERR_INT_CLR_OFFSET 18 #define M18_ERR_INT_CLR_MASK 0x00040000 #define M17_ERR_INT_CLR_OFFSET 17 #define M17_ERR_INT_CLR_MASK 0x00020000 #define M16_ERR_INT_CLR_OFFSET 16 #define M16_ERR_INT_CLR_MASK 0x00010000 #define M15_ERR_INT_CLR_OFFSET 15 #define M15_ERR_INT_CLR_MASK 0x00008000 #define M14_ERR_INT_CLR_OFFSET 14 #define M14_ERR_INT_CLR_MASK 0x00004000 #define M13_ERR_INT_CLR_OFFSET 13 #define M13_ERR_INT_CLR_MASK 0x00002000 #define M12_ERR_INT_CLR_OFFSET 12 #define M12_ERR_INT_CLR_MASK 0x00001000 #define M11_ERR_INT_CLR_OFFSET 11 #define M11_ERR_INT_CLR_MASK 0x00000800 #define M10_ERR_INT_CLR_OFFSET 10 #define M10_ERR_INT_CLR_MASK 0x00000400 #define M9_ERR_INT_CLR_OFFSET 9 #define M9_ERR_INT_CLR_MASK 0x00000200 #define M8_ERR_INT_CLR_OFFSET 8 #define M8_ERR_INT_CLR_MASK 0x00000100 #define M7_ERR_INT_CLR_OFFSET 7 #define M7_ERR_INT_CLR_MASK 0x00000080 #define M6_ERR_INT_CLR_OFFSET 6 #define M6_ERR_INT_CLR_MASK 0x00000040 #define M5_ERR_INT_CLR_OFFSET 5 #define M5_ERR_INT_CLR_MASK 0x00000020 #define M4_ERR_INT_CLR_OFFSET 4 #define M4_ERR_INT_CLR_MASK 0x00000010 #define M3_ERR_INT_CLR_OFFSET 3 #define M3_ERR_INT_CLR_MASK 0x00000008 #define M2_ERR_INT_CLR_OFFSET 2 #define M2_ERR_INT_CLR_MASK 0x00000004 #define M1_ERR_INT_CLR_OFFSET 1 #define M1_ERR_INT_CLR_MASK 0x00000002 #define M0_ERR_INT_CLR_OFFSET 0 #define M0_ERR_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_AHB_MIPI_DBG_CFG_ADDR 0x00188 #define MIPI_DBG_SEL_OFFSET 0 #define MIPI_DBG_SEL_MASK 0x000000FF //----------------------------------- #define CFG_AHB_CPU_GATE_CFG_ADDR 0x0018C #define RV5_CORE2_SIMD_EB_OFFSET 9 #define RV5_CORE2_SIMD_EB_MASK 0x00000200 #define RV5_CORE0_SIMD_EB_OFFSET 8 #define RV5_CORE0_SIMD_EB_MASK 0x00000100 #define RV5_CORE2_BTB_EB_OFFSET 1 #define RV5_CORE2_BTB_EB_MASK 0x00000002 #define RV5_CORE0_BTB_EB_OFFSET 0 #define RV5_CORE0_BTB_EB_MASK 0x00000001 //----------------------------------- #define CFG_AHB_CPU0_IEXPT_CFG0_ADDR 0x00190 #define RV5_CORE0_I_EXPT_MASK_OFFSET 24 #define RV5_CORE0_I_EXPT_MASK_MASK 0x01000000 #define RV5_CORE0_I_ACCESS_EN_OFFSET 0 #define RV5_CORE0_I_ACCESS_EN_MASK 0x0001FFFF //----------------------------------- #define CFG_AHB_CPU0_DEXPT_CFG0_ADDR 0x00194 #define RV5_CORE0_D_EXPT_MASK_OFFSET 24 #define RV5_CORE0_D_EXPT_MASK_MASK 0x3F000000 #define RV5_CORE0_D_ACCESS_EN_OFFSET 0 #define RV5_CORE0_D_ACCESS_EN_MASK 0x0001FFFF //----------------------------------- #define CFG_AHB_CPU2_IEXPT_CFG0_ADDR 0x00198 #define RV5_CORE2_I_EXPT_MASK_OFFSET 24 #define RV5_CORE2_I_EXPT_MASK_MASK 0x01000000 #define RV5_CORE2_I_ACCESS_EN_OFFSET 0 #define RV5_CORE2_I_ACCESS_EN_MASK 0x0001FFFF //----------------------------------- #define CFG_AHB_CPU2_DEXPT_CFG0_ADDR 0x0019C #define RV5_CORE2_D_EXPT_MASK_OFFSET 24 #define RV5_CORE2_D_EXPT_MASK_MASK 0x3F000000 #define RV5_CORE2_D_ACCESS_EN_OFFSET 0 #define RV5_CORE2_D_ACCESS_EN_MASK 0x0001FFFF //----------------------------------- #define CFG_AHB_REG0_SET_ADDR 0x001A0 #define MPRXCSI3_SOFT_RST_SET_OFFSET 31 #define MPRXCSI3_SOFT_RST_SET_MASK 0x80000000 #define MPRXCSI2_SOFT_RST_SET_OFFSET 30 #define MPRXCSI2_SOFT_RST_SET_MASK 0x40000000 #define MPRXCSI1_SOFT_RST_SET_OFFSET 29 #define MPRXCSI1_SOFT_RST_SET_MASK 0x20000000 #define MPRXCSI0_SOFT_RST_SET_OFFSET 28 #define MPRXCSI0_SOFT_RST_SET_MASK 0x10000000 #define SDIO0_SOFT_RST_SET_OFFSET 27 #define SDIO0_SOFT_RST_SET_MASK 0x08000000 #define SNAP_SHOT_SOFT_RST_SET_OFFSET 26 #define SNAP_SHOT_SOFT_RST_SET_MASK 0x04000000 #define SW_DMA1_SOFT_RST_SET_OFFSET 25 #define SW_DMA1_SOFT_RST_SET_MASK 0x02000000 #define SW_DMA0_SOFT_RST_SET_OFFSET 24 #define SW_DMA0_SOFT_RST_SET_MASK 0x01000000 #define PHY_ANA_SOFT_RST_SET_OFFSET 23 #define PHY_ANA_SOFT_RST_SET_MASK 0x00800000 #define PHY_REG_SOFT_RST_SET_OFFSET 22 #define PHY_REG_SOFT_RST_SET_MASK 0x00400000 #define PHY_SOFT_RST_SET_OFFSET 21 #define PHY_SOFT_RST_SET_MASK 0x00200000 #define MAC_REG_SOFT_RST_SET_OFFSET 20 #define MAC_REG_SOFT_RST_SET_MASK 0x00100000 #define MTX_TRANS_SOFT_RST_SET_OFFSET 19 #define MTX_TRANS_SOFT_RST_SET_MASK 0x00080000 #define MPTX_SOFT_RST_SET_OFFSET 18 #define MPTX_SOFT_RST_SET_MASK 0x00040000 #define RV5_CORE2_SOFT_RST_SET_OFFSET 17 #define RV5_CORE2_SOFT_RST_SET_MASK 0x00020000 #define RV5_CORE0_SOFT_RST_SET_OFFSET 16 #define RV5_CORE0_SOFT_RST_SET_MASK 0x00010000 #define DMC_SOFT_RST_SET_OFFSET 15 #define DMC_SOFT_RST_SET_MASK 0x00008000 #define DVP3_SOFT_RST_SET_OFFSET 14 #define DVP3_SOFT_RST_SET_MASK 0x00004000 #define DVP2_SOFT_RST_SET_OFFSET 13 #define DVP2_SOFT_RST_SET_MASK 0x00002000 #define DVP1_SOFT_RST_SET_OFFSET 12 #define DVP1_SOFT_RST_SET_MASK 0x00001000 #define DVP0_SOFT_RST_SET_OFFSET 11 #define DVP0_SOFT_RST_SET_MASK 0x00000800 #define FISHEYE_SOFT_RST_SET_OFFSET 10 #define FISHEYE_SOFT_RST_SET_MASK 0x00000400 #define ITR_SOFT_RST_SET_OFFSET 9 #define ITR_SOFT_RST_SET_MASK 0x00000200 #define AI_SOFT_RST_SET_OFFSET 7 #define AI_SOFT_RST_SET_MASK 0x00000080 #define GMACG_SOFT_RST_SET_OFFSET 6 #define GMACG_SOFT_RST_SET_MASK 0x00000040 #define GMAC_SOFT_RST_SET_OFFSET 5 #define GMAC_SOFT_RST_SET_MASK 0x00000020 #define DCACHE_SOFT_RST_SET_OFFSET 4 #define DCACHE_SOFT_RST_SET_MASK 0x00000010 #define ICACHE_SOFT_RST_SET_OFFSET 3 #define ICACHE_SOFT_RST_SET_MASK 0x00000008 #define NDFC_SOFT_RST_SET_OFFSET 2 #define NDFC_SOFT_RST_SET_MASK 0x00000004 #define ADA_SOFT_RST_SET_OFFSET 1 #define ADA_SOFT_RST_SET_MASK 0x00000002 #define MAC_SOFT_RST_SET_OFFSET 0 #define MAC_SOFT_RST_SET_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG0_CLR_ADDR 0x001A4 #define MPRXCSI3_SOFT_RST_CLR_OFFSET 31 #define MPRXCSI3_SOFT_RST_CLR_MASK 0x80000000 #define MPRXCSI2_SOFT_RST_CLR_OFFSET 30 #define MPRXCSI2_SOFT_RST_CLR_MASK 0x40000000 #define MPRXCSI1_SOFT_RST_CLR_OFFSET 29 #define MPRXCSI1_SOFT_RST_CLR_MASK 0x20000000 #define MPRXCSI0_SOFT_RST_CLR_OFFSET 28 #define MPRXCSI0_SOFT_RST_CLR_MASK 0x10000000 #define SDIO0_SOFT_RST_CLR_OFFSET 27 #define SDIO0_SOFT_RST_CLR_MASK 0x08000000 #define SNAP_SHOT_SOFT_RST_CLR_OFFSET 26 #define SNAP_SHOT_SOFT_RST_CLR_MASK 0x04000000 #define SW_DMA1_SOFT_RST_CLR_OFFSET 25 #define SW_DMA1_SOFT_RST_CLR_MASK 0x02000000 #define SW_DMA0_SOFT_RST_CLR_OFFSET 24 #define SW_DMA0_SOFT_RST_CLR_MASK 0x01000000 #define PHY_ANA_SOFT_RST_CLR_OFFSET 23 #define PHY_ANA_SOFT_RST_CLR_MASK 0x00800000 #define PHY_REG_SOFT_RST_CLR_OFFSET 22 #define PHY_REG_SOFT_RST_CLR_MASK 0x00400000 #define PHY_SOFT_RST_CLR_OFFSET 21 #define PHY_SOFT_RST_CLR_MASK 0x00200000 #define MAC_REG_SOFT_RST_CLR_OFFSET 20 #define MAC_REG_SOFT_RST_CLR_MASK 0x00100000 #define MTX_TRANS_SOFT_RST_CLR_OFFSET 19 #define MTX_TRANS_SOFT_RST_CLR_MASK 0x00080000 #define MPTX_SOFT_RST_CLR_OFFSET 18 #define MPTX_SOFT_RST_CLR_MASK 0x00040000 #define RV5_CORE2_SOFT_RST_CLR_OFFSET 17 #define RV5_CORE2_SOFT_RST_CLR_MASK 0x00020000 #define RV5_CORE0_SOFT_RST_CLR_OFFSET 16 #define RV5_CORE0_SOFT_RST_CLR_MASK 0x00010000 #define DMC_SOFT_RST_CLR_OFFSET 15 #define DMC_SOFT_RST_CLR_MASK 0x00008000 #define DVP3_SOFT_RST_CLR_OFFSET 14 #define DVP3_SOFT_RST_CLR_MASK 0x00004000 #define DVP2_SOFT_RST_CLR_OFFSET 13 #define DVP2_SOFT_RST_CLR_MASK 0x00002000 #define DVP1_SOFT_RST_CLR_OFFSET 12 #define DVP1_SOFT_RST_CLR_MASK 0x00001000 #define DVP0_SOFT_RST_CLR_OFFSET 11 #define DVP0_SOFT_RST_CLR_MASK 0x00000800 #define FISHEYE_SOFT_RST_CLR_OFFSET 10 #define FISHEYE_SOFT_RST_CLR_MASK 0x00000400 #define ITR_SOFT_RST_CLR_OFFSET 9 #define ITR_SOFT_RST_CLR_MASK 0x00000200 #define AI_SOFT_RST_CLR_OFFSET 7 #define AI_SOFT_RST_CLR_MASK 0x00000080 #define GMACG_SOFT_RST_CLR_OFFSET 6 #define GMACG_SOFT_RST_CLR_MASK 0x00000040 #define GMAC_SOFT_RST_CLR_OFFSET 5 #define GMAC_SOFT_RST_CLR_MASK 0x00000020 #define DCACHE_SOFT_RST_CLR_OFFSET 4 #define DCACHE_SOFT_RST_CLR_MASK 0x00000010 #define ICACHE_SOFT_RST_CLR_OFFSET 3 #define ICACHE_SOFT_RST_CLR_MASK 0x00000008 #define NDFC_SOFT_RST_CLR_OFFSET 2 #define NDFC_SOFT_RST_CLR_MASK 0x00000004 #define ADA_SOFT_RST_CLR_OFFSET 1 #define ADA_SOFT_RST_CLR_MASK 0x00000002 #define MAC_SOFT_RST_CLR_OFFSET 0 #define MAC_SOFT_RST_CLR_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG1_SET_ADDR 0x001A8 #define MPRXCSI3_EB_SET_OFFSET 31 #define MPRXCSI3_EB_SET_MASK 0x80000000 #define MPRXCSI2_EB_SET_OFFSET 30 #define MPRXCSI2_EB_SET_MASK 0x40000000 #define MPRXCSI1_EB_SET_OFFSET 29 #define MPRXCSI1_EB_SET_MASK 0x20000000 #define MPRXCSI0_EB_SET_OFFSET 28 #define MPRXCSI0_EB_SET_MASK 0x10000000 #define SDIO0_EB_SET_OFFSET 27 #define SDIO0_EB_SET_MASK 0x08000000 #define SNAP_SHOT_EB_SET_OFFSET 26 #define SNAP_SHOT_EB_SET_MASK 0x04000000 #define SW_DMA1_EB_SET_OFFSET 25 #define SW_DMA1_EB_SET_MASK 0x02000000 #define SW_DMA0_EB_SET_OFFSET 24 #define SW_DMA0_EB_SET_MASK 0x01000000 #define ITR_EB_SET_OFFSET 22 #define ITR_EB_SET_MASK 0x00400000 #define MPTX_EB_SET_OFFSET 21 #define MPTX_EB_SET_MASK 0x00200000 #define PHY_EB_SET_OFFSET 20 #define PHY_EB_SET_MASK 0x00100000 #define PERI_SYS_EB_SET_OFFSET 19 #define PERI_SYS_EB_SET_MASK 0x00080000 #define AHB_SYS_ENA_SET_OFFSET 18 #define AHB_SYS_ENA_SET_MASK 0x00040000 #define RV5_CORE2_EB_SET_OFFSET 17 #define RV5_CORE2_EB_SET_MASK 0x00020000 #define RV5_CORE0_EB_SET_OFFSET 16 #define RV5_CORE0_EB_SET_MASK 0x00010000 #define DMC_EB_SET_OFFSET 15 #define DMC_EB_SET_MASK 0x00008000 #define DVP3_EB_SET_OFFSET 14 #define DVP3_EB_SET_MASK 0x00004000 #define DVP2_EB_SET_OFFSET 13 #define DVP2_EB_SET_MASK 0x00002000 #define DVP1_EB_SET_OFFSET 12 #define DVP1_EB_SET_MASK 0x00001000 #define DVP0_EB_SET_OFFSET 11 #define DVP0_EB_SET_MASK 0x00000800 #define FISHEYE_EB_SET_OFFSET 10 #define FISHEYE_EB_SET_MASK 0x00000400 #define MTXTRANS_EB_SET_OFFSET 9 #define MTXTRANS_EB_SET_MASK 0x00000200 #define AI_EB_SET_OFFSET 7 #define AI_EB_SET_MASK 0x00000080 #define GMACG_EB_SET_OFFSET 6 #define GMACG_EB_SET_MASK 0x00000040 #define GMAC_EB_SET_OFFSET 5 #define GMAC_EB_SET_MASK 0x00000020 #define DCACHE_EB_SET_OFFSET 4 #define DCACHE_EB_SET_MASK 0x00000010 #define ICACHE_EB_SET_OFFSET 3 #define ICACHE_EB_SET_MASK 0x00000008 #define NDFC_EB_SET_OFFSET 2 #define NDFC_EB_SET_MASK 0x00000004 #define ADA_EB_SET_OFFSET 1 #define ADA_EB_SET_MASK 0x00000002 #define MAC_EB_SET_OFFSET 0 #define MAC_EB_SET_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG1_CLR_ADDR 0x001AC #define MPRXCSI3_EB_CLR_OFFSET 31 #define MPRXCSI3_EB_CLR_MASK 0x80000000 #define MPRXCSI2_EB_CLR_OFFSET 30 #define MPRXCSI2_EB_CLR_MASK 0x40000000 #define MPRXCSI1_EB_CLR_OFFSET 29 #define MPRXCSI1_EB_CLR_MASK 0x20000000 #define MPRXCSI0_EB_CLR_OFFSET 28 #define MPRXCSI0_EB_CLR_MASK 0x10000000 #define SDIO0_EB_CLR_OFFSET 27 #define SDIO0_EB_CLR_MASK 0x08000000 #define SNAP_SHOT_EB_CLR_OFFSET 26 #define SNAP_SHOT_EB_CLR_MASK 0x04000000 #define SW_DMA1_EB_CLR_OFFSET 25 #define SW_DMA1_EB_CLR_MASK 0x02000000 #define SW_DMA0_EB_CLR_OFFSET 24 #define SW_DMA0_EB_CLR_MASK 0x01000000 #define ITR_EB_CLR_OFFSET 22 #define ITR_EB_CLR_MASK 0x00400000 #define MPTX_EB_CLR_OFFSET 21 #define MPTX_EB_CLR_MASK 0x00200000 #define PHY_EB_CLR_OFFSET 20 #define PHY_EB_CLR_MASK 0x00100000 #define PERI_SYS_EB_CLR_OFFSET 19 #define PERI_SYS_EB_CLR_MASK 0x00080000 #define AHB_SYS_ENA_CLR_OFFSET 18 #define AHB_SYS_ENA_CLR_MASK 0x00040000 #define RV5_CORE2_EB_CLR_OFFSET 17 #define RV5_CORE2_EB_CLR_MASK 0x00020000 #define RV5_CORE0_EB_CLR_OFFSET 16 #define RV5_CORE0_EB_CLR_MASK 0x00010000 #define DMC_EB_CLR_OFFSET 15 #define DMC_EB_CLR_MASK 0x00008000 #define DVP3_EB_CLR_OFFSET 14 #define DVP3_EB_CLR_MASK 0x00004000 #define DVP2_EB_CLR_OFFSET 13 #define DVP2_EB_CLR_MASK 0x00002000 #define DVP1_EB_CLR_OFFSET 12 #define DVP1_EB_CLR_MASK 0x00001000 #define DVP0_EB_CLR_OFFSET 11 #define DVP0_EB_CLR_MASK 0x00000800 #define FISHEYE_EB_CLR_OFFSET 10 #define FISHEYE_EB_CLR_MASK 0x00000400 #define MTXTRANS_EB_CLR_OFFSET 9 #define MTXTRANS_EB_CLR_MASK 0x00000200 #define AI_EB_CLR_OFFSET 7 #define AI_EB_CLR_MASK 0x00000080 #define GMACG_EB_CLR_OFFSET 6 #define GMACG_EB_CLR_MASK 0x00000040 #define GMAC_EB_CLR_OFFSET 5 #define GMAC_EB_CLR_MASK 0x00000020 #define DCACHE_EB_CLR_OFFSET 4 #define DCACHE_EB_CLR_MASK 0x00000010 #define ICACHE_EB_CLR_OFFSET 3 #define ICACHE_EB_CLR_MASK 0x00000008 #define NDFC_EB_CLR_OFFSET 2 #define NDFC_EB_CLR_MASK 0x00000004 #define ADA_EB_CLR_OFFSET 1 #define ADA_EB_CLR_MASK 0x00000002 #define MAC_EB_CLR_OFFSET 0 #define MAC_EB_CLR_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG2_SET_ADDR 0x01B0 #define USB_EB_SET_OFFSET 11 #define USB_EB_SET_MASK 0x00000800 #define AFFT1_EB_SET_OFFSET 10 #define AFFT1_EB_SET_MASK 0x00000400 #define CHOL1_EB_SET_OFFSET 9 #define CHOL1_EB_SET_MASK 0x00000200 #define EIG1_EB_SET_OFFSET 8 #define EIG1_EB_SET_MASK 0x00000100 #define CMM1_EB_SET_OFFSET 7 #define CMM1_EB_SET_MASK 0x00000080 #define PHY_ANA_EB_SET_OFFSET 6 #define PHY_ANA_EB_SET_MASK 0x00000040 #define AFFT0_EB_SET_OFFSET 5 #define AFFT0_EB_SET_MASK 0x00000020 #define CHOL0_EB_SET_OFFSET 4 #define CHOL0_EB_SET_MASK 0x00000010 #define EIG0_EB_SET_OFFSET 3 #define EIG0_EB_SET_MASK 0x00000008 #define CMM0_EB_SET_OFFSET 2 #define CMM0_EB_SET_MASK 0x00000004 #define EPARSER_EB_SET_OFFSET 1 #define EPARSER_EB_SET_MASK 0x00000002 #define BUSMON_EB_SET_OFFSET 0 #define BUSMON_EB_SET_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG2_CLR_ADDR 0x01B4 #define USB_EB_CLR_OFFSET 11 #define USB_EB_CLR_MASK 0x00000800 #define AFFT1_EB_CLR_OFFSET 10 #define AFFT1_EB_CLR_MASK 0x00000400 #define CHOL1_EB_CLR_OFFSET 9 #define CHOL1_EB_CLR_MASK 0x00000200 #define EIG1_EB_CLR_OFFSET 8 #define EIG1_EB_CLR_MASK 0x00000100 #define CMM1_EB_CLR_OFFSET 7 #define CMM1_EB_CLR_MASK 0x00000080 #define PHY_ANA_EB_CLR_OFFSET 6 #define PHY_ANA_EB_CLR_MASK 0x00000040 #define AFFT0_EB_CLR_OFFSET 5 #define AFFT0_EB_CLR_MASK 0x00000020 #define CHOL0_EB_CLR_OFFSET 4 #define CHOL0_EB_CLR_MASK 0x00000010 #define EIG0_EB_CLR_OFFSET 3 #define EIG0_EB_CLR_MASK 0x00000008 #define CMM0_EB_CLR_OFFSET 2 #define CMM0_EB_CLR_MASK 0x00000004 #define EPARSER_EB_CLR_OFFSET 1 #define EPARSER_EB_CLR_MASK 0x00000002 #define BUSMON_EB_CLR_OFFSET 0 #define BUSMON_EB_CLR_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG3_SET_ADDR 0x01B8 #define USB_SOFT_RST_SET_OFFSET 11 #define USB_SOFT_RST_SET_MASK 0x00000800 #define AFFT1_SOFT_RST_SET_OFFSET 10 #define AFFT1_SOFT_RST_SET_MASK 0x00000400 #define CHOL1_SOFT_RST_SET_OFFSET 9 #define CHOL1_SOFT_RST_SET_MASK 0x00000200 #define EIG1_SOFT_RST_SET_OFFSET 8 #define EIG1_SOFT_RST_SET_MASK 0x00000100 #define CMM1_SOFT_RST_SET_OFFSET 7 #define CMM1_SOFT_RST_SET_MASK 0x00000080 #define AFFT0_SOFT_RST_SET_OFFSET 5 #define AFFT0_SOFT_RST_SET_MASK 0x00000020 #define CHOL0_SOFT_RST_SET_OFFSET 4 #define CHOL0_SOFT_RST_SET_MASK 0x00000010 #define EIG0_SOFT_RST_SET_OFFSET 3 #define EIG0_SOFT_RST_SET_MASK 0x00000008 #define CMM0_SOFT_RST_SET_OFFSET 2 #define CMM0_SOFT_RST_SET_MASK 0x00000004 #define EPARSER_SOFT_RST_SET_OFFSET 1 #define EPARSER_SOFT_RST_SET_MASK 0x00000002 #define BUSMON_SOFT_RST_SET_OFFSET 0 #define BUSMON_SOFT_RST_SET_MASK 0x00000001 //----------------------------------- #define CFG_AHB_REG3_CLR_ADDR 0x01BC #define USB_SOFT_RST_CLR_OFFSET 11 #define USB_SOFT_RST_CLR_MASK 0x00000800 #define AFFT1_SOFT_RST_CLR_OFFSET 10 #define AFFT1_SOFT_RST_CLR_MASK 0x00000400 #define CHOL1_SOFT_RST_CLR_OFFSET 9 #define CHOL1_SOFT_RST_CLR_MASK 0x00000200 #define EIG1_SOFT_RST_CLR_OFFSET 8 #define EIG1_SOFT_RST_CLR_MASK 0x00000100 #define CMM1_SOFT_RST_CLR_OFFSET 7 #define CMM1_SOFT_RST_CLR_MASK 0x00000080 #define AFFT0_SOFT_RST_CLR_OFFSET 5 #define AFFT0_SOFT_RST_CLR_MASK 0x00000020 #define CHOL0_SOFT_RST_CLR_OFFSET 4 #define CHOL0_SOFT_RST_CLR_MASK 0x00000010 #define EIG0_SOFT_RST_CLR_OFFSET 3 #define EIG0_SOFT_RST_CLR_MASK 0x00000008 #define CMM0_SOFT_RST_CLR_OFFSET 2 #define CMM0_SOFT_RST_CLR_MASK 0x00000004 #define EPARSER_SOFT_RST_CLR_OFFSET 1 #define EPARSER_SOFT_RST_CLR_MASK 0x00000002 #define BUSMON_SOFT_RST_CLR_OFFSET 0 #define BUSMON_SOFT_RST_CLR_MASK 0x00000001 //----------------------------------- #define CFG_MTX_HREADY_ST0_ADDR 0x01C0 #define MTX_HREADY_STS_CLR_OFFSET 31 #define MTX_HREADY_STS_CLR_MASK 0x80000000 #define MTX_SLV_HREADY_STS_OFFSET 0 #define MTX_SLV_HREADY_STS_MASK 0x0000FFFF //----------------------------------- #define CFG_MTX_HREADY_ST1_ADDR 0x01C4 #define MTX_MST_HREADY_STS_OFFSET 0 #define MTX_MST_HREADY_STS_MASK 0x007FFFFF //----------------------------------- #define CFG_LMTX_HREADY_ST0_ADDR 0x01C8 #define LMTX_SLV_HREADY_STS_OFFSET 11 #define LMTX_SLV_HREADY_STS_MASK 0x00003800 #define LMTX_MST_HREADY_STS_OFFSET 0 #define LMTX_MST_HREADY_STS_MASK 0x000007FF //----------------------------------- #define CFG_MTX_HREADY_DBG0_ADDR 0x01CC #define MTX_SLV_HREADY_DBG_OFFSET 0 #define MTX_SLV_HREADY_DBG_MASK 0x0000FFFF //----------------------------------- #define CFG_MTX_HREADY_DBG1_ADDR 0x01D0 #define MTX_MST_HREADY_DBG_OFFSET 0 #define MTX_MST_HREADY_DBG_MASK 0x007FFFFF //----------------------------------- #define CFG_LMTX_HREADY_DBG0_ADDR 0x01D4 #define LMTX_SLV_HREADY_DBG_OFFSET 11 #define LMTX_SLV_HREADY_DBG_MASK 0x00003800 #define LMTX_MST_HREADY_DBG_OFFSET 0 #define LMTX_MST_HREADY_DBG_MASK 0x000007FF //HW module read/write macro #define AHB_RF_READ_REG(addr) SOC_READ_REG(AHB_RF_BASEADDR + addr) #define AHB_RF_WRITE_REG(addr,value) SOC_WRITE_REG(AHB_RF_BASEADDR + addr,value)