//-----------------------------------
#define CFG_ANA_RX_REG_0_ADDR 0x0000
#define RX_PWDPGFOFFSET_OFFSET 30
#define RX_PWDPGFOFFSET_MASK 0x40000000
#define RX_PWDPGAOFFSET_OFFSET 29
#define RX_PWDPGAOFFSET_MASK 0x20000000
#define RX_PWDCGM_OFFSET 28
#define RX_PWDCGM_MASK 0x10000000
#define RX_PGFLOOPEN_OFFSET 27
#define RX_PGFLOOPEN_MASK 0x08000000
#define RX_BYPHPF_OFFSET 26
#define RX_BYPHPF_MASK 0x04000000
#define RX_HPFENORD2_OFFSET 25
#define RX_HPFENORD2_MASK 0x02000000
#define RX_PGAOFFSET_OFFSET 20
#define RX_PGAOFFSET_MASK 0x01F00000
#define RX_PGFOFFSET_OFFSET 14
#define RX_PGFOFFSET_MASK 0x000FC000
#define RX_SELC_OFFSET 8
#define RX_SELC_MASK 0x00003F00
#define RX_GPGA_OFFSET 4
#define RX_GPGA_MASK 0x000000F0
#define RX_GBQ_OFFSET 2
#define RX_GBQ_MASK 0x0000000C
#define RX_GPGF_OFFSET 0
#define RX_GPGF_MASK 0x00000003

//-----------------------------------
#define CFG_ANA_RX_REG_1_ADDR 0x0001
#define RX_PGATESTEN_OFFSET 14
#define RX_PGATESTEN_MASK 0x00004000
#define RX_BQTESTEN_OFFSET 13
#define RX_BQTESTEN_MASK 0x00002000
#define RX_PGFTESTEN_OFFSET 12
#define RX_PGFTESTEN_MASK 0x00001000
#define RX_HPFTESTEN_OFFSET 11
#define RX_HPFTESTEN_MASK 0x00000800
#define RX_TESTEN_OFFSET 10
#define RX_TESTEN_MASK 0x00000400
#define RX_ATB_OFFSET 5
#define RX_ATB_MASK 0x000003E0
#define RX_CGMBYP_OFFSET 0
#define RX_CGMBYP_MASK 0x0000001F

//-----------------------------------
#define CFG_ANA_ADC_REG_ADDR 0x0002
#define ADC_ATB_SEL_OFFSET 13
#define ADC_ATB_SEL_MASK 0x00006000
#define ADC_EN_CAL_COUNTER_OFFSET 12
#define ADC_EN_CAL_COUNTER_MASK 0x00001000
#define ADC_EN_TIMER_OFFSET 11
#define ADC_EN_TIMER_MASK 0x00000800
#define ADC_CFG_SAMPLE_CLK_OFFSET 10
#define ADC_CFG_SAMPLE_CLK_MASK 0x00000400
#define ADC_F_H_OFFSET 7
#define ADC_F_H_MASK 0x00000380
#define ADC_CFG_DLY_OFFSET 4
#define ADC_CFG_DLY_MASK 0x00000070
#define ADC_TIMER_DLY_OFFSET 0
#define ADC_TIMER_DLY_MASK 0x0000000F

//-----------------------------------
#define CFG_ANA_SADC_REG_ADDR 0x0003
#define SADC_EN_CAL_OFFSET 27
#define SADC_EN_CAL_MASK 0x08000000
#define SADC_METER2PAD_EN_NEG_OVR_OFFSET 25
#define SADC_METER2PAD_EN_NEG_OVR_MASK 0x06000000
#define SADC_METER2PAD_EN_OVR_OFFSET 21
#define SADC_METER2PAD_EN_OVR_MASK 0x01E00000
#define SADC_SCLR_CNTRL_DIV2_DIV5_OFFSET 20
#define SADC_SCLR_CNTRL_DIV2_DIV5_MASK 0x00100000
#define SADC_SEL_SCL_MUX_OFFSET 17
#define SADC_SEL_SCL_MUX_MASK 0x000E0000
#define SADC_EN_CAL_COUNTER_OFFSET 16
#define SADC_EN_CAL_COUNTER_MASK 0x00010000
#define SADC_EN_OFFSET 15
#define SADC_EN_MASK 0x00008000
#define SADC_RESET_N_OFFSET 14
#define SADC_RESET_N_MASK 0x00004000
#define SADC_EN_TIMER_OFFSET 13
#define SADC_EN_TIMER_MASK 0x00002000
#define SADC_ATB_SEL_OFFSET 11
#define SADC_ATB_SEL_MASK 0x00001800
#define SADC_SAMPLE_SEL_OFFSET 10
#define SADC_SAMPLE_SEL_MASK 0x00000400
#define SADC_F_H_OFFSET 7
#define SADC_F_H_MASK 0x00000380
#define SADC_CFG_DLY_OFFSET 4
#define SADC_CFG_DLY_MASK 0x00000070
#define SADC_TIMER_DLY_OFFSET 0
#define SADC_TIMER_DLY_MASK 0x0000000F

//-----------------------------------
#define CFG_ANA_PLL_REG_ADDR 0x0004
#define PLL_CHANGE_CHANNEL_OFFSET 15
#define PLL_CHANGE_CHANNEL_MASK 0x00008000
#define PLL_BP_OFFSET 14
#define PLL_BP_MASK 0x00004000
#define PLL_M_OFFSET 6
#define PLL_M_MASK 0x00003FC0
#define PLL_N_OFFSET 2
#define PLL_N_MASK 0x0000003C
#define PLL_OD_OFFSET 0
#define PLL_OD_MASK 0x00000003

//-----------------------------------
#define CFG_ANA_DAC_REG_ADDR 0x0005
#define DAC_INVCLKEN_OFFSET 14
#define DAC_INVCLKEN_MASK 0x00004000
#define DAC_MINSCALE_B_OFFSET 13
#define DAC_MINSCALE_B_MASK 0x00002000
#define DAC_FULLSCALE_OFFSET 12
#define DAC_FULLSCALE_MASK 0x00001000
#define DAC_BURNIN_OFFSET 11
#define DAC_BURNIN_MASK 0x00000800
#define DAC_DATAOVREN_OFFSET 10
#define DAC_DATAOVREN_MASK 0x00000400
#define DAC_DATAOVR_OFFSET 0
#define DAC_DATAOVR_MASK 0x000003FF

//-----------------------------------
#define CFG_ANA_TX_REG_ADDR 0x0006
#define TX_ATB_OFFSET 12
#define TX_ATB_MASK 0x0003F000
#define TX_CGMBYP_OFFSET 7
#define TX_CGMBYP_MASK 0x00000F80
#define TX_PWDCGM_OFFSET 6
#define TX_PWDCGM_MASK 0x00000040
#define TX_GPGA_OFFSET 4
#define TX_GPGA_MASK 0x00000030
#define TX_PGATESTEN_OFFSET 3
#define TX_PGATESTEN_MASK 0x00000008
#define TX_FLTTESTEN_OFFSET 2
#define TX_FLTTESTEN_MASK 0x00000004
#define TX_TESTEN_OFFSET 1
#define TX_TESTEN_MASK 0x00000002
#define TX_COMPEN_OFFSET 0
#define TX_COMPEN_MASK 0x00000001

//-----------------------------------
#define CFG_ANA_BIAS_REG_0_ADDR 0x0007
#define BIAS_ADJ_IR25U_BIT0_OFFSET 21
#define BIAS_ADJ_IR25U_BIT0_MASK 0xFFE00000
#define BIAS_ADJ_IC25U_BIT0_OFFSET 0
#define BIAS_ADJ_IC25U_BIT0_MASK 0x001FFFFF

//-----------------------------------
#define CFG_ANA_BIAS_REG_1_ADDR 0x0008
#define BIAS_ADJ_IR25U_BIT1_OFFSET 21
#define BIAS_ADJ_IR25U_BIT1_MASK 0xFFE00000
#define BIAS_ADJ_IC25U_BIT1_OFFSET 0
#define BIAS_ADJ_IC25U_BIT1_MASK 0x001FFFFF

//-----------------------------------
#define CFG_ANA_BIAS_REG_2_ADDR 0x0009
#define BIAS_SEL_IC_TEST_OFFSET 24
#define BIAS_SEL_IC_TEST_MASK 0xFF000000
#define BIAS_SEL_IR_TEST_OFFSET 17
#define BIAS_SEL_IR_TEST_MASK 0x00FE0000
#define BIAS_SEL_VBG_TEST_OFFSET 16
#define BIAS_SEL_VBG_TEST_MASK 0x00010000
#define BIAS_TEST_VBG_OFFSET 15
#define BIAS_TEST_VBG_MASK 0x00008000
#define BIAS_EN_ICAL_OFFSET 14
#define BIAS_EN_ICAL_MASK 0x00004000
#define BIAS_CAL_OFFSET 9
#define BIAS_CAL_MASK 0x00003E00
#define BIAS_TRIM_SADCREF_OFFSET 6
#define BIAS_TRIM_SADCREF_MASK 0x000001C0
#define BIAS_TRIM_ADCREF_OFFSET 3
#define BIAS_TRIM_ADCREF_MASK 0x00000038
#define BIAS_TRIM_DCDC_OFFSET 0
#define BIAS_TRIM_DCDC_MASK 0x00000007

//-----------------------------------
#define CFG_ANA_TOP_REG_ADDR 0x000A
#define TOP_TX_DIV_OVR_OFFSET 23
#define TOP_TX_DIV_OVR_MASK 0x01800000
#define TOP_RX_DIV_OVR_OFFSET 21
#define TOP_RX_DIV_OVR_MASK 0x00600000
#define TOP_EN_XO_OFFSET 19
#define TOP_EN_XO_MASK 0x00080000
#define TOP_EN_PLLOUT_300M_OFFSET 18
#define TOP_EN_PLLOUT_300M_MASK 0x00040000
#define TOP_EN_DAC_OFFSET 17
#define TOP_EN_DAC_MASK 0x00020000
#define TOP_RESET_N_ADC_OFFSET 16
#define TOP_RESET_N_ADC_MASK 0x00010000
#define TOP_EN_ADC_OFFSET 15
#define TOP_EN_ADC_MASK 0x00008000
#define TOP_TESTPAD_EN_OFFSET 14
#define TOP_TESTPAD_EN_MASK 0x00004000
#define TOP_ATB2PAD_EN_OFFSET 13
#define TOP_ATB2PAD_EN_MASK 0x00002000
#define TOP_GLNA_OFFSET 10
#define TOP_GLNA_MASK 0x00001C00
#define TOP_ENLIC_OFFSET 8
#define TOP_ENLIC_MASK 0x00000300
#define TOP_SADC_SCALING_OFFSET 7
#define TOP_SADC_SCALING_MASK 0x00000080
#define TOP_SEL_METER_INPUT_OFFSET 4
#define TOP_SEL_METER_INPUT_MASK 0x00000070
#define TOP_EN_SADC_OFFSET 3
#define TOP_EN_SADC_MASK 0x00000008
#define TOP_EN_BIAS_OFFSET 2
#define TOP_EN_BIAS_MASK 0x00000004
#define TOP_EN_TX_OFFSET 1
#define TOP_EN_TX_MASK 0x00000002
#define TOP_EN_RX_OFFSET 0
#define TOP_EN_RX_MASK 0x00000001