//-----------------------------------
#define CFG_SNAPSHOT_RVER_ADDR 0x0000
#define AHB_RF_VER_OFFSET 0
#define AHB_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL0_ADDR 0x0004
#define SNAPSHOT_INIT_OFFSET 16
#define SNAPSHOT_INIT_MASK 0x00010000
#define SNAPSHOT_DATA_SEL_OFFSET 8
#define SNAPSHOT_DATA_SEL_MASK 0x00000100
#define SNAPSHOT_EB_OFFSET 0
#define SNAPSHOT_EB_MASK 0x00000001

//-----------------------------------
#define CFG_SNAPSHOT_CTRL1_ADDR 0x0008
#define SNAPSHOT_MASK_OFFSET 0
#define SNAPSHOT_MASK_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL2_ADDR 0x000C
#define SNAPSHOT_CAUSE_OFFSET 0
#define SNAPSHOT_CAUSE_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL3_ADDR 0x0010
#define CPU0_I_HADDR_LLMIT_OFFSET 0
#define CPU0_I_HADDR_LLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL4_ADDR 0x0014
#define CPU0_I_HADDR_HLMIT_OFFSET 0
#define CPU0_I_HADDR_HLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL5_ADDR 0x0018
#define CPU0_D_HADDR_LLMIT_OFFSET 0
#define CPU0_D_HADDR_LLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL6_ADDR 0x001C
#define CPU0_D_HADDR_HLMIT_OFFSET 0
#define CPU0_D_HADDR_HLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL7_ADDR 0x0020
#define CPU1_I_HADDR_LLMIT_OFFSET 0
#define CPU1_I_HADDR_LLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL8_ADDR 0x0024
#define CPU1_I_HADDR_HLMIT_OFFSET 0
#define CPU1_I_HADDR_HLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL9_ADDR 0x0028
#define CPU1_D_HADDR_LLMIT_OFFSET 0
#define CPU1_D_HADDR_LLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL10_ADDR 0x002C
#define CPU1_D_HADDR_HLMIT_OFFSET 0
#define CPU1_D_HADDR_HLMIT_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_CTRL11_ADDR 0x0030
#define FORCE_TRIGGER_OFFSET 0
#define FORCE_TRIGGER_MASK 0x00000001

//-----------------------------------
#define CFG_SNAPSHOT_CTRL12_ADDR 0x0034
#define RW_SEL_OFFSET 0
#define RW_SEL_MASK 0x00000001

//-----------------------------------
#define CFG_SNAPSHOT_DATA_0_ADDR 0x0100
#define SNAPSHOT_DATA_0_OFFSET 0
#define SNAPSHOT_DATA_0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_1_ADDR 0x0104
#define SNAPSHOT_DATA_1_OFFSET 0
#define SNAPSHOT_DATA_1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_2_ADDR 0x0108
#define SNAPSHOT_DATA_2_OFFSET 0
#define SNAPSHOT_DATA_2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_3_ADDR 0x010C
#define SNAPSHOT_DATA_3_OFFSET 0
#define SNAPSHOT_DATA_3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_4_ADDR 0x0110
#define SNAPSHOT_DATA_4_OFFSET 0
#define SNAPSHOT_DATA_4_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_5_ADDR 0x0114
#define SNAPSHOT_DATA_5_OFFSET 0
#define SNAPSHOT_DATA_5_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_6_ADDR 0x0118
#define SNAPSHOT_DATA_6_OFFSET 0
#define SNAPSHOT_DATA_6_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_7_ADDR 0x011C
#define SNAPSHOT_DATA_7_OFFSET 0
#define SNAPSHOT_DATA_7_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_8_ADDR 0x0120
#define SNAPSHOT_DATA_8_OFFSET 0
#define SNAPSHOT_DATA_8_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_9_ADDR 0x0124
#define SNAPSHOT_DATA_9_OFFSET 0
#define SNAPSHOT_DATA_9_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_A_ADDR 0x0128
#define SNAPSHOT_DATA_A_OFFSET 0
#define SNAPSHOT_DATA_A_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_B_ADDR 0x012C
#define SNAPSHOT_DATA_B_OFFSET 0
#define SNAPSHOT_DATA_B_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_C_ADDR 0x0130
#define SNAPSHOT_DATA_C_OFFSET 0
#define SNAPSHOT_DATA_C_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_D_ADDR 0x0134
#define SNAPSHOT_DATA_D_OFFSET 0
#define SNAPSHOT_DATA_D_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_E_ADDR 0x0138
#define SNAPSHOT_DATA_E_OFFSET 0
#define SNAPSHOT_DATA_E_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_SNAPSHOT_DATA_F_ADDR 0x013C
#define SNAPSHOT_DATA_F_OFFSET 0
#define SNAPSHOT_DATA_F_MASK 0xFFFFFFFF

//HW module read/write macro
#define SNAPSHOT_RF_READ_REG(addr) SOC_READ_REG(SNAPSHOT_RF_BASEADDR + addr)
#define SNAPSHOT_RF_WRITE_REG(addr,value) SOC_WRITE_REG(SNAPSHOT_RF_BASEADDR + addr,value)