/**************************************************************************** Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED. This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT be copied by any method or incorporated into another program without the express written consent of Aerospace C.Power. This Information or any portion thereof remains the property of Aerospace C.Power. The Information contained herein is believed to be accurate and Aerospace C.Power assumes no responsibility or liability for its use in any way and conveys no license or title under any patent or copyright and makes no representation or warranty that this Information is free from patent or copyright infringement. ****************************************************************************/ #ifndef _INCLUDE_MCP_IO_DRV_H_ #define _INCLUDE_MCP_IO_DRV_H_ #ifdef __cplusplus extern "C" { #endif #define MCP_SLAVER_ADDR (0x20) #define MCP_GPA 0x0 #define MCP_GPB 0x1 #define MCP_GPMAX 0x2 /* 32 & 33 conflicted with LED_RX & LED_TX */ #define MCP_SDA_GPIO 32 #define MCP_SCL_GPIO 33 #define MCP_MAX_GPIO_NUM_PER_PORT 8 #define MCP_MAX_GPIO_NUM (MCP_MAX_GPIO_NUM_PER_PORT * MCP_GPMAX) #define MCP_GPIO_VALID(io) (((io) < MCP_MAX_GPIO_NUM && (io) >= 0) ? 1 : 0) /* GPIO <---> PORT 0 GPA0 1 GPA1 2 GPA2 3 GPA3 4 GPA4 5 GPA5 6 GPA6 7 GPA7 8 GPB0 9 GPB1 10 GPB2 11 GPB3 12 GPB4 13 GPB5 14 GPB6 15 GPB7 */ /* mcp23017 register addr use bank = 0 ,here wo don't use bank = 1*/ #define IODIRA (0x00) #define IPOLA (0x02) #define GPINTENA (0x04) #define DEFVALA (0x06) #define INTCONA (0x08) #define IOCONA (0x0A) #define GPPUA (0x0C) #define INTFA (0x0E) #define INTCAPA (0x10) #define GPIOA (0x12) #define OLATA (0x14) #define IODIRB (0x01) #define IPOLB (0x03) #define GPINTENB (0x05) #define DEFVALB (0x07) #define INTCONB (0x09) #define IOCONB (0x0B) #define GPPUB (0x0D) #define INTFB (0x0F) #define INTCAPB (0x11) #define GPIOB (0x13) #define OLATB (0x15) #define IO_2_GP(io) ((io) < MCP_MAX_GPIO_NUM_PER_PORT ? MCP_GPA : MCP_GPB) #define IO_SHIFT(io) ((io) < MCP_MAX_GPIO_NUM_PER_PORT ? (io) : (io) - MCP_MAX_GPIO_NUM_PER_PORT) /* Controls the direction of the data I/O. 1 = Pin is configured as an input. 0 = Pin is configured as an output. */ #define IODIR(io) (IO_2_GP(io) == MCP_GPA ? IODIRA : IODIRB) /* This register allows the user to configure the polarity on the corresponding GPIO port bits. 1 = GPIO register bit will reflect the opposite logic state of the input pin. 0 = GPIO register bit will reflect the same logic state of the input pin. */ #define IPOL(io) (IO_2_GP(io) == MCP_GPA ? IPOLA : IPOLB) /* The GPINTEN register controls the interrupt-onchange feature for each pin. 1 = Enable GPIO input pin for interrupt-on-change event. 0 = Disable GPIO input pin for interrupt-on-change event. */ #define GPINTEN(io) (IO_2_GP(io) == MCP_GPA ? GPINTENA : GPINTENB) /* The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur. */ #define DEFVAL(io) (IO_2_GP(io) == MCP_GPA ? DEFVALA : DEFVALB) /* The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value 1 = The corresponding I/O pin is compared against the associated bit in the DEFVAL register. 0 = Pin value is compared against the previous pin value. */ #define INTCON(io) (IO_2_GP(io) == MCP_GPA ? INTCONA : INTCONB) /* Keep default value. */ #define IOCON(io) (IO_2_GP(io) == MCP_GPA ? IOCONA : IOCONB) /* The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 kΩ resistor. 1 = Pull-up enabled. 0 = Pull-up disabled. */ #define GPPU(io) (IO_2_GP(io) == MCP_GPA ? GPPUA : GPPUB) /* The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt. 1 = Pin caused interrupt. 0 = Interrupt not pending. */ #define INTF(io) (IO_2_GP(io) == MCP_GPA ? INTFA : INTFB) /* The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is ‘read only’ and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO. 1 = Logic-high. 0 = Logic-low */ #define INTCAP(io) (IO_2_GP(io) == MCP_GPA ? INTCAPA : INTCAPB) /* The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. 1 = Logic-high. 0 = Logic-low. */ #define GPIO(io) (IO_2_GP(io) == MCP_GPA ? GPIOA : GPIOB) /* The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs. 1 = Logic-high. 0 = Logic-low. */ #define OLAT(io) (IO_2_GP(io) == MCP_GPA ? OLATA : OLATB) #define MCP_IO_BIT(io) (1 << IO_SHIFT(io)) #define MCP_IO_SET(data, io) ((data) |= MCP_IO_BIT(io)) #define MCP_IO_GET(data, io) (((data) & MCP_IO_BIT(io)) ? 1 : 0) #define MCP_IO_CLEAR(data, io) ((data) &= (~ MCP_IO_BIT(io))) enum mcp_gpio_mode { MCP_GPIO_INPUT, MCP_GPIO_OUTPUT }; /** * @brief Modes of interrupt. Only when gpio_mode set as GPIO_INTERRUPT, * int_mode is available. */ enum mcp_gpio_int_trigger_mode { MCP_GPIO_RAISING, /**< Interrupt triggered when the voltage of this GPIO switchs from LOW to HIGH. */ MCP_GPIO_FALLING, /**< Interrupt triggered when the voltage of this GPIO switchs from HIGH to LOW. */ MCP_GPIO_BOTH_EDGE, /**< Interrupt triggered when the voltage of this GPIO switchs to HIGH or LOW . */ MCP_GPIO_INVALID /**< Invalid value */ }; uint32_t mcp_gpio_get_value(uint32_t gpio); uint32_t mcp_gpio_set_value(uint32_t gpio, uint32_t val); uint32_t mcp_gpio_set_dir(uint32_t gpio, uint32_t dir); uint32_t mcp_gpio_set_interrupt(uint32_t gpio, uint32_t enable, uint32_t mode); uint32_t mcp_gpio_get_int_gpio(void); uint32_t mcp_gpio_set_pullup(uint32_t gpio, uint32_t enable); uint32_t mcp_init(void); #ifdef __cplusplus } #endif #endif/*__GPIO_EX_H*/