#define STR1(x) #x #define STR(x) STR1(x) #define TYPE_UIB 0b00000 #define TYPE_SIB 0b00001 #define TYPE_UIH 0b00010 #define TYPE_SIH 0b00011 #define TYPE_UIW 0b00100 #define TYPE_SIW 0b00101 #define TYPE_FPH 0b01010 #define TYPE_FPW 0b01100 #define INST_VADD 0b00100000000000000000000000001011 #define INST_VSUB 0b00100010000000000000000000001011 #define INST_VADDW 0b00100100000000000000000000001011 #define INST_VSUBW 0b00100110000000000000000000001011 #define INST_VSEQ 0b00101000000000000000000000001011 #define INST_VSNE 0b00101010000000000000000000001011 #define INST_VSLT 0b00101100000000000000000000001011 #define INST_VSGE 0b00101110000000000000000000001011 #define INST_VMIN 0b00110000000000000000000000001011 #define INST_VMAX 0b00110010000000000000000000001011 //#define INST_R 0b00110100000000000000000000001011 //#define INST_R 0b00111000000000000000000000001011 #define INST_VMULL 0b01000000000000000000000000001011 #define INST_VMULH 0b01000010000000000000000000001011 #define INST_VMULW 0b01000100000000000000000000001011 //#define INST_R 0b01000110000000000000000000001011 //#define INST_VDIV 0b01001000000000000000000000001011 //#define INST_VREM 0b01001010000000000000000000001011 //#define INST_R 0b01001100000000000000000000001011 //#define INST_R 0b01010000000000000000000000001011 #define INST_VMADD 0b01100000000000000000000000001011 #define INST_VMADDW 0b01100010000000000000000000001011 #define INST_VMSUB 0b01100100000000000000000000001011 #define INST_VMSUBW 0b01100110000000000000000000001011 #define INST_VSLL 0b10000000000000000000000000001011 #define INST_VSRL 0b10000010000000000000000000001011 #define INST_VSRA 0b10000100000000000000000000001011 #define INST_VAND 0b10000110000000000000000000001011 #define INST_VOR 0b10001000000000000000000000001011 #define INST_VXOR 0b10001010000000000000000000001011 #define INST_VMERGE 0b10001100000000000000000000001011 #define INST_VSELECT 0b11001110000000000000000000001011 #define INST_VLD 0b00000000000000000000000000101011 #define INST_VLDS 0b01000000000000000000000000101011 #define INST_VLDX 0b10000000000000000000000000101011 #define INST_VST 0b00000000000000000100000000101011 #define INST_VSTS 0b01000000000000000100000000101011 #define INST_VSTX 0b10000000000000000100000000101011 #define INST_VCSRC 0b00000000000000000011000000101011 #define INST_VCSRW 0b00000000000000000111000000101011 #define CUSTOM0_VCSR(inst, rd, rs1, vcsr_addr) \ inst | \ ((rd & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((vcsr_addr & 0b111111111111) << (7+5+3+5)) #define CUSTOM0_VD_VS12(inst, vd, vs1, vs2) \ inst | \ ((vd & 0b11111) << (7)) | \ ((vs1 & 0b11111) << (7+5+3)) | \ ((vs2 & 0b11111) << (7+5+3+5)) #define CUSTOM0_RS1_VS3(inst, rs1, vs3) \ inst | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((vs3 & 0b11111) << (7+5+3+5+5)) #define CUSTOM0_VST(inst, type, rs1, str, vs3) \ inst | \ ((type & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((str & 0b11111) << (7+5+3+5)) | \ ((vs3 & 0b11111) << (7+5+3+5+5)) #define CUSTOM0_VSTS(inst, type, rs1, rs2, vs3) \ inst | \ ((type & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((rs2 & 0b11111) << (7+5+3+5)) | \ ((vs3 & 0b11111) << (7+5+3+5+5)) #define CUSTOM0_VSTX(inst, type, rs1, vs2, vs3) \ inst | \ ((type & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((vs2 & 0b11111) << (7+5+3+5)) | \ ((vs3 & 0b11111) << (7+5+3+5+5)) #define CUSTOM0_VD_RS1(inst, vd, rs1) \ inst | \ ((vd & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) #define CUSTOM0_VLD(inst, type, vd, rs1, str) \ inst | \ ((vd & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((str & 0b11111) << (7+5+3+5)) | \ ((type & 0b11111) << (7+5+3+5+5)) #define CUSTOM0_VLDS(inst, type, vd, rs1, rs2) \ inst | \ ((vd & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((rs2 & 0b11111) << (7+5+3+5)) | \ ((type & 0b11111) << (7+5+3+5+5)) #define CUSTOM0_VLDX(inst, type, vd, rs1, vs2) \ inst | \ ((vd & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((vs2 & 0b11111) << (7+5+3+5)) | \ ((type & 0b11111) << (7+5+3+5+5)) #define CUSTOM0_VD_RS12(inst, vd, rs1, rs2) \ inst | \ ((vd & 0b11111) << (7)) | \ ((rs1 & 0b11111) << (7+5+3)) | \ ((rs2 & 0b11111) << (7+5+3+5)) #define vcsrw(rd, rs1, vcsr_addr) \ { \ register uint32_t rd_ asm ("x10"); \ register uint32_t rs1_ asm ("x11") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VCSR(INST_VCSRW, 10, 11, vcsr_addr)) "\n\t" \ : "=r" (rd_) \ : [_rs1] "r" (rs1_)); \ rd = rd_; \ } #define vcsrr(rd, vcsr_addr) \ { \ register uint32_t rd_ asm ("x10"); \ asm volatile ( \ ".word " STR(CUSTOM0_VCSR(INST_VCSRC, 10, 0, vcsr_addr)) "\n\t" \ : "=r" (rd_) \ :); \ rd = rd_; \ } #define vadd(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VADD, vd_n, vs1_n, vs2_n))); #define vsub(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSUB, vd_n, vs1_n, vs2_n))); #define vseq(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSEQ, vd_n, vs1_n, vs2_n))); #define vsne(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSNE, vd_n, vs1_n, vs2_n))); #define vslt(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSLT, vd_n, vs1_n, vs2_n))); #define vsge(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSGE, vd_n, vs1_n, vs2_n))); #define vmin(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMIN, vd_n, vs1_n, vs2_n))); #define vmax(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMAX, vd_n, vs1_n, vs2_n))); #define vmull(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMULL, vd_n, vs1_n, vs2_n))); #define vmulh(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMULH, vd_n, vs1_n, vs2_n))); #define vmulw(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMULW, vd_n, vs1_n, vs2_n))); //#define vdiv(vd_n, vs1_n, vs2_n) // asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VDIV, vd_n, vs1_n, vs2_n))); // //#define vrem(vd_n, vs1_n, vs2_n) // asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VREM, vd_n, vs1_n, vs2_n))); #define vmadd(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMADD, vd_n, vs1_n, vs2_n))); #define vmaddw(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMADDW, vd_n, vs1_n, vs2_n))); #define vmsub(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMSUB, vd_n, vs1_n, vs2_n))); #define vmsubw(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMSUBW, vd_n, vs1_n, vs2_n))); #define vsll(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSLL, vd_n, vs1_n, vs2_n))); #define vsrl(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSRL, vd_n, vs1_n, vs2_n))); #define vsra(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSRA, vd_n, vs1_n, vs2_n))); #define vand(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VAND, vd_n, vs1_n, vs2_n))); #define vor(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VOR, vd_n, vs1_n, vs2_n))); #define vxor(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VXOR, vd_n, vs1_n, vs2_n))); #define vmerge(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VMERGE, vd_n, vs1_n, vs2_n))); #define vselect(vd_n, vs1_n, vs2_n) \ asm volatile (".word " STR(CUSTOM0_VD_VS12(INST_VSELECT, vd_n, vs1_n, vs2_n))); #define vld_uib(vd_n, rs1, str) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLD(INST_VLD, TYPE_UIB, vd_n, 10, str)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vld_sib(vd_n, rs1, str) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLD(INST_VLD, TYPE_SIB, vd_n, 10, str)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vld_uih(vd_n, rs1, str) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLD(INST_VLD, TYPE_UIH, vd_n, 10, str)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vld_sih(vd_n, rs1, str) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLD(INST_VLD, TYPE_SIH, vd_n, 10, str)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vld_uiw(vd_n, rs1, str) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLD(INST_VLD, TYPE_UIW, vd_n, 10, str)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vld_siw(vd_n, rs1, str) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLD(INST_VLD, TYPE_SIW, vd_n, 10, str)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vld_fpw(vd_n, rs1, str) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLD(INST_VLD, TYPE_FPW, vd_n, 10, str)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vst_uib(rs1, str, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VST(INST_VST, TYPE_UIB, 10, str, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vst_sib(rs1, str, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VST(INST_VST, TYPE_SIB, 10, str, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vst_uih(rs1, str, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VST(INST_VST, TYPE_UIH, 10, str, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vst_sih(rs1, str, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VST(INST_VST, TYPE_SIH, 10, str, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vst_uiw(rs1, str, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VST(INST_VST, TYPE_UIW, 10, str, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vst_siw(rs1, str, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VST(INST_VST, TYPE_SIW, 10, str, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vst_fpw(rs1, str, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VST(INST_VST, TYPE_FPW, 10, str, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vlds_uib(vd_n, rs1, rs2) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDS(INST_VLDS, TYPE_UIB, vd_n, 10, 11)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vlds_sib(vd_n, rs1, rs2) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDS(INST_VLDS, TYPE_SIB, vd_n, 10, 11)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vlds_uih(vd_n, rs1, rs2) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDS(INST_VLDS, TYPE_UIH, vd_n, 10, 11)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vlds_sih(vd_n, rs1, rs2) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDS(INST_VLDS, TYPE_SIH, vd_n, 10, 11)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vlds_uiw(vd_n, rs1, rs2) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDS(INST_VLDS, TYPE_UIW, vd_n, 10, 11)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vlds_siw(vd_n, rs1, rs2) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDS(INST_VLDS, TYPE_SIW, vd_n, 10, 11)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vlds_fpw(vd_n, rs1, rs2) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDS(INST_VLDS, TYPE_FPW, vd_n, 10, 11)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vsts_uib(rs1, rs2, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTS(INST_VSTS, TYPE_UIB, 10, 11, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vsts_sib(rs1, rs2, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTS(INST_VSTS, TYPE_SIB, 10, 11, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vsts_uih(rs1, rs2, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTS(INST_VSTS, TYPE_UIH, 10, 11, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vsts_sih(rs1, rs2, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTS(INST_VSTS, TYPE_SIH, 10, 11, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vsts_uiw(rs1, rs2, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTS(INST_VSTS, TYPE_UIW, 10, 11, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vsts_siw(rs1, rs2, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTS(INST_VSTS, TYPE_SIW, 10, 11, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vsts_fpw(rs1, rs2, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ register uint32_t rs2_ asm ("x11") = (uint32_t) rs2; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTS(INST_VSTS, TYPE_FPW, 10, 11, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_), [_rs2] "r" (rs2_)); \ } #define vldx_uib(vd_n, rs1, vs2_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDX(INST_VLDX, TYPE_UIB, vd_n, 10, vs2_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vldx_sib(vd_n, rs1, vs2_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDX(INST_VLDX, TYPE_SIB, vd_n, 10, vs2_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vldx_uih(vd_n, rs1, vs2_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDX(INST_VLDX, TYPE_UIH, vd_n, 10, vs2_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vldx_sih(vd_n, rs1, vs2_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDX(INST_VLDX, TYPE_SIH, vd_n, 10, vs2_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vldx_uiw(vd_n, rs1, vs2_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDX(INST_VLDX, TYPE_UIW, vd_n, 10, vs2_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vldx_siw(vd_n, rs1, vs2_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDX(INST_VLDX, TYPE_SIW, vd_n, 10, vs2_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vldx_fpw(vd_n, rs1, vs2_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VLDX(INST_VLDX, TYPE_FPW, vd_n, 10, vs2_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vstx_uib(rs1, vs2_n, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTX(INST_VSTX, TYPE_UIB, 10, vs2_n, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vstx_sib(rs1, vs2_n, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTX(INST_VSTX, TYPE_SIB, 10, vs2_n, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vstx_uih(rs1, vs2_n, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTX(INST_VSTX, TYPE_UIH, 10, vs2_n, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vstx_sih(rs1, vs2_n, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTX(INST_VSTX, TYPE_SIH, 10, vs2_n, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vstx_uiw(rs1, vs2_n, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTX(INST_VSTX, TYPE_UIW, 10, vs2_n, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vstx_siw(rs1, vs2_n, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTX(INST_VSTX, TYPE_SIW, 10, vs2_n, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ } #define vstx_fpw(rs1, vs2_n, vs3_n) \ { \ register uint32_t rs1_ asm ("x10") = (uint32_t) rs1; \ asm volatile ( \ ".word " STR(CUSTOM0_VSTX(INST_VSTX, TYPE_FPW, 10, vs2_n, vs3_n)) "\n\t" \ :: [_rs1] "r" (rs1_)); \ }