//-----------------------------------
#define CFG_I2C_SLAVE_RVER_ADDR 0x0000
#define I2C_SLAVE_RF_VER_OFFSET 0
#define I2C_SLAVE_RF_VER_MASK 0x000000FF

//-----------------------------------
#define CFG_I2C_SLAVE_CTRL0_ADDR 0x0004
#define I2C_RD_WR_SPEC_OFFSET 19
#define I2C_RD_WR_SPEC_MASK 0x00080000
#define I2C_DEV_ADDR_OFFSET 12
#define I2C_DEV_ADDR_MASK 0x0007F000
#define SDA_FILTER_THRS_OFFSET 8
#define SDA_FILTER_THRS_MASK 0x00000F00
#define SCL_FILTER_THRS_OFFSET 4
#define SCL_FILTER_THRS_MASK 0x000000F0
#define SDA_FILTER_EB_OFFSET 2
#define SDA_FILTER_EB_MASK 0x00000004
#define SCL_FILTER_EB_OFFSET 1
#define SCL_FILTER_EB_MASK 0x00000002
#define I2C_FSM_EB_OFFSET 0
#define I2C_FSM_EB_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_SLAVE_CTRL1_ADDR 0x0008
#define ACK_NACK_SAT_TIME_OFFSET 20
#define ACK_NACK_SAT_TIME_MASK 0x0FF00000
#define LOW_LEVEL_PERIOD_OFFSET 12
#define LOW_LEVEL_PERIOD_MASK 0x000FF000
#define HIGH_LEVEL_PERIOD_OFFSET 4
#define HIGH_LEVEL_PERIOD_MASK 0x00000FF0
#define TRANS_BIT_ORDER_OFFSET 3
#define TRANS_BIT_ORDER_MASK 0x00000008
#define RECE_BIT_ORDER_OFFSET 2
#define RECE_BIT_ORDER_MASK 0x00000004
#define I2C_FORCE_DRIVE_SDA_OFFSET 1
#define I2C_FORCE_DRIVE_SDA_MASK 0x00000002
#define I2C_FSM_RST_OFFSET 0
#define I2C_FSM_RST_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_SLAVE_FIFO_STATUS_ADDR 0x000C
#define FIFO_DATA_NUM_OFFSET 4
#define FIFO_DATA_NUM_MASK 0x000001F0
#define FIFO_FULL_OFFSET 1
#define FIFO_FULL_MASK 0x00000002
#define FIFO_EMP_OFFSET 0
#define FIFO_EMP_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_SLAVE_STATUS_ADDR 0x0010
#define RECE_1ST_BYTE_OFFSET 4
#define RECE_1ST_BYTE_MASK 0x00000FF0
#define I2C_FSM_STATUS_OFFSET 0
#define I2C_FSM_STATUS_MASK 0x0000000F

//-----------------------------------
#define CFG_I2C_SLAVE_INT_RAW_ADDR 0x0020
#define I2C_FSM_DONE_INT_RAW_OFFSET 4
#define I2C_FSM_DONE_INT_RAW_MASK 0x00000010
#define TRANS_FIFO_IS_EMP_INT_RAW_OFFSET 3
#define TRANS_FIFO_IS_EMP_INT_RAW_MASK 0x00000008
#define RECE_FIFO_FULL_NACK_INT_RAW_OFFSET 2
#define RECE_FIFO_FULL_NACK_INT_RAW_MASK 0x00000004
#define RECE_1ST_BYTE_INT_RAW_OFFSET 1
#define RECE_1ST_BYTE_INT_RAW_MASK 0x00000002
#define DEV_ADDR_NO_MATCH_INT_RAW_OFFSET 0
#define DEV_ADDR_NO_MATCH_INT_RAW_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_SLAVE_INT_ST_ADDR 0x0024
#define I2C_FSM_DONE_INT_ST_OFFSET 4
#define I2C_FSM_DONE_INT_ST_MASK 0x00000010
#define TRANS_FIFO_IS_EMP_INT_ST_OFFSET 3
#define TRANS_FIFO_IS_EMP_INT_ST_MASK 0x00000008
#define RECE_FIFO_FULL_NACK_INT_ST_OFFSET 2
#define RECE_FIFO_FULL_NACK_INT_ST_MASK 0x00000004
#define RECE_1ST_BYTE_INT_ST_OFFSET 1
#define RECE_1ST_BYTE_INT_ST_MASK 0x00000002
#define DEV_ADDR_NO_MATCH_INT_ST_OFFSET 0
#define DEV_ADDR_NO_MATCH_INT_ST_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_SLAVE_INT_ENA_ADDR 0x0028
#define I2C_FSM_DONE_INT_ENA_OFFSET 4
#define I2C_FSM_DONE_INT_ENA_MASK 0x00000010
#define TRANS_FIFO_IS_EMP_INT_ENA_OFFSET 3
#define TRANS_FIFO_IS_EMP_INT_ENA_MASK 0x00000008
#define RECE_FIFO_FULL_NACK_INT_ENA_OFFSET 2
#define RECE_FIFO_FULL_NACK_INT_ENA_MASK 0x00000004
#define RECE_1ST_BYTE_INT_ENA_OFFSET 1
#define RECE_1ST_BYTE_INT_ENA_MASK 0x00000002
#define DEV_ADDR_NO_MATCH_INT_ENA_OFFSET 0
#define DEV_ADDR_NO_MATCH_INT_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_SLAVE_INT_CLR_ADDR 0x002C
#define I2C_FSM_DONE_INT_CLR_OFFSET 4
#define I2C_FSM_DONE_INT_CLR_MASK 0x00000010
#define TRANS_FIFO_IS_EMP_INT_CLR_OFFSET 3
#define TRANS_FIFO_IS_EMP_INT_CLR_MASK 0x00000008
#define RECE_FIFO_FULL_NACK_INT_CLR_OFFSET 2
#define RECE_FIFO_FULL_NACK_INT_CLR_MASK 0x00000004
#define RECE_1ST_BYTE_INT_CLR_OFFSET 1
#define RECE_1ST_BYTE_INT_CLR_MASK 0x00000002
#define DEV_ADDR_NO_MATCH_INT_CLR_OFFSET 0
#define DEV_ADDR_NO_MATCH_INT_CLR_MASK 0x00000001

//-----------------------------------
#define CFG_I2C_S_FIFO_RDATA_ADDR 0x0040
#define FIFO_RDATA_OFFSET 0
#define FIFO_RDATA_MASK 0x000000FF

//-----------------------------------
#define CFG_I2C_S_FIFO_WDATA_ADDR 0x0044
#define FIFO_WDATA_OFFSET 0
#define FIFO_WDATA_MASK 0x000000FF

//-----------------------------------
#define CFG_I2C_S_FIFO_RD_ADDR 0x0048
#define FIFO_RD_WE_OFFSET 0
#define FIFO_RD_WE_MASK 0x00000001

//HW module read/write macro
#define I2C_SLAVE0_READ_REG(addr) SOC_READ_REG(I2C_SLAVE0_BASEADDR + addr)
#define I2C_SLAVE0_WRITE_REG(addr,value) SOC_WRITE_REG(I2C_SLAVE0_BASEADDR + addr,value)
#define I2C_SLAVE1_READ_REG(addr) SOC_READ_REG(I2C_SLAVE1_BASEADDR + addr)
#define I2C_SLAVE1_WRITE_REG(addr,value) SOC_WRITE_REG(I2C_SLAVE1_BASEADDR + addr,value)