//-----------------------------------
#define CFG_INTC_RVER_ADDR 0x0000
#define INTC_RF_VER_OFFSET 0
#define INTC_RF_VER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_INT_SRC_ADDR 0x0004
#define INT_SRC_OFFSET 0
#define INT_SRC_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_ENA_ADDR 0x0008
#define INT_ENA_OFFSET 0
#define INT_ENA_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_PRI_SEL_ADDR 0x000c
#define INT_PRI_SEL_OFFSET 0
#define INT_PRI_SEL_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG0_ADDR 0x0010
#define INT7_PRI_CFG_OFFSET 28
#define INT7_PRI_CFG_MASK 0x70000000
#define INT6_PRI_CFG_OFFSET 24
#define INT6_PRI_CFG_MASK 0x07000000
#define INT5_PRI_CFG_OFFSET 20
#define INT5_PRI_CFG_MASK 0x00700000
#define INT4_PRI_CFG_OFFSET 16
#define INT4_PRI_CFG_MASK 0x00070000
#define INT3_PRI_CFG_OFFSET 12
#define INT3_PRI_CFG_MASK 0x00007000
#define INT2_PRI_CFG_OFFSET 8
#define INT2_PRI_CFG_MASK 0x00000700
#define INT1_PRI_CFG_OFFSET 4
#define INT1_PRI_CFG_MASK 0x00000070
#define INT0_PRI_CFG_OFFSET 0
#define INT0_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG1_ADDR 0x0014
#define INT15_PRI_CFG_OFFSET 28
#define INT15_PRI_CFG_MASK 0x70000000
#define INT14_PRI_CFG_OFFSET 24
#define INT14_PRI_CFG_MASK 0x07000000
#define INT13_PRI_CFG_OFFSET 20
#define INT13_PRI_CFG_MASK 0x00700000
#define INT12_PRI_CFG_OFFSET 16
#define INT12_PRI_CFG_MASK 0x00070000
#define INT11_PRI_CFG_OFFSET 12
#define INT11_PRI_CFG_MASK 0x00007000
#define INT10_PRI_CFG_OFFSET 8
#define INT10_PRI_CFG_MASK 0x00000700
#define INT9_PRI_CFG_OFFSET 4
#define INT9_PRI_CFG_MASK 0x00000070
#define INT8_PRI_CFG_OFFSET 0
#define INT8_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG2_ADDR 0x0018
#define INT23_PRI_CFG_OFFSET 28
#define INT23_PRI_CFG_MASK 0x70000000
#define INT22_PRI_CFG_OFFSET 24
#define INT22_PRI_CFG_MASK 0x07000000
#define INT21_PRI_CFG_OFFSET 20
#define INT21_PRI_CFG_MASK 0x00700000
#define INT20_PRI_CFG_OFFSET 16
#define INT20_PRI_CFG_MASK 0x00070000
#define INT19_PRI_CFG_OFFSET 12
#define INT19_PRI_CFG_MASK 0x00007000
#define INT18_PRI_CFG_OFFSET 8
#define INT18_PRI_CFG_MASK 0x00000700
#define INT17_PRI_CFG_OFFSET 4
#define INT17_PRI_CFG_MASK 0x00000070
#define INT16_PRI_CFG_OFFSET 0
#define INT16_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_PRI_CFG3_ADDR 0x001c
#define INT31_PRI_CFG_OFFSET 28
#define INT31_PRI_CFG_MASK 0x70000000
#define INT30_PRI_CFG_OFFSET 24
#define INT30_PRI_CFG_MASK 0x07000000
#define INT29_PRI_CFG_OFFSET 20
#define INT29_PRI_CFG_MASK 0x00700000
#define INT28_PRI_CFG_OFFSET 16
#define INT28_PRI_CFG_MASK 0x00070000
#define INT27_PRI_CFG_OFFSET 12
#define INT27_PRI_CFG_MASK 0x00007000
#define INT26_PRI_CFG_OFFSET 8
#define INT26_PRI_CFG_MASK 0x00000700
#define INT25_PRI_CFG_OFFSET 4
#define INT25_PRI_CFG_MASK 0x00000070
#define INT24_PRI_CFG_OFFSET 0
#define INT24_PRI_CFG_MASK 0x00000007

//-----------------------------------
#define CFG_INT_STS_ADDR 0x0020
#define INT_STS_OFFSET 0
#define INT_STS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_INT_PRI_STS_ADDR 0x0024
#define INT_PRI_STS_OFFSET 0
#define INT_PRI_STS_MASK 0x00000007

//HW module read/write macro
#define INTC_READ_REG(addr) SOC_READ_REG(INTC_BASEADDR + addr)
#define INTC_WRITE_REG(addr,value) SOC_WRITE_REG(INTC_BASEADDR + addr,value)