//-----------------------------------
#define CFG_TIMER0_ADDR 0x0000
#define CFG_RCG_TIMER_OFFSET 16
#define CFG_RCG_TIMER_MASK 0xFFFF0000
#define CFG_CMG_TIMER_OFFSET 0
#define CFG_CMG_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER1_ADDR 0x0004
#define CFG_RIFS_TIMER_OFFSET 16
#define CFG_RIFS_TIMER_MASK 0xFFFF0000
#define CFG_CIFS_TIMER_OFFSET 0
#define CFG_CIFS_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER2_ADDR 0x0008
#define CFG_TX_DELAY_OFFSET 22
#define CFG_TX_DELAY_MASK 0xFFC00000
#define CFG_RX_SHORT_DELAY_OFFSET 11
#define CFG_RX_SHORT_DELAY_MASK 0x003FF800
#define CFG_RX_LONG_DELAY_OFFSET 0
#define CFG_RX_LONG_DELAY_MASK 0x000007FF

//-----------------------------------
#define CFG_TIMER3_ADDR 0x000c
#define CFG_DELIMITER_TIMER1_OFFSET 16
#define CFG_DELIMITER_TIMER1_MASK 0xFFFF0000
#define CFG_DELIMITER_TIMER0_OFFSET 0
#define CFG_DELIMITER_TIMER0_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER4_ADDR 0x0010
#define CFG_FC_LEN_TIMER1_OFFSET 16
#define CFG_FC_LEN_TIMER1_MASK 0xFFFF0000
#define CFG_FC_LEN_TIMER0_OFFSET 0
#define CFG_FC_LEN_TIMER0_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER5_ADDR 0x0014
#define CFG_BIFS_TIMER_OFFSET 16
#define CFG_BIFS_TIMER_MASK 0xFFFF0000
#define CFG_EIFS_TIMER_OFFSET 0
#define CFG_EIFS_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER6_ADDR 0x0018
#define CFG_AIFS_TIMER_OFFSET 16
#define CFG_AIFS_TIMER_MASK 0xFFFF0000
#define CFG_B2BIFS_TIMER_OFFSET 0
#define CFG_B2BIFS_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER7_ADDR 0x001c
#define CFG_PRS_SLOT_TIMER_OFFSET 0
#define CFG_PRS_SLOT_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER8_ADDR 0x0020
#define CFG_SLOT_TIMER_OFFSET 0
#define CFG_SLOT_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER9_ADDR 0x0024
#define CFG_DELIMITER_TIMER3_OFFSET 16
#define CFG_DELIMITER_TIMER3_MASK 0xFFFF0000
#define CFG_DELIMITER_TIMER2_OFFSET 0
#define CFG_DELIMITER_TIMER2_MASK 0x0000FFFF

//-----------------------------------
#define CFG_TIMER10_ADDR 0x0028
#define CFG_FC_LEN_TIMER3_OFFSET 16
#define CFG_FC_LEN_TIMER3_MASK 0xFFFF0000
#define CFG_FC_LEN_TIMER2_OFFSET 0
#define CFG_FC_LEN_TIMER2_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_TIMER0_ADDR 0x002c
#define CFG_SG_CIFS_TIMER_OFFSET 16
#define CFG_SG_CIFS_TIMER_MASK 0xFFFF0000
#define CFG_SG_EIFS_TIMER_OFFSET 0
#define CFG_SG_EIFS_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_TIMER1_ADDR 0x0030
#define CFG_SG_RIFS_TIMER_OFFSET 0
#define CFG_SG_RIFS_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_TIMER2_ADDR 0x0034
#define CFG_SG_TX_DELAY_OFFSET 0
#define CFG_SG_TX_DELAY_MASK 0x000003FF

//-----------------------------------
#define CFG_SG_TIMER3_ADDR 0x0038
#define CFG_SG_RX_SHORT_DELAY_OFFSET 0
#define CFG_SG_RX_SHORT_DELAY_MASK 0x000007FF

//-----------------------------------
#define CFG_SG_TIMER4_ADDR 0x003C
#define CFG_SG_RX_LONG_DELAY_OFFSET 0
#define CFG_SG_RX_LONG_DELAY_MASK 0x000007FF

//-----------------------------------
#define CFG_SG_TIMER5_ADDR 0x0040
#define CFG_SG_DELIMITER_TIMER_1_OFFSET 16
#define CFG_SG_DELIMITER_TIMER_1_MASK 0xFFFF0000
#define CFG_SG_DELIMITER_TIMER_0_OFFSET 0
#define CFG_SG_DELIMITER_TIMER_0_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_TIMER6_ADDR 0x0044
#define CFG_SG_DELIMITER_TIMER_3_OFFSET 16
#define CFG_SG_DELIMITER_TIMER_3_MASK 0xFFFF0000
#define CFG_SG_DELIMITER_TIMER_2_OFFSET 0
#define CFG_SG_DELIMITER_TIMER_2_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_TIMER7_ADDR 0x0048
#define CFG_SG_FC_LEN_TIMER_1_OFFSET 16
#define CFG_SG_FC_LEN_TIMER_1_MASK 0xFFFF0000
#define CFG_SG_FC_LEN_TIMER_0_OFFSET 0
#define CFG_SG_FC_LEN_TIMER_0_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_TIMER8_ADDR 0x004c
#define CFG_SG_FC_LEN_TIMER_3_OFFSET 16
#define CFG_SG_FC_LEN_TIMER_3_MASK 0xFFFF0000
#define CFG_SG_FC_LEN_TIMER_2_OFFSET 0
#define CFG_SG_FC_LEN_TIMER_2_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_TIMER9_ADDR 0x0050
#define CFG_SG_B2BIFS_TIMER_OFFSET 0
#define CFG_SG_B2BIFS_TIMER_MASK 0x0000FFFF

//-----------------------------------
#define CFG_SG_DUMMY1_ADDR 0x0054

//-----------------------------------
#define CFG_TMR_CTRL_ADDR 0x0058
#define CFG_EIFS_SELECT_OFFSET 0
#define CFG_EIFS_SELECT_MASK 0x00000001

//-----------------------------------
#define CFG_VCS_CNT_ADDR 0x0060
#define CFG_VCS_INIT_VALUE_OFFSET 1
#define CFG_VCS_INIT_VALUE_MASK 0x0001FFFE
#define CFG_VCS_INIT_LOAD_TRIG_OFFSET 0
#define CFG_VCS_INIT_LOAD_TRIG_MASK 0x00000001

//-----------------------------------
#define CFG_TX_FC_CTRL_ADDR 0x0064
#define CFG_TX_FC_FL_BY_SW_OFFSET 2
#define CFG_TX_FC_FL_BY_SW_MASK 0x00000004
#define CFG_TX_FC_PBNUM_BY_SW_OFFSET 1
#define CFG_TX_FC_PBNUM_BY_SW_MASK 0x00000002
#define CFG_TX_FC_SYMBNUM_BY_SW_OFFSET 0
#define CFG_TX_FC_SYMBNUM_BY_SW_MASK 0x00000001

//HW module read/write macro
#define RGF_TMR_READ_REG(addr) SOC_READ_REG(RGF_TMR_BASEADDR + addr)
#define RGF_TMR_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_TMR_BASEADDR + addr,value)