//----------------------------------- #define CFG_GPIO_INT0_ENA0_ADDR 0x0 #define GPIO_INT0_ENA0_OFFSET 0 #define GPIO_INT0_ENA0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO_INT0_ENA1_ADDR 0x4 #define GPIO_INT0_ENA1_OFFSET 0 #define GPIO_INT0_ENA1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO_INT1_ENA0_ADDR 0x8 #define GPIO_INT1_ENA0_OFFSET 0 #define GPIO_INT1_ENA0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO_INT1_ENA1_ADDR 0xc #define GPIO_INT1_ENA1_OFFSET 0 #define GPIO_INT1_ENA1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO_INT0_STS0_ADDR 0x10 #define GPIO_INT0_STS0_OFFSET 0 #define GPIO_INT0_STS0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO_INT0_STS1_ADDR 0x14 #define GPIO_INT0_STS1_OFFSET 0 #define GPIO_INT0_STS1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO_INT1_STS0_ADDR 0x18 #define GPIO_INT1_STS0_OFFSET 0 #define GPIO_INT1_STS0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO_INT1_STS1_ADDR 0x1c #define GPIO_INT1_STS1_OFFSET 0 #define GPIO_INT1_STS1_MASK 0xFFFFFFFF //----------------------------------- #define CFG_GPIO0_CFG_ADDR 0x20 #define GPIO0_OD_MODE_OFFSET 12 #define GPIO0_OD_MODE_MASK 0x00003000 #define GPIO0_OUT_OFFSET 11 #define GPIO0_OUT_MASK 0x00000800 #define GPIO0_OE_OFFSET 10 #define GPIO0_OE_MASK 0x00000400 #define GPIO0_IE_OFFSET 9 #define GPIO0_IE_MASK 0x00000200 #define GPIO0_IN_OFFSET 8 #define GPIO0_IN_MASK 0x00000100 #define GPIO0_WAKEUP_ENA_OFFSET 7 #define GPIO0_WAKEUP_ENA_MASK 0x00000080 #define GPIO0_INT_TYPE_OFFSET 4 #define GPIO0_INT_TYPE_MASK 0x00000070 #define GPIO0_INT_RAW_OFFSET 3 #define GPIO0_INT_RAW_MASK 0x00000008 #define GPIO0_INT_STS_OFFSET 2 #define GPIO0_INT_STS_MASK 0x00000004 #define GPIO0_INT_ENA_OFFSET 1 #define GPIO0_INT_ENA_MASK 0x00000002 #define GPIO0_INT_CLR_OFFSET 0 #define GPIO0_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO1_CFG_ADDR 0x24 #define GPIO1_OD_MODE_OFFSET 12 #define GPIO1_OD_MODE_MASK 0x00003000 #define GPIO1_OUT_OFFSET 11 #define GPIO1_OUT_MASK 0x00000800 #define GPIO1_OE_OFFSET 10 #define GPIO1_OE_MASK 0x00000400 #define GPIO1_IE_OFFSET 9 #define GPIO1_IE_MASK 0x00000200 #define GPIO1_IN_OFFSET 8 #define GPIO1_IN_MASK 0x00000100 #define GPIO1_WAKEUP_ENA_OFFSET 7 #define GPIO1_WAKEUP_ENA_MASK 0x00000080 #define GPIO1_INT_TYPE_OFFSET 4 #define GPIO1_INT_TYPE_MASK 0x00000070 #define GPIO1_INT_RAW_OFFSET 3 #define GPIO1_INT_RAW_MASK 0x00000008 #define GPIO1_INT_STS_OFFSET 2 #define GPIO1_INT_STS_MASK 0x00000004 #define GPIO1_INT_ENA_OFFSET 1 #define GPIO1_INT_ENA_MASK 0x00000002 #define GPIO1_INT_CLR_OFFSET 0 #define GPIO1_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO2_CFG_ADDR 0x28 #define GPIO2_OD_MODE_OFFSET 12 #define GPIO2_OD_MODE_MASK 0x00003000 #define GPIO2_OUT_OFFSET 11 #define GPIO2_OUT_MASK 0x00000800 #define GPIO2_OE_OFFSET 10 #define GPIO2_OE_MASK 0x00000400 #define GPIO2_IE_OFFSET 9 #define GPIO2_IE_MASK 0x00000200 #define GPIO2_IN_OFFSET 8 #define GPIO2_IN_MASK 0x00000100 #define GPIO2_WAKEUP_ENA_OFFSET 7 #define GPIO2_WAKEUP_ENA_MASK 0x00000080 #define GPIO2_INT_TYPE_OFFSET 4 #define GPIO2_INT_TYPE_MASK 0x00000070 #define GPIO2_INT_RAW_OFFSET 3 #define GPIO2_INT_RAW_MASK 0x00000008 #define GPIO2_INT_STS_OFFSET 2 #define GPIO2_INT_STS_MASK 0x00000004 #define GPIO2_INT_ENA_OFFSET 1 #define GPIO2_INT_ENA_MASK 0x00000002 #define GPIO2_INT_CLR_OFFSET 0 #define GPIO2_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO3_CFG_ADDR 0x2c #define GPIO3_OD_MODE_OFFSET 12 #define GPIO3_OD_MODE_MASK 0x00003000 #define GPIO3_OUT_OFFSET 11 #define GPIO3_OUT_MASK 0x00000800 #define GPIO3_OE_OFFSET 10 #define GPIO3_OE_MASK 0x00000400 #define GPIO3_IE_OFFSET 9 #define GPIO3_IE_MASK 0x00000200 #define GPIO3_IN_OFFSET 8 #define GPIO3_IN_MASK 0x00000100 #define GPIO3_WAKEUP_ENA_OFFSET 7 #define GPIO3_WAKEUP_ENA_MASK 0x00000080 #define GPIO3_INT_TYPE_OFFSET 4 #define GPIO3_INT_TYPE_MASK 0x00000070 #define GPIO3_INT_RAW_OFFSET 3 #define GPIO3_INT_RAW_MASK 0x00000008 #define GPIO3_INT_STS_OFFSET 2 #define GPIO3_INT_STS_MASK 0x00000004 #define GPIO3_INT_ENA_OFFSET 1 #define GPIO3_INT_ENA_MASK 0x00000002 #define GPIO3_INT_CLR_OFFSET 0 #define GPIO3_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO4_CFG_ADDR 0x30 #define GPIO4_OD_MODE_OFFSET 12 #define GPIO4_OD_MODE_MASK 0x00003000 #define GPIO4_OUT_OFFSET 11 #define GPIO4_OUT_MASK 0x00000800 #define GPIO4_OE_OFFSET 10 #define GPIO4_OE_MASK 0x00000400 #define GPIO4_IE_OFFSET 9 #define GPIO4_IE_MASK 0x00000200 #define GPIO4_IN_OFFSET 8 #define GPIO4_IN_MASK 0x00000100 #define GPIO4_WAKEUP_ENA_OFFSET 7 #define GPIO4_WAKEUP_ENA_MASK 0x00000080 #define GPIO4_INT_TYPE_OFFSET 4 #define GPIO4_INT_TYPE_MASK 0x00000070 #define GPIO4_INT_RAW_OFFSET 3 #define GPIO4_INT_RAW_MASK 0x00000008 #define GPIO4_INT_STS_OFFSET 2 #define GPIO4_INT_STS_MASK 0x00000004 #define GPIO4_INT_ENA_OFFSET 1 #define GPIO4_INT_ENA_MASK 0x00000002 #define GPIO4_INT_CLR_OFFSET 0 #define GPIO4_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO5_CFG_ADDR 0x34 #define GPIO5_OD_MODE_OFFSET 12 #define GPIO5_OD_MODE_MASK 0x00003000 #define GPIO5_OUT_OFFSET 11 #define GPIO5_OUT_MASK 0x00000800 #define GPIO5_OE_OFFSET 10 #define GPIO5_OE_MASK 0x00000400 #define GPIO5_IE_OFFSET 9 #define GPIO5_IE_MASK 0x00000200 #define GPIO5_IN_OFFSET 8 #define GPIO5_IN_MASK 0x00000100 #define GPIO5_WAKEUP_ENA_OFFSET 7 #define GPIO5_WAKEUP_ENA_MASK 0x00000080 #define GPIO5_INT_TYPE_OFFSET 4 #define GPIO5_INT_TYPE_MASK 0x00000070 #define GPIO5_INT_RAW_OFFSET 3 #define GPIO5_INT_RAW_MASK 0x00000008 #define GPIO5_INT_STS_OFFSET 2 #define GPIO5_INT_STS_MASK 0x00000004 #define GPIO5_INT_ENA_OFFSET 1 #define GPIO5_INT_ENA_MASK 0x00000002 #define GPIO5_INT_CLR_OFFSET 0 #define GPIO5_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO6_CFG_ADDR 0x38 #define GPIO6_OD_MODE_OFFSET 12 #define GPIO6_OD_MODE_MASK 0x00003000 #define GPIO6_OUT_OFFSET 11 #define GPIO6_OUT_MASK 0x00000800 #define GPIO6_OE_OFFSET 10 #define GPIO6_OE_MASK 0x00000400 #define GPIO6_IE_OFFSET 9 #define GPIO6_IE_MASK 0x00000200 #define GPIO6_IN_OFFSET 8 #define GPIO6_IN_MASK 0x00000100 #define GPIO6_WAKEUP_ENA_OFFSET 7 #define GPIO6_WAKEUP_ENA_MASK 0x00000080 #define GPIO6_INT_TYPE_OFFSET 4 #define GPIO6_INT_TYPE_MASK 0x00000070 #define GPIO6_INT_RAW_OFFSET 3 #define GPIO6_INT_RAW_MASK 0x00000008 #define GPIO6_INT_STS_OFFSET 2 #define GPIO6_INT_STS_MASK 0x00000004 #define GPIO6_INT_ENA_OFFSET 1 #define GPIO6_INT_ENA_MASK 0x00000002 #define GPIO6_INT_CLR_OFFSET 0 #define GPIO6_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO7_CFG_ADDR 0x3c #define GPIO7_OD_MODE_OFFSET 12 #define GPIO7_OD_MODE_MASK 0x00003000 #define GPIO7_OUT_OFFSET 11 #define GPIO7_OUT_MASK 0x00000800 #define GPIO7_OE_OFFSET 10 #define GPIO7_OE_MASK 0x00000400 #define GPIO7_IE_OFFSET 9 #define GPIO7_IE_MASK 0x00000200 #define GPIO7_IN_OFFSET 8 #define GPIO7_IN_MASK 0x00000100 #define GPIO7_WAKEUP_ENA_OFFSET 7 #define GPIO7_WAKEUP_ENA_MASK 0x00000080 #define GPIO7_INT_TYPE_OFFSET 4 #define GPIO7_INT_TYPE_MASK 0x00000070 #define GPIO7_INT_RAW_OFFSET 3 #define GPIO7_INT_RAW_MASK 0x00000008 #define GPIO7_INT_STS_OFFSET 2 #define GPIO7_INT_STS_MASK 0x00000004 #define GPIO7_INT_ENA_OFFSET 1 #define GPIO7_INT_ENA_MASK 0x00000002 #define GPIO7_INT_CLR_OFFSET 0 #define GPIO7_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO8_CFG_ADDR 0x40 #define GPIO8_OD_MODE_OFFSET 12 #define GPIO8_OD_MODE_MASK 0x00003000 #define GPIO8_OUT_OFFSET 11 #define GPIO8_OUT_MASK 0x00000800 #define GPIO8_OE_OFFSET 10 #define GPIO8_OE_MASK 0x00000400 #define GPIO8_IE_OFFSET 9 #define GPIO8_IE_MASK 0x00000200 #define GPIO8_IN_OFFSET 8 #define GPIO8_IN_MASK 0x00000100 #define GPIO8_WAKEUP_ENA_OFFSET 7 #define GPIO8_WAKEUP_ENA_MASK 0x00000080 #define GPIO8_INT_TYPE_OFFSET 4 #define GPIO8_INT_TYPE_MASK 0x00000070 #define GPIO8_INT_RAW_OFFSET 3 #define GPIO8_INT_RAW_MASK 0x00000008 #define GPIO8_INT_STS_OFFSET 2 #define GPIO8_INT_STS_MASK 0x00000004 #define GPIO8_INT_ENA_OFFSET 1 #define GPIO8_INT_ENA_MASK 0x00000002 #define GPIO8_INT_CLR_OFFSET 0 #define GPIO8_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO9_CFG_ADDR 0x44 #define GPIO9_OD_MODE_OFFSET 12 #define GPIO9_OD_MODE_MASK 0x00003000 #define GPIO9_OUT_OFFSET 11 #define GPIO9_OUT_MASK 0x00000800 #define GPIO9_OE_OFFSET 10 #define GPIO9_OE_MASK 0x00000400 #define GPIO9_IE_OFFSET 9 #define GPIO9_IE_MASK 0x00000200 #define GPIO9_IN_OFFSET 8 #define GPIO9_IN_MASK 0x00000100 #define GPIO9_WAKEUP_ENA_OFFSET 7 #define GPIO9_WAKEUP_ENA_MASK 0x00000080 #define GPIO9_INT_TYPE_OFFSET 4 #define GPIO9_INT_TYPE_MASK 0x00000070 #define GPIO9_INT_RAW_OFFSET 3 #define GPIO9_INT_RAW_MASK 0x00000008 #define GPIO9_INT_STS_OFFSET 2 #define GPIO9_INT_STS_MASK 0x00000004 #define GPIO9_INT_ENA_OFFSET 1 #define GPIO9_INT_ENA_MASK 0x00000002 #define GPIO9_INT_CLR_OFFSET 0 #define GPIO9_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO10_CFG_ADDR 0x48 #define GPIO10_OD_MODE_OFFSET 12 #define GPIO10_OD_MODE_MASK 0x00003000 #define GPIO10_OUT_OFFSET 11 #define GPIO10_OUT_MASK 0x00000800 #define GPIO10_OE_OFFSET 10 #define GPIO10_OE_MASK 0x00000400 #define GPIO10_IE_OFFSET 9 #define GPIO10_IE_MASK 0x00000200 #define GPIO10_IN_OFFSET 8 #define GPIO10_IN_MASK 0x00000100 #define GPIO10_WAKEUP_ENA_OFFSET 7 #define GPIO10_WAKEUP_ENA_MASK 0x00000080 #define GPIO10_INT_TYPE_OFFSET 4 #define GPIO10_INT_TYPE_MASK 0x00000070 #define GPIO10_INT_RAW_OFFSET 3 #define GPIO10_INT_RAW_MASK 0x00000008 #define GPIO10_INT_STS_OFFSET 2 #define GPIO10_INT_STS_MASK 0x00000004 #define GPIO10_INT_ENA_OFFSET 1 #define GPIO10_INT_ENA_MASK 0x00000002 #define GPIO10_INT_CLR_OFFSET 0 #define GPIO10_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO11_CFG_ADDR 0x4c #define GPIO11_OD_MODE_OFFSET 12 #define GPIO11_OD_MODE_MASK 0x00003000 #define GPIO11_OUT_OFFSET 11 #define GPIO11_OUT_MASK 0x00000800 #define GPIO11_OE_OFFSET 10 #define GPIO11_OE_MASK 0x00000400 #define GPIO11_IE_OFFSET 9 #define GPIO11_IE_MASK 0x00000200 #define GPIO11_IN_OFFSET 8 #define GPIO11_IN_MASK 0x00000100 #define GPIO11_WAKEUP_ENA_OFFSET 7 #define GPIO11_WAKEUP_ENA_MASK 0x00000080 #define GPIO11_INT_TYPE_OFFSET 4 #define GPIO11_INT_TYPE_MASK 0x00000070 #define GPIO11_INT_RAW_OFFSET 3 #define GPIO11_INT_RAW_MASK 0x00000008 #define GPIO11_INT_STS_OFFSET 2 #define GPIO11_INT_STS_MASK 0x00000004 #define GPIO11_INT_ENA_OFFSET 1 #define GPIO11_INT_ENA_MASK 0x00000002 #define GPIO11_INT_CLR_OFFSET 0 #define GPIO11_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO12_CFG_ADDR 0x50 #define GPIO12_OD_MODE_OFFSET 12 #define GPIO12_OD_MODE_MASK 0x00003000 #define GPIO12_OUT_OFFSET 11 #define GPIO12_OUT_MASK 0x00000800 #define GPIO12_OE_OFFSET 10 #define GPIO12_OE_MASK 0x00000400 #define GPIO12_IE_OFFSET 9 #define GPIO12_IE_MASK 0x00000200 #define GPIO12_IN_OFFSET 8 #define GPIO12_IN_MASK 0x00000100 #define GPIO12_WAKEUP_ENA_OFFSET 7 #define GPIO12_WAKEUP_ENA_MASK 0x00000080 #define GPIO12_INT_TYPE_OFFSET 4 #define GPIO12_INT_TYPE_MASK 0x00000070 #define GPIO12_INT_RAW_OFFSET 3 #define GPIO12_INT_RAW_MASK 0x00000008 #define GPIO12_INT_STS_OFFSET 2 #define GPIO12_INT_STS_MASK 0x00000004 #define GPIO12_INT_ENA_OFFSET 1 #define GPIO12_INT_ENA_MASK 0x00000002 #define GPIO12_INT_CLR_OFFSET 0 #define GPIO12_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO13_CFG_ADDR 0x54 #define GPIO13_OD_MODE_OFFSET 12 #define GPIO13_OD_MODE_MASK 0x00003000 #define GPIO13_OUT_OFFSET 11 #define GPIO13_OUT_MASK 0x00000800 #define GPIO13_OE_OFFSET 10 #define GPIO13_OE_MASK 0x00000400 #define GPIO13_IE_OFFSET 9 #define GPIO13_IE_MASK 0x00000200 #define GPIO13_IN_OFFSET 8 #define GPIO13_IN_MASK 0x00000100 #define GPIO13_WAKEUP_ENA_OFFSET 7 #define GPIO13_WAKEUP_ENA_MASK 0x00000080 #define GPIO13_INT_TYPE_OFFSET 4 #define GPIO13_INT_TYPE_MASK 0x00000070 #define GPIO13_INT_RAW_OFFSET 3 #define GPIO13_INT_RAW_MASK 0x00000008 #define GPIO13_INT_STS_OFFSET 2 #define GPIO13_INT_STS_MASK 0x00000004 #define GPIO13_INT_ENA_OFFSET 1 #define GPIO13_INT_ENA_MASK 0x00000002 #define GPIO13_INT_CLR_OFFSET 0 #define GPIO13_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO14_CFG_ADDR 0x58 #define GPIO14_OD_MODE_OFFSET 12 #define GPIO14_OD_MODE_MASK 0x00003000 #define GPIO14_OUT_OFFSET 11 #define GPIO14_OUT_MASK 0x00000800 #define GPIO14_OE_OFFSET 10 #define GPIO14_OE_MASK 0x00000400 #define GPIO14_IE_OFFSET 9 #define GPIO14_IE_MASK 0x00000200 #define GPIO14_IN_OFFSET 8 #define GPIO14_IN_MASK 0x00000100 #define GPIO14_WAKEUP_ENA_OFFSET 7 #define GPIO14_WAKEUP_ENA_MASK 0x00000080 #define GPIO14_INT_TYPE_OFFSET 4 #define GPIO14_INT_TYPE_MASK 0x00000070 #define GPIO14_INT_RAW_OFFSET 3 #define GPIO14_INT_RAW_MASK 0x00000008 #define GPIO14_INT_STS_OFFSET 2 #define GPIO14_INT_STS_MASK 0x00000004 #define GPIO14_INT_ENA_OFFSET 1 #define GPIO14_INT_ENA_MASK 0x00000002 #define GPIO14_INT_CLR_OFFSET 0 #define GPIO14_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO15_CFG_ADDR 0x5c #define GPIO15_OD_MODE_OFFSET 12 #define GPIO15_OD_MODE_MASK 0x00003000 #define GPIO15_OUT_OFFSET 11 #define GPIO15_OUT_MASK 0x00000800 #define GPIO15_OE_OFFSET 10 #define GPIO15_OE_MASK 0x00000400 #define GPIO15_IE_OFFSET 9 #define GPIO15_IE_MASK 0x00000200 #define GPIO15_IN_OFFSET 8 #define GPIO15_IN_MASK 0x00000100 #define GPIO15_WAKEUP_ENA_OFFSET 7 #define GPIO15_WAKEUP_ENA_MASK 0x00000080 #define GPIO15_INT_TYPE_OFFSET 4 #define GPIO15_INT_TYPE_MASK 0x00000070 #define GPIO15_INT_RAW_OFFSET 3 #define GPIO15_INT_RAW_MASK 0x00000008 #define GPIO15_INT_STS_OFFSET 2 #define GPIO15_INT_STS_MASK 0x00000004 #define GPIO15_INT_ENA_OFFSET 1 #define GPIO15_INT_ENA_MASK 0x00000002 #define GPIO15_INT_CLR_OFFSET 0 #define GPIO15_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO16_CFG_ADDR 0x60 #define GPIO16_OD_MODE_OFFSET 12 #define GPIO16_OD_MODE_MASK 0x00003000 #define GPIO16_OUT_OFFSET 11 #define GPIO16_OUT_MASK 0x00000800 #define GPIO16_OE_OFFSET 10 #define GPIO16_OE_MASK 0x00000400 #define GPIO16_IE_OFFSET 9 #define GPIO16_IE_MASK 0x00000200 #define GPIO16_IN_OFFSET 8 #define GPIO16_IN_MASK 0x00000100 #define GPIO16_WAKEUP_ENA_OFFSET 7 #define GPIO16_WAKEUP_ENA_MASK 0x00000080 #define GPIO16_INT_TYPE_OFFSET 4 #define GPIO16_INT_TYPE_MASK 0x00000070 #define GPIO16_INT_RAW_OFFSET 3 #define GPIO16_INT_RAW_MASK 0x00000008 #define GPIO16_INT_STS_OFFSET 2 #define GPIO16_INT_STS_MASK 0x00000004 #define GPIO16_INT_ENA_OFFSET 1 #define GPIO16_INT_ENA_MASK 0x00000002 #define GPIO16_INT_CLR_OFFSET 0 #define GPIO16_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO17_CFG_ADDR 0x64 #define GPIO17_OD_MODE_OFFSET 12 #define GPIO17_OD_MODE_MASK 0x00003000 #define GPIO17_OUT_OFFSET 11 #define GPIO17_OUT_MASK 0x00000800 #define GPIO17_OE_OFFSET 10 #define GPIO17_OE_MASK 0x00000400 #define GPIO17_IE_OFFSET 9 #define GPIO17_IE_MASK 0x00000200 #define GPIO17_IN_OFFSET 8 #define GPIO17_IN_MASK 0x00000100 #define GPIO17_WAKEUP_ENA_OFFSET 7 #define GPIO17_WAKEUP_ENA_MASK 0x00000080 #define GPIO17_INT_TYPE_OFFSET 4 #define GPIO17_INT_TYPE_MASK 0x00000070 #define GPIO17_INT_RAW_OFFSET 3 #define GPIO17_INT_RAW_MASK 0x00000008 #define GPIO17_INT_STS_OFFSET 2 #define GPIO17_INT_STS_MASK 0x00000004 #define GPIO17_INT_ENA_OFFSET 1 #define GPIO17_INT_ENA_MASK 0x00000002 #define GPIO17_INT_CLR_OFFSET 0 #define GPIO17_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO18_CFG_ADDR 0x68 #define GPIO18_OD_MODE_OFFSET 12 #define GPIO18_OD_MODE_MASK 0x00003000 #define GPIO18_OUT_OFFSET 11 #define GPIO18_OUT_MASK 0x00000800 #define GPIO18_OE_OFFSET 10 #define GPIO18_OE_MASK 0x00000400 #define GPIO18_IE_OFFSET 9 #define GPIO18_IE_MASK 0x00000200 #define GPIO18_IN_OFFSET 8 #define GPIO18_IN_MASK 0x00000100 #define GPIO18_WAKEUP_ENA_OFFSET 7 #define GPIO18_WAKEUP_ENA_MASK 0x00000080 #define GPIO18_INT_TYPE_OFFSET 4 #define GPIO18_INT_TYPE_MASK 0x00000070 #define GPIO18_INT_RAW_OFFSET 3 #define GPIO18_INT_RAW_MASK 0x00000008 #define GPIO18_INT_STS_OFFSET 2 #define GPIO18_INT_STS_MASK 0x00000004 #define GPIO18_INT_ENA_OFFSET 1 #define GPIO18_INT_ENA_MASK 0x00000002 #define GPIO18_INT_CLR_OFFSET 0 #define GPIO18_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO19_CFG_ADDR 0x6c #define GPIO19_OD_MODE_OFFSET 12 #define GPIO19_OD_MODE_MASK 0x00003000 #define GPIO19_OUT_OFFSET 11 #define GPIO19_OUT_MASK 0x00000800 #define GPIO19_OE_OFFSET 10 #define GPIO19_OE_MASK 0x00000400 #define GPIO19_IE_OFFSET 9 #define GPIO19_IE_MASK 0x00000200 #define GPIO19_IN_OFFSET 8 #define GPIO19_IN_MASK 0x00000100 #define GPIO19_WAKEUP_ENA_OFFSET 7 #define GPIO19_WAKEUP_ENA_MASK 0x00000080 #define GPIO19_INT_TYPE_OFFSET 4 #define GPIO19_INT_TYPE_MASK 0x00000070 #define GPIO19_INT_RAW_OFFSET 3 #define GPIO19_INT_RAW_MASK 0x00000008 #define GPIO19_INT_STS_OFFSET 2 #define GPIO19_INT_STS_MASK 0x00000004 #define GPIO19_INT_ENA_OFFSET 1 #define GPIO19_INT_ENA_MASK 0x00000002 #define GPIO19_INT_CLR_OFFSET 0 #define GPIO19_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO20_CFG_ADDR 0x70 #define GPIO20_OD_MODE_OFFSET 12 #define GPIO20_OD_MODE_MASK 0x00003000 #define GPIO20_OUT_OFFSET 11 #define GPIO20_OUT_MASK 0x00000800 #define GPIO20_OE_OFFSET 10 #define GPIO20_OE_MASK 0x00000400 #define GPIO20_IE_OFFSET 9 #define GPIO20_IE_MASK 0x00000200 #define GPIO20_IN_OFFSET 8 #define GPIO20_IN_MASK 0x00000100 #define GPIO20_WAKEUP_ENA_OFFSET 7 #define GPIO20_WAKEUP_ENA_MASK 0x00000080 #define GPIO20_INT_TYPE_OFFSET 4 #define GPIO20_INT_TYPE_MASK 0x00000070 #define GPIO20_INT_RAW_OFFSET 3 #define GPIO20_INT_RAW_MASK 0x00000008 #define GPIO20_INT_STS_OFFSET 2 #define GPIO20_INT_STS_MASK 0x00000004 #define GPIO20_INT_ENA_OFFSET 1 #define GPIO20_INT_ENA_MASK 0x00000002 #define GPIO20_INT_CLR_OFFSET 0 #define GPIO20_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO21_CFG_ADDR 0x74 #define GPIO21_OD_MODE_OFFSET 12 #define GPIO21_OD_MODE_MASK 0x00003000 #define GPIO21_OUT_OFFSET 11 #define GPIO21_OUT_MASK 0x00000800 #define GPIO21_OE_OFFSET 10 #define GPIO21_OE_MASK 0x00000400 #define GPIO21_IE_OFFSET 9 #define GPIO21_IE_MASK 0x00000200 #define GPIO21_IN_OFFSET 8 #define GPIO21_IN_MASK 0x00000100 #define GPIO21_WAKEUP_ENA_OFFSET 7 #define GPIO21_WAKEUP_ENA_MASK 0x00000080 #define GPIO21_INT_TYPE_OFFSET 4 #define GPIO21_INT_TYPE_MASK 0x00000070 #define GPIO21_INT_RAW_OFFSET 3 #define GPIO21_INT_RAW_MASK 0x00000008 #define GPIO21_INT_STS_OFFSET 2 #define GPIO21_INT_STS_MASK 0x00000004 #define GPIO21_INT_ENA_OFFSET 1 #define GPIO21_INT_ENA_MASK 0x00000002 #define GPIO21_INT_CLR_OFFSET 0 #define GPIO21_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO22_CFG_ADDR 0x78 #define GPIO22_OD_MODE_OFFSET 12 #define GPIO22_OD_MODE_MASK 0x00003000 #define GPIO22_OUT_OFFSET 11 #define GPIO22_OUT_MASK 0x00000800 #define GPIO22_OE_OFFSET 10 #define GPIO22_OE_MASK 0x00000400 #define GPIO22_IE_OFFSET 9 #define GPIO22_IE_MASK 0x00000200 #define GPIO22_IN_OFFSET 8 #define GPIO22_IN_MASK 0x00000100 #define GPIO22_WAKEUP_ENA_OFFSET 7 #define GPIO22_WAKEUP_ENA_MASK 0x00000080 #define GPIO22_INT_TYPE_OFFSET 4 #define GPIO22_INT_TYPE_MASK 0x00000070 #define GPIO22_INT_RAW_OFFSET 3 #define GPIO22_INT_RAW_MASK 0x00000008 #define GPIO22_INT_STS_OFFSET 2 #define GPIO22_INT_STS_MASK 0x00000004 #define GPIO22_INT_ENA_OFFSET 1 #define GPIO22_INT_ENA_MASK 0x00000002 #define GPIO22_INT_CLR_OFFSET 0 #define GPIO22_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO23_CFG_ADDR 0x7c #define GPIO23_OD_MODE_OFFSET 12 #define GPIO23_OD_MODE_MASK 0x00003000 #define GPIO23_OUT_OFFSET 11 #define GPIO23_OUT_MASK 0x00000800 #define GPIO23_OE_OFFSET 10 #define GPIO23_OE_MASK 0x00000400 #define GPIO23_IE_OFFSET 9 #define GPIO23_IE_MASK 0x00000200 #define GPIO23_IN_OFFSET 8 #define GPIO23_IN_MASK 0x00000100 #define GPIO23_WAKEUP_ENA_OFFSET 7 #define GPIO23_WAKEUP_ENA_MASK 0x00000080 #define GPIO23_INT_TYPE_OFFSET 4 #define GPIO23_INT_TYPE_MASK 0x00000070 #define GPIO23_INT_RAW_OFFSET 3 #define GPIO23_INT_RAW_MASK 0x00000008 #define GPIO23_INT_STS_OFFSET 2 #define GPIO23_INT_STS_MASK 0x00000004 #define GPIO23_INT_ENA_OFFSET 1 #define GPIO23_INT_ENA_MASK 0x00000002 #define GPIO23_INT_CLR_OFFSET 0 #define GPIO23_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO24_CFG_ADDR 0x80 #define GPIO24_OD_MODE_OFFSET 12 #define GPIO24_OD_MODE_MASK 0x00003000 #define GPIO24_OUT_OFFSET 11 #define GPIO24_OUT_MASK 0x00000800 #define GPIO24_OE_OFFSET 10 #define GPIO24_OE_MASK 0x00000400 #define GPIO24_IE_OFFSET 9 #define GPIO24_IE_MASK 0x00000200 #define GPIO24_IN_OFFSET 8 #define GPIO24_IN_MASK 0x00000100 #define GPIO24_WAKEUP_ENA_OFFSET 7 #define GPIO24_WAKEUP_ENA_MASK 0x00000080 #define GPIO24_INT_TYPE_OFFSET 4 #define GPIO24_INT_TYPE_MASK 0x00000070 #define GPIO24_INT_RAW_OFFSET 3 #define GPIO24_INT_RAW_MASK 0x00000008 #define GPIO24_INT_STS_OFFSET 2 #define GPIO24_INT_STS_MASK 0x00000004 #define GPIO24_INT_ENA_OFFSET 1 #define GPIO24_INT_ENA_MASK 0x00000002 #define GPIO24_INT_CLR_OFFSET 0 #define GPIO24_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO25_CFG_ADDR 0x84 #define GPIO25_OD_MODE_OFFSET 12 #define GPIO25_OD_MODE_MASK 0x00003000 #define GPIO25_OUT_OFFSET 11 #define GPIO25_OUT_MASK 0x00000800 #define GPIO25_OE_OFFSET 10 #define GPIO25_OE_MASK 0x00000400 #define GPIO25_IE_OFFSET 9 #define GPIO25_IE_MASK 0x00000200 #define GPIO25_IN_OFFSET 8 #define GPIO25_IN_MASK 0x00000100 #define GPIO25_WAKEUP_ENA_OFFSET 7 #define GPIO25_WAKEUP_ENA_MASK 0x00000080 #define GPIO25_INT_TYPE_OFFSET 4 #define GPIO25_INT_TYPE_MASK 0x00000070 #define GPIO25_INT_RAW_OFFSET 3 #define GPIO25_INT_RAW_MASK 0x00000008 #define GPIO25_INT_STS_OFFSET 2 #define GPIO25_INT_STS_MASK 0x00000004 #define GPIO25_INT_ENA_OFFSET 1 #define GPIO25_INT_ENA_MASK 0x00000002 #define GPIO25_INT_CLR_OFFSET 0 #define GPIO25_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO26_CFG_ADDR 0x88 #define GPIO26_OD_MODE_OFFSET 12 #define GPIO26_OD_MODE_MASK 0x00003000 #define GPIO26_OUT_OFFSET 11 #define GPIO26_OUT_MASK 0x00000800 #define GPIO26_OE_OFFSET 10 #define GPIO26_OE_MASK 0x00000400 #define GPIO26_IE_OFFSET 9 #define GPIO26_IE_MASK 0x00000200 #define GPIO26_IN_OFFSET 8 #define GPIO26_IN_MASK 0x00000100 #define GPIO26_WAKEUP_ENA_OFFSET 7 #define GPIO26_WAKEUP_ENA_MASK 0x00000080 #define GPIO26_INT_TYPE_OFFSET 4 #define GPIO26_INT_TYPE_MASK 0x00000070 #define GPIO26_INT_RAW_OFFSET 3 #define GPIO26_INT_RAW_MASK 0x00000008 #define GPIO26_INT_STS_OFFSET 2 #define GPIO26_INT_STS_MASK 0x00000004 #define GPIO26_INT_ENA_OFFSET 1 #define GPIO26_INT_ENA_MASK 0x00000002 #define GPIO26_INT_CLR_OFFSET 0 #define GPIO26_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO27_CFG_ADDR 0x8c #define GPIO27_OD_MODE_OFFSET 12 #define GPIO27_OD_MODE_MASK 0x00003000 #define GPIO27_OUT_OFFSET 11 #define GPIO27_OUT_MASK 0x00000800 #define GPIO27_OE_OFFSET 10 #define GPIO27_OE_MASK 0x00000400 #define GPIO27_IE_OFFSET 9 #define GPIO27_IE_MASK 0x00000200 #define GPIO27_IN_OFFSET 8 #define GPIO27_IN_MASK 0x00000100 #define GPIO27_WAKEUP_ENA_OFFSET 7 #define GPIO27_WAKEUP_ENA_MASK 0x00000080 #define GPIO27_INT_TYPE_OFFSET 4 #define GPIO27_INT_TYPE_MASK 0x00000070 #define GPIO27_INT_RAW_OFFSET 3 #define GPIO27_INT_RAW_MASK 0x00000008 #define GPIO27_INT_STS_OFFSET 2 #define GPIO27_INT_STS_MASK 0x00000004 #define GPIO27_INT_ENA_OFFSET 1 #define GPIO27_INT_ENA_MASK 0x00000002 #define GPIO27_INT_CLR_OFFSET 0 #define GPIO27_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO28_CFG_ADDR 0x90 #define GPIO28_OD_MODE_OFFSET 12 #define GPIO28_OD_MODE_MASK 0x00003000 #define GPIO28_OUT_OFFSET 11 #define GPIO28_OUT_MASK 0x00000800 #define GPIO28_OE_OFFSET 10 #define GPIO28_OE_MASK 0x00000400 #define GPIO28_IE_OFFSET 9 #define GPIO28_IE_MASK 0x00000200 #define GPIO28_IN_OFFSET 8 #define GPIO28_IN_MASK 0x00000100 #define GPIO28_WAKEUP_ENA_OFFSET 7 #define GPIO28_WAKEUP_ENA_MASK 0x00000080 #define GPIO28_INT_TYPE_OFFSET 4 #define GPIO28_INT_TYPE_MASK 0x00000070 #define GPIO28_INT_RAW_OFFSET 3 #define GPIO28_INT_RAW_MASK 0x00000008 #define GPIO28_INT_STS_OFFSET 2 #define GPIO28_INT_STS_MASK 0x00000004 #define GPIO28_INT_ENA_OFFSET 1 #define GPIO28_INT_ENA_MASK 0x00000002 #define GPIO28_INT_CLR_OFFSET 0 #define GPIO28_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO29_CFG_ADDR 0x94 #define GPIO29_OD_MODE_OFFSET 12 #define GPIO29_OD_MODE_MASK 0x00003000 #define GPIO29_OUT_OFFSET 11 #define GPIO29_OUT_MASK 0x00000800 #define GPIO29_OE_OFFSET 10 #define GPIO29_OE_MASK 0x00000400 #define GPIO29_IE_OFFSET 9 #define GPIO29_IE_MASK 0x00000200 #define GPIO29_IN_OFFSET 8 #define GPIO29_IN_MASK 0x00000100 #define GPIO29_WAKEUP_ENA_OFFSET 7 #define GPIO29_WAKEUP_ENA_MASK 0x00000080 #define GPIO29_INT_TYPE_OFFSET 4 #define GPIO29_INT_TYPE_MASK 0x00000070 #define GPIO29_INT_RAW_OFFSET 3 #define GPIO29_INT_RAW_MASK 0x00000008 #define GPIO29_INT_STS_OFFSET 2 #define GPIO29_INT_STS_MASK 0x00000004 #define GPIO29_INT_ENA_OFFSET 1 #define GPIO29_INT_ENA_MASK 0x00000002 #define GPIO29_INT_CLR_OFFSET 0 #define GPIO29_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO30_CFG_ADDR 0x98 #define GPIO30_OD_MODE_OFFSET 12 #define GPIO30_OD_MODE_MASK 0x00003000 #define GPIO30_OUT_OFFSET 11 #define GPIO30_OUT_MASK 0x00000800 #define GPIO30_OE_OFFSET 10 #define GPIO30_OE_MASK 0x00000400 #define GPIO30_IE_OFFSET 9 #define GPIO30_IE_MASK 0x00000200 #define GPIO30_IN_OFFSET 8 #define GPIO30_IN_MASK 0x00000100 #define GPIO30_WAKEUP_ENA_OFFSET 7 #define GPIO30_WAKEUP_ENA_MASK 0x00000080 #define GPIO30_INT_TYPE_OFFSET 4 #define GPIO30_INT_TYPE_MASK 0x00000070 #define GPIO30_INT_RAW_OFFSET 3 #define GPIO30_INT_RAW_MASK 0x00000008 #define GPIO30_INT_STS_OFFSET 2 #define GPIO30_INT_STS_MASK 0x00000004 #define GPIO30_INT_ENA_OFFSET 1 #define GPIO30_INT_ENA_MASK 0x00000002 #define GPIO30_INT_CLR_OFFSET 0 #define GPIO30_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO31_CFG_ADDR 0x9c #define GPIO31_OD_MODE_OFFSET 12 #define GPIO31_OD_MODE_MASK 0x00003000 #define GPIO31_OUT_OFFSET 11 #define GPIO31_OUT_MASK 0x00000800 #define GPIO31_OE_OFFSET 10 #define GPIO31_OE_MASK 0x00000400 #define GPIO31_IE_OFFSET 9 #define GPIO31_IE_MASK 0x00000200 #define GPIO31_IN_OFFSET 8 #define GPIO31_IN_MASK 0x00000100 #define GPIO31_WAKEUP_ENA_OFFSET 7 #define GPIO31_WAKEUP_ENA_MASK 0x00000080 #define GPIO31_INT_TYPE_OFFSET 4 #define GPIO31_INT_TYPE_MASK 0x00000070 #define GPIO31_INT_RAW_OFFSET 3 #define GPIO31_INT_RAW_MASK 0x00000008 #define GPIO31_INT_STS_OFFSET 2 #define GPIO31_INT_STS_MASK 0x00000004 #define GPIO31_INT_ENA_OFFSET 1 #define GPIO31_INT_ENA_MASK 0x00000002 #define GPIO31_INT_CLR_OFFSET 0 #define GPIO31_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO32_CFG_ADDR 0xa0 #define GPIO32_OD_MODE_OFFSET 12 #define GPIO32_OD_MODE_MASK 0x00003000 #define GPIO32_OUT_OFFSET 11 #define GPIO32_OUT_MASK 0x00000800 #define GPIO32_OE_OFFSET 10 #define GPIO32_OE_MASK 0x00000400 #define GPIO32_IE_OFFSET 9 #define GPIO32_IE_MASK 0x00000200 #define GPIO32_IN_OFFSET 8 #define GPIO32_IN_MASK 0x00000100 #define GPIO32_WAKEUP_ENA_OFFSET 7 #define GPIO32_WAKEUP_ENA_MASK 0x00000080 #define GPIO32_INT_TYPE_OFFSET 4 #define GPIO32_INT_TYPE_MASK 0x00000070 #define GPIO32_INT_RAW_OFFSET 3 #define GPIO32_INT_RAW_MASK 0x00000008 #define GPIO32_INT_STS_OFFSET 2 #define GPIO32_INT_STS_MASK 0x00000004 #define GPIO32_INT_ENA_OFFSET 1 #define GPIO32_INT_ENA_MASK 0x00000002 #define GPIO32_INT_CLR_OFFSET 0 #define GPIO32_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO33_CFG_ADDR 0xa4 #define GPIO33_OD_MODE_OFFSET 12 #define GPIO33_OD_MODE_MASK 0x00003000 #define GPIO33_OUT_OFFSET 11 #define GPIO33_OUT_MASK 0x00000800 #define GPIO33_OE_OFFSET 10 #define GPIO33_OE_MASK 0x00000400 #define GPIO33_IE_OFFSET 9 #define GPIO33_IE_MASK 0x00000200 #define GPIO33_IN_OFFSET 8 #define GPIO33_IN_MASK 0x00000100 #define GPIO33_WAKEUP_ENA_OFFSET 7 #define GPIO33_WAKEUP_ENA_MASK 0x00000080 #define GPIO33_INT_TYPE_OFFSET 4 #define GPIO33_INT_TYPE_MASK 0x00000070 #define GPIO33_INT_RAW_OFFSET 3 #define GPIO33_INT_RAW_MASK 0x00000008 #define GPIO33_INT_STS_OFFSET 2 #define GPIO33_INT_STS_MASK 0x00000004 #define GPIO33_INT_ENA_OFFSET 1 #define GPIO33_INT_ENA_MASK 0x00000002 #define GPIO33_INT_CLR_OFFSET 0 #define GPIO33_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO34_CFG_ADDR 0xa8 #define GPIO34_OD_MODE_OFFSET 12 #define GPIO34_OD_MODE_MASK 0x00003000 #define GPIO34_OUT_OFFSET 11 #define GPIO34_OUT_MASK 0x00000800 #define GPIO34_OE_OFFSET 10 #define GPIO34_OE_MASK 0x00000400 #define GPIO34_IE_OFFSET 9 #define GPIO34_IE_MASK 0x00000200 #define GPIO34_IN_OFFSET 8 #define GPIO34_IN_MASK 0x00000100 #define GPIO34_WAKEUP_ENA_OFFSET 7 #define GPIO34_WAKEUP_ENA_MASK 0x00000080 #define GPIO34_INT_TYPE_OFFSET 4 #define GPIO34_INT_TYPE_MASK 0x00000070 #define GPIO34_INT_RAW_OFFSET 3 #define GPIO34_INT_RAW_MASK 0x00000008 #define GPIO34_INT_STS_OFFSET 2 #define GPIO34_INT_STS_MASK 0x00000004 #define GPIO34_INT_ENA_OFFSET 1 #define GPIO34_INT_ENA_MASK 0x00000002 #define GPIO34_INT_CLR_OFFSET 0 #define GPIO34_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO35_CFG_ADDR 0xac #define GPIO35_OD_MODE_OFFSET 12 #define GPIO35_OD_MODE_MASK 0x00003000 #define GPIO35_OUT_OFFSET 11 #define GPIO35_OUT_MASK 0x00000800 #define GPIO35_OE_OFFSET 10 #define GPIO35_OE_MASK 0x00000400 #define GPIO35_IE_OFFSET 9 #define GPIO35_IE_MASK 0x00000200 #define GPIO35_IN_OFFSET 8 #define GPIO35_IN_MASK 0x00000100 #define GPIO35_WAKEUP_ENA_OFFSET 7 #define GPIO35_WAKEUP_ENA_MASK 0x00000080 #define GPIO35_INT_TYPE_OFFSET 4 #define GPIO35_INT_TYPE_MASK 0x00000070 #define GPIO35_INT_RAW_OFFSET 3 #define GPIO35_INT_RAW_MASK 0x00000008 #define GPIO35_INT_STS_OFFSET 2 #define GPIO35_INT_STS_MASK 0x00000004 #define GPIO35_INT_ENA_OFFSET 1 #define GPIO35_INT_ENA_MASK 0x00000002 #define GPIO35_INT_CLR_OFFSET 0 #define GPIO35_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO36_CFG_ADDR 0xb0 #define GPIO36_OD_MODE_OFFSET 12 #define GPIO36_OD_MODE_MASK 0x00003000 #define GPIO36_OUT_OFFSET 11 #define GPIO36_OUT_MASK 0x00000800 #define GPIO36_OE_OFFSET 10 #define GPIO36_OE_MASK 0x00000400 #define GPIO36_IE_OFFSET 9 #define GPIO36_IE_MASK 0x00000200 #define GPIO36_IN_OFFSET 8 #define GPIO36_IN_MASK 0x00000100 #define GPIO36_WAKEUP_ENA_OFFSET 7 #define GPIO36_WAKEUP_ENA_MASK 0x00000080 #define GPIO36_INT_TYPE_OFFSET 4 #define GPIO36_INT_TYPE_MASK 0x00000070 #define GPIO36_INT_RAW_OFFSET 3 #define GPIO36_INT_RAW_MASK 0x00000008 #define GPIO36_INT_STS_OFFSET 2 #define GPIO36_INT_STS_MASK 0x00000004 #define GPIO36_INT_ENA_OFFSET 1 #define GPIO36_INT_ENA_MASK 0x00000002 #define GPIO36_INT_CLR_OFFSET 0 #define GPIO36_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO37_CFG_ADDR 0xb4 #define GPIO37_OD_MODE_OFFSET 12 #define GPIO37_OD_MODE_MASK 0x00003000 #define GPIO37_OUT_OFFSET 11 #define GPIO37_OUT_MASK 0x00000800 #define GPIO37_OE_OFFSET 10 #define GPIO37_OE_MASK 0x00000400 #define GPIO37_IE_OFFSET 9 #define GPIO37_IE_MASK 0x00000200 #define GPIO37_IN_OFFSET 8 #define GPIO37_IN_MASK 0x00000100 #define GPIO37_WAKEUP_ENA_OFFSET 7 #define GPIO37_WAKEUP_ENA_MASK 0x00000080 #define GPIO37_INT_TYPE_OFFSET 4 #define GPIO37_INT_TYPE_MASK 0x00000070 #define GPIO37_INT_RAW_OFFSET 3 #define GPIO37_INT_RAW_MASK 0x00000008 #define GPIO37_INT_STS_OFFSET 2 #define GPIO37_INT_STS_MASK 0x00000004 #define GPIO37_INT_ENA_OFFSET 1 #define GPIO37_INT_ENA_MASK 0x00000002 #define GPIO37_INT_CLR_OFFSET 0 #define GPIO37_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO38_CFG_ADDR 0xb8 #define GPIO38_OD_MODE_OFFSET 12 #define GPIO38_OD_MODE_MASK 0x00003000 #define GPIO38_OUT_OFFSET 11 #define GPIO38_OUT_MASK 0x00000800 #define GPIO38_OE_OFFSET 10 #define GPIO38_OE_MASK 0x00000400 #define GPIO38_IE_OFFSET 9 #define GPIO38_IE_MASK 0x00000200 #define GPIO38_IN_OFFSET 8 #define GPIO38_IN_MASK 0x00000100 #define GPIO38_WAKEUP_ENA_OFFSET 7 #define GPIO38_WAKEUP_ENA_MASK 0x00000080 #define GPIO38_INT_TYPE_OFFSET 4 #define GPIO38_INT_TYPE_MASK 0x00000070 #define GPIO38_INT_RAW_OFFSET 3 #define GPIO38_INT_RAW_MASK 0x00000008 #define GPIO38_INT_STS_OFFSET 2 #define GPIO38_INT_STS_MASK 0x00000004 #define GPIO38_INT_ENA_OFFSET 1 #define GPIO38_INT_ENA_MASK 0x00000002 #define GPIO38_INT_CLR_OFFSET 0 #define GPIO38_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO39_CFG_ADDR 0xbc #define GPIO39_OD_MODE_OFFSET 12 #define GPIO39_OD_MODE_MASK 0x00003000 #define GPIO39_OUT_OFFSET 11 #define GPIO39_OUT_MASK 0x00000800 #define GPIO39_OE_OFFSET 10 #define GPIO39_OE_MASK 0x00000400 #define GPIO39_IE_OFFSET 9 #define GPIO39_IE_MASK 0x00000200 #define GPIO39_IN_OFFSET 8 #define GPIO39_IN_MASK 0x00000100 #define GPIO39_WAKEUP_ENA_OFFSET 7 #define GPIO39_WAKEUP_ENA_MASK 0x00000080 #define GPIO39_INT_TYPE_OFFSET 4 #define GPIO39_INT_TYPE_MASK 0x00000070 #define GPIO39_INT_RAW_OFFSET 3 #define GPIO39_INT_RAW_MASK 0x00000008 #define GPIO39_INT_STS_OFFSET 2 #define GPIO39_INT_STS_MASK 0x00000004 #define GPIO39_INT_ENA_OFFSET 1 #define GPIO39_INT_ENA_MASK 0x00000002 #define GPIO39_INT_CLR_OFFSET 0 #define GPIO39_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO40_CFG_ADDR 0xc0 #define GPIO40_OD_MODE_OFFSET 12 #define GPIO40_OD_MODE_MASK 0x00003000 #define GPIO40_OUT_OFFSET 11 #define GPIO40_OUT_MASK 0x00000800 #define GPIO40_OE_OFFSET 10 #define GPIO40_OE_MASK 0x00000400 #define GPIO40_IE_OFFSET 9 #define GPIO40_IE_MASK 0x00000200 #define GPIO40_IN_OFFSET 8 #define GPIO40_IN_MASK 0x00000100 #define GPIO40_WAKEUP_ENA_OFFSET 7 #define GPIO40_WAKEUP_ENA_MASK 0x00000080 #define GPIO40_INT_TYPE_OFFSET 4 #define GPIO40_INT_TYPE_MASK 0x00000070 #define GPIO40_INT_RAW_OFFSET 3 #define GPIO40_INT_RAW_MASK 0x00000008 #define GPIO40_INT_STS_OFFSET 2 #define GPIO40_INT_STS_MASK 0x00000004 #define GPIO40_INT_ENA_OFFSET 1 #define GPIO40_INT_ENA_MASK 0x00000002 #define GPIO40_INT_CLR_OFFSET 0 #define GPIO40_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO41_CFG_ADDR 0xc4 #define GPIO41_OD_MODE_OFFSET 12 #define GPIO41_OD_MODE_MASK 0x00003000 #define GPIO41_OUT_OFFSET 11 #define GPIO41_OUT_MASK 0x00000800 #define GPIO41_OE_OFFSET 10 #define GPIO41_OE_MASK 0x00000400 #define GPIO41_IE_OFFSET 9 #define GPIO41_IE_MASK 0x00000200 #define GPIO41_IN_OFFSET 8 #define GPIO41_IN_MASK 0x00000100 #define GPIO41_WAKEUP_ENA_OFFSET 7 #define GPIO41_WAKEUP_ENA_MASK 0x00000080 #define GPIO41_INT_TYPE_OFFSET 4 #define GPIO41_INT_TYPE_MASK 0x00000070 #define GPIO41_INT_RAW_OFFSET 3 #define GPIO41_INT_RAW_MASK 0x00000008 #define GPIO41_INT_STS_OFFSET 2 #define GPIO41_INT_STS_MASK 0x00000004 #define GPIO41_INT_ENA_OFFSET 1 #define GPIO41_INT_ENA_MASK 0x00000002 #define GPIO41_INT_CLR_OFFSET 0 #define GPIO41_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO42_CFG_ADDR 0xc8 #define GPIO42_OD_MODE_OFFSET 12 #define GPIO42_OD_MODE_MASK 0x00003000 #define GPIO42_OUT_OFFSET 11 #define GPIO42_OUT_MASK 0x00000800 #define GPIO42_OE_OFFSET 10 #define GPIO42_OE_MASK 0x00000400 #define GPIO42_IE_OFFSET 9 #define GPIO42_IE_MASK 0x00000200 #define GPIO42_IN_OFFSET 8 #define GPIO42_IN_MASK 0x00000100 #define GPIO42_WAKEUP_ENA_OFFSET 7 #define GPIO42_WAKEUP_ENA_MASK 0x00000080 #define GPIO42_INT_TYPE_OFFSET 4 #define GPIO42_INT_TYPE_MASK 0x00000070 #define GPIO42_INT_RAW_OFFSET 3 #define GPIO42_INT_RAW_MASK 0x00000008 #define GPIO42_INT_STS_OFFSET 2 #define GPIO42_INT_STS_MASK 0x00000004 #define GPIO42_INT_ENA_OFFSET 1 #define GPIO42_INT_ENA_MASK 0x00000002 #define GPIO42_INT_CLR_OFFSET 0 #define GPIO42_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO43_CFG_ADDR 0xcc #define GPIO43_OD_MODE_OFFSET 12 #define GPIO43_OD_MODE_MASK 0x00003000 #define GPIO43_OUT_OFFSET 11 #define GPIO43_OUT_MASK 0x00000800 #define GPIO43_OE_OFFSET 10 #define GPIO43_OE_MASK 0x00000400 #define GPIO43_IE_OFFSET 9 #define GPIO43_IE_MASK 0x00000200 #define GPIO43_IN_OFFSET 8 #define GPIO43_IN_MASK 0x00000100 #define GPIO43_WAKEUP_ENA_OFFSET 7 #define GPIO43_WAKEUP_ENA_MASK 0x00000080 #define GPIO43_INT_TYPE_OFFSET 4 #define GPIO43_INT_TYPE_MASK 0x00000070 #define GPIO43_INT_RAW_OFFSET 3 #define GPIO43_INT_RAW_MASK 0x00000008 #define GPIO43_INT_STS_OFFSET 2 #define GPIO43_INT_STS_MASK 0x00000004 #define GPIO43_INT_ENA_OFFSET 1 #define GPIO43_INT_ENA_MASK 0x00000002 #define GPIO43_INT_CLR_OFFSET 0 #define GPIO43_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO44_CFG_ADDR 0xd0 #define GPIO44_OD_MODE_OFFSET 12 #define GPIO44_OD_MODE_MASK 0x00003000 #define GPIO44_OUT_OFFSET 11 #define GPIO44_OUT_MASK 0x00000800 #define GPIO44_OE_OFFSET 10 #define GPIO44_OE_MASK 0x00000400 #define GPIO44_IE_OFFSET 9 #define GPIO44_IE_MASK 0x00000200 #define GPIO44_IN_OFFSET 8 #define GPIO44_IN_MASK 0x00000100 #define GPIO44_WAKEUP_ENA_OFFSET 7 #define GPIO44_WAKEUP_ENA_MASK 0x00000080 #define GPIO44_INT_TYPE_OFFSET 4 #define GPIO44_INT_TYPE_MASK 0x00000070 #define GPIO44_INT_RAW_OFFSET 3 #define GPIO44_INT_RAW_MASK 0x00000008 #define GPIO44_INT_STS_OFFSET 2 #define GPIO44_INT_STS_MASK 0x00000004 #define GPIO44_INT_ENA_OFFSET 1 #define GPIO44_INT_ENA_MASK 0x00000002 #define GPIO44_INT_CLR_OFFSET 0 #define GPIO44_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO45_CFG_ADDR 0xd4 #define GPIO45_OD_MODE_OFFSET 12 #define GPIO45_OD_MODE_MASK 0x00003000 #define GPIO45_OUT_OFFSET 11 #define GPIO45_OUT_MASK 0x00000800 #define GPIO45_OE_OFFSET 10 #define GPIO45_OE_MASK 0x00000400 #define GPIO45_IE_OFFSET 9 #define GPIO45_IE_MASK 0x00000200 #define GPIO45_IN_OFFSET 8 #define GPIO45_IN_MASK 0x00000100 #define GPIO45_WAKEUP_ENA_OFFSET 7 #define GPIO45_WAKEUP_ENA_MASK 0x00000080 #define GPIO45_INT_TYPE_OFFSET 4 #define GPIO45_INT_TYPE_MASK 0x00000070 #define GPIO45_INT_RAW_OFFSET 3 #define GPIO45_INT_RAW_MASK 0x00000008 #define GPIO45_INT_STS_OFFSET 2 #define GPIO45_INT_STS_MASK 0x00000004 #define GPIO45_INT_ENA_OFFSET 1 #define GPIO45_INT_ENA_MASK 0x00000002 #define GPIO45_INT_CLR_OFFSET 0 #define GPIO45_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_GPIO46_CFG_ADDR 0xd8 #define GPIO46_OD_MODE_OFFSET 12 #define GPIO46_OD_MODE_MASK 0x00003000 #define GPIO46_OUT_OFFSET 11 #define GPIO46_OUT_MASK 0x00000800 #define GPIO46_OE_OFFSET 10 #define GPIO46_OE_MASK 0x00000400 #define GPIO46_IE_OFFSET 9 #define GPIO46_IE_MASK 0x00000200 #define GPIO46_IN_OFFSET 8 #define GPIO46_IN_MASK 0x00000100 #define GPIO46_WAKEUP_ENA_OFFSET 7 #define GPIO46_WAKEUP_ENA_MASK 0x00000080 #define GPIO46_INT_TYPE_OFFSET 4 #define GPIO46_INT_TYPE_MASK 0x00000070 #define GPIO46_INT_RAW_OFFSET 3 #define GPIO46_INT_RAW_MASK 0x00000008 #define GPIO46_INT_STS_OFFSET 2 #define GPIO46_INT_STS_MASK 0x00000004 #define GPIO46_INT_ENA_OFFSET 1 #define GPIO46_INT_ENA_MASK 0x00000002 #define GPIO46_INT_CLR_OFFSET 0 #define GPIO46_INT_CLR_MASK 0x00000001 //HW module read/write macro #define GPIO_READ_REG(addr) SOC_READ_REG(GPIO_BASEADDR + addr) #define GPIO_WRITE_REG(addr,value) SOC_WRITE_REG(GPIO_BASEADDR + addr,value)