//----------------------------------- #define CFG_MAC_CONF_ADDR 0x0000 #define ARPEN_OFFSET 31 #define ARPEN_MASK 0x80000000 #define SARC_OFFSET 28 #define SARC_MASK 0x70000000 #define IPC_OFFSET 27 #define IPC_MASK 0x08000000 #define IPG_OFFSET 24 #define IPG_MASK 0x07000000 #define GPSLCE_OFFSET 23 #define GPSLCE_MASK 0x00800000 #define S2KP_OFFSET 22 #define S2KP_MASK 0x00400000 #define CST_OFFSET 21 #define CST_MASK 0x00200000 #define ACS_OFFSET 20 #define ACS_MASK 0x00100000 #define WD_OFFSET 19 #define WD_MASK 0x00080000 #define BE_OFFSET 18 #define BE_MASK 0x00040000 #define JD_OFFSET 17 #define JD_MASK 0x00020000 #define JE_OFFSET 16 #define JE_MASK 0x00010000 #define PS_OFFSET 15 #define PS_MASK 0x00008000 #define FES_OFFSET 14 #define FES_MASK 0x00004000 #define DM_OFFSET 13 #define DM_MASK 0x00002000 #define LM_OFFSET 12 #define LM_MASK 0x00001000 #define ECRSFD_OFFSET 11 #define ECRSFD_MASK 0x00000800 #define DO_OFFSET 10 #define DO_MASK 0x00000400 #define DCRS_OFFSET 9 #define DCRS_MASK 0x00000200 #define DR_OFFSET 8 #define DR_MASK 0x00000100 #define BL_OFFSET 5 #define BL_MASK 0x00000060 #define DC_OFFSET 4 #define DC_MASK 0x00000010 #define PRELEN_OFFSET 2 #define PRELEN_MASK 0x0000000C #define TE_OFFSET 1 #define TE_MASK 0x00000002 #define RE_OFFSET 0 #define RE_MASK 0x00000001 //----------------------------------- #define CFG_MAC_EXT_CONF_ADDR 0x0004 #define EIPG_OFFSET 25 #define EIPG_MASK 0x3E000000 #define EIPGEN_OFFSET 24 #define EIPGEN_MASK 0x01000000 #define HDSMS_OFFSET 20 #define HDSMS_MASK 0x00700000 #define USP_OFFSET 18 #define USP_MASK 0x00040000 #define SPEN_OFFSET 17 #define SPEN_MASK 0x00020000 #define DCRCC_OFFSET 16 #define DCRCC_MASK 0x00010000 #define GPSL_OFFSET 0 #define GPSL_MASK 0x00003FFF //----------------------------------- #define CFG_MAC_PKT_FILTER_ADDR 0x0008 #define RA_OFFSET 31 #define RA_MASK 0x80000000 #define DNTU_OFFSET 21 #define DNTU_MASK 0x00200000 #define IPFE_OFFSET 20 #define IPFE_MASK 0x00100000 #define VTFE_OFFSET 16 #define VTFE_MASK 0x00010000 #define HPF_OFFSET 10 #define HPF_MASK 0x00000400 #define SAF_OFFSET 9 #define SAF_MASK 0x00000200 #define SAIF_OFFSET 8 #define SAIF_MASK 0x00000100 #define PCF_OFFSET 6 #define PCF_MASK 0x000000C0 #define DBF_OFFSET 5 #define DBF_MASK 0x00000020 #define PM_OFFSET 4 #define PM_MASK 0x00000010 #define DAIF_OFFSET 3 #define DAIF_MASK 0x00000008 #define HMC_OFFSET 2 #define HMC_MASK 0x00000004 #define HUC_OFFSET 1 #define HUC_MASK 0x00000002 //#define PR_OFFSET 0 //#define PR_MASK 0x00000001 //----------------------------------- #define CFG_MAC_WD_TO_ADDR 0x000c #define PWE_OFFSET 8 #define PWE_MASK 0x00000100 #define WTO_OFFSET 0 #define WTO_MASK 0x0000000F //----------------------------------- #define CFG_MAC_HASH_TB_REG0_ADDR 0x0010 #define HT31T0_OFFSET 0 #define HT31T0_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MAC_HASH_TB_REG1_ADDR 0x0014 #define HT64T32_OFFSET 0 #define HT64T32_MASK 0xFFFFFFFF //----------------------------------- #define CFG_TDMA_ST_REG_ADDR 0x0030 #define TDMA_ST_OFFSET 0 #define TDMA_ST_MASK 0x001FFFFF //----------------------------------- #define CFG_TDMA_WIDTH_REG_ADDR 0x0034 #define TDMA_WIDTH_OFFSET 0 #define TDMA_WIDTH_MASK 0x001FFFFF //----------------------------------- #define CFG_TDMA_PERIOD_REG_ADDR 0x0038 #define TDMA_EN_OFFSET 31 #define TDMA_EN_MASK 0x80000000 #define TDMA_PERIOD_OFFSET 0 #define TDMA_PERIOD_MASK 0x001FFFFF //----------------------------------- #define CFG_MAC_Q0_TX_FLOW_CTRL_ADDR 0x0070 #define PT0_OFFSET 16 #define PT0_MASK 0xFFFF0000 #define DZPQ0_OFFSET 7 #define DZPQ0_MASK 0x00000080 #define PLT0_OFFSET 4 #define PLT0_MASK 0x00000070 #define TFE0_OFFSET 1 #define TFE0_MASK 0x00000002 #define FCB_BPA0_OFFSET 0 #define FCB_BPA0_MASK 0x00000001 //----------------------------------- #define CFG_MAC_Q1_TX_FLOW_CTRL_ADDR 0x0074 #define PT1_OFFSET 16 #define PT1_MASK 0xFFFF0000 #define DZPQ1_OFFSET 7 #define DZPQ1_MASK 0x00000080 #define PLT1_OFFSET 4 #define PLT1_MASK 0x00000070 #define TFE1_OFFSET 1 #define TFE1_MASK 0x00000002 #define FCB_BPA1_OFFSET 0 #define FCB_BPA1_MASK 0x00000001 //----------------------------------- #define CFG_MAC_Q2_TX_FLOW_CTRL_ADDR 0x0078 #define PT2_OFFSET 16 #define PT2_MASK 0xFFFF0000 #define DZPQ2_OFFSET 7 #define DZPQ2_MASK 0x00000080 #define PLT2_OFFSET 4 #define PLT2_MASK 0x00000070 #define TFE2_OFFSET 1 #define TFE2_MASK 0x00000002 #define FCB_BPA2_OFFSET 0 #define FCB_BPA2_MASK 0x00000001 //----------------------------------- #define CFG_MAC_RX_FLOW_CTRL_ADDR 0x0090 #define PFCE_OFFSET 8 #define PFCE_MASK 0x00000100 #define UP_OFFSET 1 #define UP_MASK 0x00000002 #define RFE_OFFSET 0 #define RFE_MASK 0x00000001 //----------------------------------- #define CFG_MAC_RXQ_CTRL4_ADDR 0x0094 #define MFFQ_OFFSET 9 #define MFFQ_MASK 0x00000200 #define MFFQE_OFFSET 8 #define MFFQE_MASK 0x00000100 #define UFFQ_OFFSET 1 #define UFFQ_MASK 0x00000002 #define UFFQE_OFFSET 0 #define UFFQE_MASK 0x00000001 //----------------------------------- #define CFG_MAC_TXQ_PRTY_MAP0_ADDR 0x0098 #define PSTQ3_OFFSET 24 #define PSTQ3_MASK 0xFF000000 #define PSTQ2_OFFSET 16 #define PSTQ2_MASK 0x00FF0000 #define PSTQ1_OFFSET 8 #define PSTQ1_MASK 0x0000FF00 #define PSTQ0_OFFSET 0 #define PSTQ0_MASK 0x000000FF //----------------------------------- #define CFG_MAC_RXQ_CTRL0_ADDR 0x00A0 #define RXQ7EN_OFFSET 14 #define RXQ7EN_MASK 0x0000C000 #define RXQ6EN_OFFSET 12 #define RXQ6EN_MASK 0x00003000 #define RXQ5EN_OFFSET 10 #define RXQ5EN_MASK 0x00000C00 #define RXQ4EN_OFFSET 8 #define RXQ4EN_MASK 0x00000300 #define RXQ3EN_OFFSET 6 #define RXQ3EN_MASK 0x000000C0 #define RXQ2EN_OFFSET 4 #define RXQ2EN_MASK 0x00000030 #define RXQ1EN_OFFSET 2 #define RXQ1EN_MASK 0x0000000C #define RXQ0EN_OFFSET 0 #define RXQ0EN_MASK 0x00000003 //----------------------------------- #define CFG_MAC_RXQ_CTRL1_ADDR 0x00A4 #define TPQC_OFFSET 22 #define TPQC_MASK 0x00400000 #define TACPQE_OFFSET 21 #define TACPQE_MASK 0x00200000 #define MCBCQEN_OFFSET 20 #define MCBCQEN_MASK 0x00100000 #define MCBCQ_OFFSET 16 #define MCBCQ_MASK 0x00070000 #define UPQ_OFFSET 12 #define UPQ_MASK 0x00007000 #define DCBCPQ_OFFSET 8 #define DCBCPQ_MASK 0x00000700 #define PTPQ_OFFSET 4 #define PTPQ_MASK 0x00000070 #define AVCPQ_OFFSET 0 #define AVCPQ_MASK 0x00000007 //----------------------------------- #define CFG_MAC_RXQ_CTRL2_ADDR 0x00A8 #define PSRQ3_OFFSET 24 #define PSRQ3_MASK 0xFF000000 #define PSRQ2_OFFSET 16 #define PSRQ2_MASK 0x00FF0000 #define PSRQ1_OFFSET 8 #define PSRQ1_MASK 0x0000FF00 #define PSRQ0_OFFSET 0 #define PSRQ0_MASK 0x000000FF //----------------------------------- #define CFG_MAC_INT_ST_ADDR 0x00B0 #define GPIIS_OFFSET 15 #define GPIIS_MASK 0x00008000 #define RXSTSIS_OFFSET 14 #define RXSTSIS_MASK 0x00004000 #define TXSTSIS_OFFSET 13 #define TXSTSIS_MASK 0x00002000 #define TSIS_OFFSET 12 #define TSIS_MASK 0x00001000 #define MMCRXIPIS_OFFSET 11 #define MMCRXIPIS_MASK 0x00000800 #define MMCTXIS_OFFSET 10 #define MMCTXIS_MASK 0x00000400 #define MMCRXIS_OFFSET 9 #define MMCRXIS_MASK 0x00000200 #define MMCIS_OFFSET 8 #define MMCIS_MASK 0x00000100 #define LPIIS_OFFSET 5 #define LPIIS_MASK 0x00000020 #define PMTIS_OFFSET 4 #define PMTIS_MASK 0x00000010 #define PHYIS_OFFSET 3 #define PHYIS_MASK 0x00000008 #define PCSANCIS_OFFSET 2 #define PCSANCIS_MASK 0x00000004 #define PCSLCHGIS_OFFSET 1 #define PCSLCHGIS_MASK 0x00000002 #define RGSMIIIS_OFFSET 0 #define RGSMIIIS_MASK 0x00000001 //----------------------------------- #define CFG_MAC_INT_EN_ADDR 0x00B4 #define RXSTSIE_OFFSET 14 #define RXSTSIE_MASK 0x00004000 #define TXSTSIE_OFFSET 13 #define TXSTSIE_MASK 0x00002000 #define TSIE_OFFSET 12 #define TSIE_MASK 0x00001000 #define LPIIE_OFFSET 5 #define LPIIE_MASK 0x00000020 #define PMTIE_OFFSET 4 #define PMTIE_MASK 0x00000010 #define PHYIE_OFFSET 3 #define PHYIE_MASK 0x00000008 #define PCSANCIE_OFFSET 2 #define PCSANCIE_MASK 0x00000004 #define PCSLCHGIE_OFFSET 1 #define PCSLCHGIE_MASK 0x00000002 #define RGSMIIIE_OFFSET 0 #define RGSMIIIE_MASK 0x00000001 //----------------------------------- #define CFG_MAC_RX_TX_ST_ADDR 0x00B8 //#define RWT_OFFSET 8 //#define RWT_MASK 0x00000100 #define EXCOL_OFFSET 5 #define EXCOL_MASK 0x00000020 #define LCOL_OFFSET 4 #define LCOL_MASK 0x00000010 #define EXDEF_OFFSET 3 #define EXDEF_MASK 0x00000008 #define LCARR_OFFSET 2 #define LCARR_MASK 0x00000004 #define NCARR_OFFSET 1 #define NCARR_MASK 0x00000002 #define TJT_OFFSET 0 #define TJT_MASK 0x00000001 #define CFG_MAC_MDIO_ADDR 0x0200 #define PA_OFFSET 21 #define PA_MASK 0x03E00000 #define RDA_OFFSET 16 #define RDA_MASK 0x001F0000 #define CR_OFFSET 8 #define CR_MASK 0x00000F00 #define GOC_OFFSET 2 #define GOC_MASK 0x0000000C #define GMII_BUSY_OFFSET 0 #define GMII_BUSY_MASK 0x00000001 #define CFG_MAC_MDIO_DATA 0x0204 #define GD_OFFSET 0 #define GD_MASK 0x0000FFFF //----------------------------------- #define CFG_MAC_ADDR0_H_ADDR 0x0300 #define AE_OFFSET 31 #define AE_MASK 0x80000000 #define DCS_OFFSET 16 #define DCS_MASK 0x00010000 #define ADDRHI_OFFSET 0 #define ADDRHI_MASK 0x0000FFFF //----------------------------------- #define CFG_MAC_ADDR0_L_ADDR 0x0304 #define ADDRLO_OFFSET 0 #define ADDRLO_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MAC_ADDR1_H_ADDR 0x0308 #define AE_OFFSET 31 #define AE_MASK 0x80000000 #define SA_OFFSET 30 #define SA_MASK 0x40000000 #define MBC_OFFSET 24 #define MBC_MASK 0x00000000 #define DCS_OFFSET 16 #define DCS_MASK 0x00010000 #define ADDRHI_OFFSET 0 #define ADDRHI_MASK 0x0000FFFF //----------------------------------- #define CFG_MAC_ADDR1_L_ADDR 0x030c #define ADDRLO_OFFSET 0 #define ADDRLO_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MAC_ADDR2_H_ADDR 0x0310 #define AE_OFFSET 31 #define AE_MASK 0x80000000 #define SA_OFFSET 30 #define SA_MASK 0x40000000 #define MBC_OFFSET 24 #define MBC_MASK 0x00000000 #define DCS_OFFSET 16 #define DCS_MASK 0x00010000 #define ADDRHI_OFFSET 0 #define ADDRHI_MASK 0x0000FFFF //----------------------------------- #define CFG_MAC_ADDR2_L_ADDR 0x0314 #define ADDRLO_OFFSET 0 #define ADDRLO_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MAC_ADDR3_H_ADDR 0x0318 #define AE_OFFSET 31 #define AE_MASK 0x80000000 #define SA_OFFSET 30 #define SA_MASK 0x40000000 #define MBC_OFFSET 24 #define MBC_MASK 0x00000000 #define DCS_OFFSET 16 #define DCS_MASK 0x00010000 #define ADDRHI_OFFSET 0 #define ADDRHI_MASK 0x0000FFFF //----------------------------------- #define CFG_MAC_ADDR3_L_ADDR 0x031c #define ADDRLO_OFFSET 0 #define ADDRLO_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MMC_RX_INT_MASK_ADDR 0x070C #define MMC_RX_INT_MASK_OFFSET 0 #define MMC_RX_INT_MASK_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MMC_TX_INT_MASK_ADDR 0x0710 #define MMC_TX_INT_MASK_OFFSET 0 #define MMC_TX_INT_MASK_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MMC_IPC_RX_INT_MASK_ADDR 0x0800 #define MMC_IPC_RX_INT_MASK_OFFSET 0 #define MMC_IPC_RX_INT_MASK_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MAC_TS_CTRL_ADDR 0x0b00 #define AV8021ASMEN_OFFSET 28 #define AV8021ASMEN_MASK 0x10000000 #define TXTSSTSM_OFFSET 24 #define TXTSSTSM_MASK 0x01000000 #define ESTI_OFFSET 20 #define ESTI_MASK 0x00100000 #define CSC_OFFSET 19 #define CSC_MASK 0x00080000 #define TSENMACADDR_OFFSET 18 #define TSENMACADDR_MASK 0x00040000 #define SNAPTYPSEL_OFFSET 16 #define SNAPTYPSEL_MASK 0x00030000 #define TSMSTRENA_OFFSET 15 #define TSMSTRENA_MASK 0x00008000 #define TSEVNTENA_OFFSET 14 #define TSEVNTENA_MASK 0x00004000 #define TSIPV4ENA_OFFSET 13 #define TSIPV4ENA_MASK 0x00002000 #define TSIPV6ENA_OFFSET 12 #define TSIPV6ENA_MASK 0x00001000 #define TSIPENA_OFFSET 11 #define TSIPENA_MASK 0x00000800 #define TSVER2ENA_OFFSET 10 #define TSVER2ENA_MASK 0x00000400 #define TSCTRLSSR_OFFSET 9 #define TSCTRLSSR_MASK 0x00000200 #define TSENALL_OFFSET 8 #define TSENALL_MASK 0x00000100 #define TSADDREG_OFFSET 5 #define TSADDREG_MASK 0x00000020 #define TSTRIG_OFFSET 4 #define TSTRIG_MASK 0x00000010 #define TSUPDT_OFFSET 3 #define TSUPDT_MASK 0x00000008 #define TSINIT_OFFSET 2 #define TSINIT_MASK 0x00000004 #define TSCFUPDT_OFFSET 1 #define TSCFUPDT_MASK 0x00000002 #define TSENA_OFFSET 0 #define TSENA_MASK 0x00000001 //----------------------------------- #define CFG_MAC_SUB_SEC_INC_ADDR 0x0b04 #define SSINC_OFFSET 16 #define SSINC_MASK 0x00FF0000 #define SNSINC_OFFSET 8 #define SNSINC_MASK 0x0000FF00 //----------------------------------- #define CFG_MAC_SYS_TIME_SEC_ADDR 0x0b08 #define TSS_OFFSET 0 #define TSS_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MAC_SYS_TIME_NAN_ADDR 0x0b0c #define TSSS_OFFSET 0 #define TSSS_MASK 0x7FFFFFFF //----------------------------------- #define CFG_MAC_SYST_SEC_UP_ADDR 0x0b10 #define TSS_UP_OFFSET 0 #define TSS_UP_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MAC_SYST_NAN_UP_ADDR 0x0b14 #define ADDSUB_OFFSET 31 #define ADDSUB_MASK 0x80000000 #define TSSS_UP_OFFSET 0 #define TSSS_UP_MASK 0x7FFFFFFF //----------------------------------- #define CFG_MAC_TS_ADDEND_ADDR 0x0b18 #define TSAR_OFFSET 0 #define TSAR_MASK 0xFFFFFFFF //----------------------------------- #define CFG_MTL_OP_MODE_ADDR 0x0c00 #define CNTCLR_OFFSET 9 #define CNTCLR_MASK 0x00000200 #define CNTPRST_OFFSET 8 #define CNTPRST_MASK 0x00000100 #define SCHALG_OFFSET 5 #define SCHALG_MASK 0x00000060 #define RAA_OFFSET 2 #define RAA_MASK 0x00000004 #define DTXSTS_OFFSET 1 #define DTXSTS_MASK 0x00000002 //----------------------------------- #define CFG_MTL_INT_ST_ADDR 0x0c20 #define DBGIS_OFFSET 17 #define DBGIS_MASK 0x00020000 //#define MACIS_OFFSET 16 //#define MACIS_MASK 0x00010000 #define Q7IS_OFFSET 7 #define Q7IS_MASK 0x00000080 #define Q6IS_OFFSET 6 #define Q6IS_MASK 0x00000040 #define Q5IS_OFFSET 5 #define Q5IS_MASK 0x00000020 #define Q4IS_OFFSET 4 #define Q4IS_MASK 0x00000010 #define Q3IS_OFFSET 3 #define Q3IS_MASK 0x00000008 #define Q2IS_OFFSET 2 #define Q2IS_MASK 0x00000004 #define Q1IS_OFFSET 1 #define Q1IS_MASK 0x00000002 #define Q0IS_OFFSET 0 #define Q0IS_MASK 0x00000001 //----------------------------------- #define CFG_MTL_RXQ_DMA_MAP_ADDR 0x0c30 //#define Q1DDMACH_OFFSET 12 //#define Q1DDMACH_MASK 0x00001000 //#define Q1MDMACH_OFFSET 8 //#define Q1MDMACH_MASK 0x00000100 //#define Q0DDMACH_OFFSET 4 //#define Q0DDMACH_MASK 0x00000010 //#define Q0MDMACH_OFFSET 0 //#define Q0MDMACH_MASK 0x00000001 //----------------------------------- #define CFG_MTL_TXQ_OP_MODE_ADDR 0x0d00 #define TQS_OFFSET 16 #define TQS_MASK 0x00030000 #define TTC_OFFSET 4 #define TTC_MASK 0x00000070 #define TXQEN_OFFSET 2 #define TXQEN_MASK 0x0000000C #define TSF_OFFSET 1 #define TSF_MASK 0x00000002 #define FTQ_OFFSET 0 #define FTQ_MASK 0x00000001 //----------------------------------- #define CFG_MTL_TXQ_QUAN_WT_ADDR 0x0d18 #define Q0MDMACH_OFFSET 0 #define Q0MDMACH_MASK 0x001FFFFF #define CFG_MTL_RXQ_OP_MODE_ADDR 0x0d30 #define RQS_OFFSET 20 #define RQS_MASK 0x00300000 //----------------------------------- #define CFG_DMA_MODE_ADDR 0x1000 #define INTM_OFFSET 16 #define INTM_MASK 0x00030000 #define PR_OFFSET 12 #define PR_MASK 0x00007000 #define TXPR_OFFSET 11 #define TXPR_MASK 0x00000800 #define DSPW_OFFSET 8 #define DSPW_MASK 0x00000100 #define TAA_OFFSET 2 #define TAA_MASK 0x0000001C #define DA_OFFSET 1 #define DA_MASK 0x00000002 #define SWR_OFFSET 0 #define SWR_MASK 0x00000001 //----------------------------------- #define CFG_DMA_SYSBUS_MODE_ADDR 0x1004 #define RB_OFFSET 15 #define RB_MASK 0x00008000 #define MB_OFFSET 14 #define MB_MASK 0x00004000 #define AAL_OFFSET 12 #define AAL_MASK 0x00001000 #define BLEN8_OFFSET 2 #define BLEN8_MASK 0x00000004 #define FB_OFFSET 0 #define FB_MASK 0x00000001 //----------------------------------- #define CFG_DMA_INT_ST_ADDR 0x1008 #define MACIS_OFFSET 17 #define MACIS_MASK 0x00020000 #define MTLIS_OFFSET 16 #define MTLIS_MASK 0x00010000 #define DC7IS_OFFSET 7 #define DC7IS_MASK 0x00000080 #define DC6IS_OFFSET 6 #define DC6IS_MASK 0x00000040 #define DC5IS_OFFSET 5 #define DC5IS_MASK 0x00000020 #define DC4IS_OFFSET 4 #define DC4IS_MASK 0x00000010 #define DC3IS_OFFSET 3 #define DC3IS_MASK 0x00000008 #define DC2IS_OFFSET 2 #define DC2IS_MASK 0x00000004 #define DC1IS_OFFSET 1 #define DC1IS_MASK 0x00000002 #define DC0IS_OFFSET 0 #define DC0IS_MASK 0x00000001 //----------------------------------- #define CFG_DMA_CH_CTRL_ADDR 0x1100 #define DSL_OFFSET 18 #define DSL_MASK 0x001C0000 #define PBLX8_OFFSET 16 #define PBLX8_MASK 0x00010000 #define MSS_OFFSET 0 #define MSS_MASK 0x00003FFF //----------------------------------- #define CFG_DMA_CH_TX_CTRL_ADDR 0x1104 #define TXPBL_OFFSET 16 #define TXPBL_MASK 0x003F0000 #define OSF_OFFSET 4 #define OSF_MASK 0x00000010 #define TCW_OFFSET 1 #define TCW_MASK 0x0000000E #define ST_OFFSET 0 #define ST_MASK 0x00000001 //----------------------------------- #define CFG_DMA_CH_RX_CTRL_ADDR 0x1108 #define RPF_OFFSET 31 #define RPF_MASK 0x80000000 #define RXPBL_OFFSET 16 #define RXPBL_MASK 0x003F0000 #define RBSZ_13_Y_OFFSET 3 #define RBSZ_13_Y_MASK 0x00007FF8 #define RBSZ_X_0_OFFSET 1 #define RBSZ_X_0_MASK 0x00000006 #define SR_OFFSET 0 #define SR_MASK 0x00000001 //----------------------------------- #define CFG_DMA_CH_TXDES_LS_ADDR 0x1114 #define TDESLA_OFFSET 2 #define TDESLA_MASK 0xFFFFFFFC //----------------------------------- #define CFG_DMA_CH_RXDES_LS_ADDR 0x111c #define RDESLA_OFFSET 2 #define RDESLA_MASK 0xFFFFFFFC //----------------------------------- #define CFG_DMA_CH_TXDES_TL_ADDR 0x1120 #define TDTP_OFFSET 2 #define TDTP_MASK 0xFFFFFFFC //----------------------------------- #define CFG_DMA_CH_RXDES_TL_ADDR 0x1128 #define RDTP_OFFSET 2 #define RDTP_MASK 0xFFFFFFFC //----------------------------------- #define CFG_DMA_CH_TXDES_LEN_ADDR 0x112c #define TDRL_OFFSET 0 #define TDRL_MASK 0x000003FF //----------------------------------- #define CFG_DMA_CH_RXDES_LEN_ADDR 0x1130 #define RDRL_OFFSET 0 #define RDRL_MASK 0x000003FF //----------------------------------- #define CFG_DMA_CH_INT_EN_ADDR 0x1134 #define NIE_OFFSET 15 #define NIE_MASK 0x00008000 #define AIE_OFFSET 14 #define AIE_MASK 0x00004000 #define CDEE_OFFSET 13 #define CDEE_MASK 0x00002000 #define FBEE_OFFSET 12 #define FBEE_MASK 0x00001000 #define ERIE_OFFSET 11 #define ERIE_MASK 0x00000800 #define ETIE_OFFSET 10 #define ETIE_MASK 0x00000400 #define RWTE_OFFSET 9 #define RWTE_MASK 0x00000200 #define RSE_OFFSET 8 #define RSE_MASK 0x00000100 #define RBUE_OFFSET 7 #define RBUE_MASK 0x00000080 #define RIE_OFFSET 6 #define RIE_MASK 0x00000040 #define TBUE_OFFSET 2 #define TBUE_MASK 0x00000004 #define TXSE_OFFSET 1 #define TXSE_MASK 0x00000002 #define TIE_OFFSET 0 #define TIE_MASK 0x00000001 //----------------------------------- #define CFG_DMA_CH_ST_ADDR 0x1160 #define REB_OFFSET 19 #define REB_MASK 0x00380000 #define TEB_OFFSET 16 #define TEB_MASK 0x00070000 #define NIS_OFFSET 15 #define NIS_MASK 0x00008000 #define AIS_OFFSET 14 #define AIS_MASK 0x00004000 #define CDE_OFFSET 13 #define CDE_MASK 0x00002000 #define FBE_OFFSET 12 #define FBE_MASK 0x00001000 #define ERI_OFFSET 11 #define ERI_MASK 0x00000800 #define ETI_OFFSET 10 #define ETI_MASK 0x00000400 #define RWT_OFFSET 9 #define RWT_MASK 0x00000200 #define RPS_OFFSET 8 #define RPS_MASK 0x00000100 #define RBU_OFFSET 7 #define RBU_MASK 0x00000080 #define RI_OFFSET 6 #define RI_MASK 0x00000040 #define TBU_OFFSET 2 #define TBU_MASK 0x00000004 #define TPS_OFFSET 1 #define TPS_MASK 0x00000002 #define TI_OFFSET 0 #define TI_MASK 0x00000001 //HW module read/write macro #define GMAC_READ_REG(addr) SOC_READ_REG(GMAC_BASEADDR + addr) #define GMAC_WRITE_REG(addr,value) SOC_WRITE_REG(GMAC_BASEADDR + addr,value)