//----------------------------------- #define CFG_I2SCONF_ADDR 0x0008 #define REG_BCK_DIV_NUM_OFFSET 22 #define REG_BCK_DIV_NUM_MASK 0x0FC00000 #define REG_CLKM_DIV_NUM_OFFSET 16 #define REG_CLKM_DIV_NUM_MASK 0x003F0000 #define REG_BITS_MOD_OFFSET 12 #define REG_BITS_MOD_MASK 0x0000F000 #define REG_RECE_MSB_SHIFT_OFFSET 11 #define REG_RECE_MSB_SHIFT_MASK 0x00000800 #define REG_TRANS_MSB_SHIFT_OFFSET 10 #define REG_TRANS_MSB_SHIFT_MASK 0x00000400 #define I2S_RX_START_OFFSET 9 #define I2S_RX_START_MASK 0x00000200 #define I2S_TX_START_OFFSET 8 #define I2S_TX_START_MASK 0x00000100 #define REG_MSB_RIGHT_OFFSET 7 #define REG_MSB_RIGHT_MASK 0x00000080 #define REG_RIGHT_FIRST_OFFSET 6 #define REG_RIGHT_FIRST_MASK 0x00000040 #define REG_RECE_SLAVE_MOD_OFFSET 5 #define REG_RECE_SLAVE_MOD_MASK 0x00000020 #define REG_TRANS_SLAVE_MOD_OFFSET 4 #define REG_TRANS_SLAVE_MOD_MASK 0x00000010 #define I2S_RX_FIFO_RESET_OFFSET 3 #define I2S_RX_FIFO_RESET_MASK 0x00000008 #define I2S_TX_FIFO_RESET_OFFSET 2 #define I2S_TX_FIFO_RESET_MASK 0x00000004 #define I2S_RX_RESET_OFFSET 1 #define I2S_RX_RESET_MASK 0x00000002 #define I2S_TX_RESET_OFFSET 0 #define I2S_TX_RESET_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_RAW_ADDR 0x000C #define I2S_TX_REMPTY_INT_RAW_OFFSET 5 #define I2S_TX_REMPTY_INT_RAW_MASK 0x00000020 #define I2S_TX_WFULL_INT_RAW_OFFSET 4 #define I2S_TX_WFULL_INT_RAW_MASK 0x00000010 #define I2S_RX_REMPTY_INT_RAW_OFFSET 3 #define I2S_RX_REMPTY_INT_RAW_MASK 0x00000008 #define I2S_RX_WFULL_INT_RAW_OFFSET 2 #define I2S_RX_WFULL_INT_RAW_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_RAW_OFFSET 1 #define I2S_TX_PUT_DATA_INT_RAW_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_RAW_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_RAW_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_ST_ADDR 0x0010 #define I2S_TX_REMPTY_INT_ST_OFFSET 5 #define I2S_TX_REMPTY_INT_ST_MASK 0x00000020 #define I2S_TX_WFULL_INT_ST_OFFSET 4 #define I2S_TX_WFULL_INT_ST_MASK 0x00000010 #define I2S_RX_REMPTY_INT_ST_OFFSET 3 #define I2S_RX_REMPTY_INT_ST_MASK 0x00000008 #define I2S_RX_WFULL_INT_ST_OFFSET 2 #define I2S_RX_WFULL_INT_ST_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_ST_OFFSET 1 #define I2S_TX_PUT_DATA_INT_ST_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_ST_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_ST_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_ENA_ADDR 0x0014 #define I2S_TX_REMPTY_INT_ENA_OFFSET 5 #define I2S_TX_REMPTY_INT_ENA_MASK 0x00000020 #define I2S_TX_WFULL_INT_ENA_OFFSET 4 #define I2S_TX_WFULL_INT_ENA_MASK 0x00000010 #define I2S_RX_REMPTY_INT_ENA_OFFSET 3 #define I2S_RX_REMPTY_INT_ENA_MASK 0x00000008 #define I2S_RX_WFULL_INT_ENA_OFFSET 2 #define I2S_RX_WFULL_INT_ENA_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_ENA_OFFSET 1 #define I2S_TX_PUT_DATA_INT_ENA_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_ENA_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_ENA_MASK 0x00000001 //----------------------------------- #define CFG_I2SINT_CLR_ADDR 0x0018 #define I2S_TX_REMPTY_INT_CLR_OFFSET 5 #define I2S_TX_REMPTY_INT_CLR_MASK 0x00000020 #define I2S_TX_WFULL_INT_CLR_OFFSET 4 #define I2S_TX_WFULL_INT_CLR_MASK 0x00000010 #define I2S_RX_REMPTY_INT_CLR_OFFSET 3 #define I2S_RX_REMPTY_INT_CLR_MASK 0x00000008 #define I2S_RX_WFULL_INT_CLR_OFFSET 2 #define I2S_RX_WFULL_INT_CLR_MASK 0x00000004 #define I2S_TX_PUT_DATA_INT_CLR_OFFSET 1 #define I2S_TX_PUT_DATA_INT_CLR_MASK 0x00000002 #define I2S_RX_TAKE_DATA_INT_CLR_OFFSET 0 #define I2S_RX_TAKE_DATA_INT_CLR_MASK 0x00000001 //----------------------------------- #define CFG_I2STIMING_ADDR 0x001C #define REG_TRANS_BCK_IN_INV_OFFSET 22 #define REG_TRANS_BCK_IN_INV_MASK 0x00400000 #define REG_RECE_DSYNC_SW_OFFSET 21 #define REG_RECE_DSYNC_SW_MASK 0x00200000 #define REG_TRANS_DSYNC_SW_OFFSET 20 #define REG_TRANS_DSYNC_SW_MASK 0x00100000 #define REG_RECE_BCK_OUT_DELAY_OFFSET 18 #define REG_RECE_BCK_OUT_DELAY_MASK 0x000C0000 #define REG_RECE_WS_OUT_DELAY_OFFSET 16 #define REG_RECE_WS_OUT_DELAY_MASK 0x00030000 #define REG_TRANS_SD_OUT_DELAY_OFFSET 14 #define REG_TRANS_SD_OUT_DELAY_MASK 0x0000C000 #define REG_TRANS_WS_OUT_DELAY_OFFSET 12 #define REG_TRANS_WS_OUT_DELAY_MASK 0x00003000 #define REG_TRANS_BCK_OUT_DELAY_OFFSET 10 #define REG_TRANS_BCK_OUT_DELAY_MASK 0x00000C00 #define REG_RECE_SD_IN_DELAY_OFFSET 8 #define REG_RECE_SD_IN_DELAY_MASK 0x00000300 #define REG_RECE_WS_IN_DELAY_OFFSET 6 #define REG_RECE_WS_IN_DELAY_MASK 0x000000C0 #define REG_RECE_BCK_IN_DELAY_OFFSET 4 #define REG_RECE_BCK_IN_DELAY_MASK 0x00000030 #define REG_TRANS_WS_IN_DELAY_OFFSET 2 #define REG_TRANS_WS_IN_DELAY_MASK 0x0000000C #define REG_TRANS_BCK_IN_DELAY_OFFSET 0 #define REG_TRANS_BCK_IN_DELAY_MASK 0x00000003 //----------------------------------- #define CFG_I2S_FIFO_CONF_ADDR 0x0020 #define REG_I2S_RX_FIFO_MOD_OFFSET 16 #define REG_I2S_RX_FIFO_MOD_MASK 0x00070000 #define REG_I2S_TX_FIFO_MOD_OFFSET 13 #define REG_I2S_TX_FIFO_MOD_MASK 0x0000E000 #define REG_I2S_DSCR_EN_OFFSET 12 #define REG_I2S_DSCR_EN_MASK 0x00001000 #define REG_I2S_TX_DATA_NUM_OFFSET 6 #define REG_I2S_TX_DATA_NUM_MASK 0x00000FC0 #define REG_I2S_RX_DATA_NUM_OFFSET 0 #define REG_I2S_RX_DATA_NUM_MASK 0x0000003F //----------------------------------- #define CFG_I2SRXEOF_NUM_ADDR 0x0024 #define REG_I2S_RX_EOF_NUM_OFFSET 0 #define REG_I2S_RX_EOF_NUM_MASK 0xFFFFFFFF //----------------------------------- #define CFG_I2SCONF_SIGLE_DATA_ADDR 0x0028 #define REG_I2S_SIGLE_DATA_OFFSET 0 #define REG_I2S_SIGLE_DATA_MASK 0xFFFFFFFF //----------------------------------- #define CFG_I2SCONF_CHAN_ADDR 0x002C #define REG_RX_CHAN_MOD_OFFSET 3 #define REG_RX_CHAN_MOD_MASK 0x00000018 #define REG_TX_CHAN_MOD_OFFSET 0 #define REG_TX_CHAN_MOD_MASK 0x00000007 //----------------------------------- #define CFG_PDM_CFG0_ADDR 0x0030 #define REG_PDM_SADC_HP_BYPASS_OFFSET 7 #define REG_PDM_SADC_HP_BYPASS_MASK 0x00000080 #define REG_PDM_SADC_64BIT_OFFSET 6 #define REG_PDM_SADC_64BIT_MASK 0x00000040 #define REG_PDM_SADC_DUMP_OFFSET 5 #define REG_PDM_SADC_DUMP_MASK 0x00000020 #define REG_PDM_SADC_EN_OFFSET 4 #define REG_PDM_SADC_EN_MASK 0x00000010 #define REG_SINC_DSAMP_OFFSET 2 #define REG_SINC_DSAMP_MASK 0x0000000C #define REG_SINC_ORDER_OFFSET 0 #define REG_SINC_ORDER_MASK 0x00000003 //----------------------------------- #define CFG_PDM_CFG1_ADDR 0x0034 #define REG_HP_SCALE_CHN3_OFFSET 28 #define REG_HP_SCALE_CHN3_MASK 0xF0000000 #define REG_HP_SCALE_CHN2_OFFSET 24 #define REG_HP_SCALE_CHN2_MASK 0x0F000000 #define REG_HP_SCALE_CHN1_OFFSET 20 #define REG_HP_SCALE_CHN1_MASK 0x00F00000 #define REG_HP_SCALE_CHN0_OFFSET 16 #define REG_HP_SCALE_CHN0_MASK 0x000F0000 #define REG_LP_SCALE_CHN3_OFFSET 12 #define REG_LP_SCALE_CHN3_MASK 0x0000F000 #define REG_LP_SCALE_CHN2_OFFSET 8 #define REG_LP_SCALE_CHN2_MASK 0x00000F00 #define REG_LP_SCALE_CHN1_OFFSET 4 #define REG_LP_SCALE_CHN1_MASK 0x000000F0 #define REG_LP_SCALE_CHN0_OFFSET 0 #define REG_LP_SCALE_CHN0_MASK 0x0000000F //----------------------------------- #define CFG_PDM_TX_CFG_ADDR 0x0038 #define REG_PDM_TX_SLAVE_MOD_OFFSET 14 #define REG_PDM_TX_SLAVE_MOD_MASK 0x00004000 #define REG_PDM_TX_SD_SCALE_OFFSET 12 #define REG_PDM_TX_SD_SCALE_MASK 0x00003000 #define REG_PDM_TX_EN_OFFSET 10 #define REG_PDM_TX_EN_MASK 0x00000400 #define REG_PDM_TX_BCK_DIV_OFFSET 4 #define REG_PDM_TX_BCK_DIV_MASK 0x000003F0 #define REG_PDM_TX_SINC16_OFFSET 3 #define REG_PDM_TX_SINC16_MASK 0x00000008 #define REG_PDM_TX_HP_BYPASS_OFFSET 2 #define REG_PDM_TX_HP_BYPASS_MASK 0x00000004 #define REG_PDM_TX_PHASE_OFFSET 0 #define REG_PDM_TX_PHASE_MASK 0x00000003 //----------------------------------- #define CFG_PDM_RX_CFG_ADDR 0x003c #define REG_RX_SLAVE_MOD_OFFSET 14 #define REG_RX_SLAVE_MOD_MASK 0x00004000 #define REG_RX_HP_DOWNSAMPLE_OFFSET 12 #define REG_RX_HP_DOWNSAMPLE_MASK 0x00003000 #define REG_PDM_RX_EN_OFFSET 10 #define REG_PDM_RX_EN_MASK 0x00000400 #define REG_PDM_RX_BCK_DIV_OFFSET 4 #define REG_PDM_RX_BCK_DIV_MASK 0x000003F0 #define REG_PDM_RX_SINC16_OFFSET 3 #define REG_PDM_RX_SINC16_MASK 0x00000008 #define REG_PDM_RX_HP_BYPASS_OFFSET 2 #define REG_PDM_RX_HP_BYPASS_MASK 0x00000004 #define REG_PDM_RX_PHASE_OFFSET 0 #define REG_PDM_RX_PHASE_MASK 0x00000003 //----------------------------------- #define CFG_I2SCONF_NEW_ADDR 0x0040 #define DMA_POP_WORD_HWORD_SEL_OFFSET 16 #define DMA_POP_WORD_HWORD_SEL_MASK 0x00010000 #define REG_TRANS_START_SEL_OFFSET 9 #define REG_TRANS_START_SEL_MASK 0x00000200 #define REG_RECE_START_SEL_OFFSET 8 #define REG_RECE_START_SEL_MASK 0x00000100 #define REG_RECE_TDM_MOD_OFFSET 6 #define REG_RECE_TDM_MOD_MASK 0x00000040 #define REG_RECE_PCM_MOD_OFFSET 5 #define REG_RECE_PCM_MOD_MASK 0x00000020 #define REG_RECE_TDM_CHN_NUM_OFFSET 0 #define REG_RECE_TDM_CHN_NUM_MASK 0x0000001F //HW module read/write macro #define I2S0_READ_REG(addr) SOC_READ_REG(I2S0_BASEADDR + addr) #define I2S0_WRITE_REG(addr,value) SOC_WRITE_REG(I2S0_BASEADDR + addr,value) #define I2S1_READ_REG(addr) SOC_READ_REG(I2S1_BASEADDR + addr) #define I2S1_WRITE_REG(addr,value) SOC_WRITE_REG(I2S1_BASEADDR + addr,value) #define I2S2_READ_REG(addr) SOC_READ_REG(I2S2_BASEADDR + addr) #define I2S2_WRITE_REG(addr,value) SOC_WRITE_REG(I2S2_BASEADDR + addr,value) #define I2S3_READ_REG(addr) SOC_READ_REG(I2S3_BASEADDR + addr) #define I2S3_WRITE_REG(addr,value) SOC_WRITE_REG(I2S3_BASEADDR + addr,value) #define I2S4_READ_REG(addr) SOC_READ_REG(I2S4_BASEADDR + addr) #define I2S4_WRITE_REG(addr,value) SOC_WRITE_REG(I2S4_BASEADDR + addr,value)