//-----------------------------------
#define CFG_MPTX_CFG0_ADDR 0x0000
#define MPTX_DONE_OFFSET 31
#define MPTX_DONE_MASK 0x80000000
#define MPTX_MST0_DONE_OFFSET 30
#define MPTX_MST0_DONE_MASK 0x40000000
#define MPTX_MST1_DONE_OFFSET 29
#define MPTX_MST1_DONE_MASK 0x20000000
#define MPTX_MST2_DONE_OFFSET 28
#define MPTX_MST2_DONE_MASK 0x10000000
#define MPTX_DEBUG_MODE_OFFSET 14
#define MPTX_DEBUG_MODE_MASK 0x00004000
#define MPTX_K3D_DIV_MODE_OFFSET 13
#define MPTX_K3D_DIV_MODE_MASK 0x00002000
#define MPTX_AUTO_MODE_OFFSET 12
#define MPTX_AUTO_MODE_MASK 0x00001000
#define MPTX_RAW_CRYPT_MODE_OFFSET 11
#define MPTX_RAW_CRYPT_MODE_MASK 0x00000800
#define MPTX_AFIFO_WDATA_INV_OFFSET 10
#define MPTX_AFIFO_WDATA_INV_MASK 0x00000400
#define MPTX_FORCE_STOP_MODE_OFFSET 9
#define MPTX_FORCE_STOP_MODE_MASK 0x00000200
#define MPTX_DATA_MODE_OFFSET 6
#define MPTX_DATA_MODE_MASK 0x000001C0
#define MPTX_WORK_MODE_OFFSET 4
#define MPTX_WORK_MODE_MASK 0x00000030
#define MPTX_MST_ENA_OFFSET 0
#define MPTX_MST_ENA_MASK 0x00000001

//-----------------------------------
#define CFG_MPTX_BUF0_CFG_ADDR 0x0004
#define MPTX_BUF0_SIZE_OFFSET 0
#define MPTX_BUF0_SIZE_MASK 0x001FFFFF

//-----------------------------------
#define CFG_MPTX_BUF1_CFG_ADDR 0x0008
#define MPTX_BUF1_SIZE_OFFSET 0
#define MPTX_BUF1_SIZE_MASK 0x001FFFFF

//-----------------------------------
#define CFG_MPTX_BUF2_CFG_ADDR 0x000c
#define MPTX_BUF2_SIZE_OFFSET 0
#define MPTX_BUF2_SIZE_MASK 0x001FFFFF

//-----------------------------------
#define CFG_MPTX_BUF0_ADDR_ADDR 0x0010
#define MPTX_BUF0_PTR_OFFSET 0
#define MPTX_BUF0_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_BUF1_ADDR_ADDR 0x0014
#define MPTX_BUF1_PTR_OFFSET 0
#define MPTX_BUF1_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_BUF2_ADDR_ADDR 0x0018
#define MPTX_BUF2_PTR_OFFSET 0
#define MPTX_BUF2_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_BURST_CFG_ADDR 0x001c
#define MPTX_BURST_LEN_OFFSET 0
#define MPTX_BURST_LEN_MASK 0x000001FF

//-----------------------------------
#define CFG_MPTX_FIFO0_CFG_ADDR 0x0020
#define MPTX_FIFO0_AF_NUM_OFFSET 0
#define MPTX_FIFO0_AF_NUM_MASK 0x000001FF

//-----------------------------------
#define CFG_MPTX_FIFO1_CFG_ADDR 0x0024
#define MPTX_FIFO1_AF_NUM_OFFSET 0
#define MPTX_FIFO1_AF_NUM_MASK 0x000001FF

//-----------------------------------
#define CFG_MPTX_FIFO2_CFG_ADDR 0x0028
#define MPTX_FIFO2_AF_NUM_OFFSET 0
#define MPTX_FIFO2_AF_NUM_MASK 0x000001FF

//-----------------------------------
#define CFG_MPTX_RAW_BUF_AF_ADDR 0x002C
#define MPTX_RAW_BUF_AF_NUM_OFFSET 0
#define MPTX_RAW_BUF_AF_NUM_MASK 0x00007FFF

//-----------------------------------
#define CFG_MPTX_STS_ADDR 0x0030
#define MPTX_MST_BUF_RST_OFFSET 7
#define MPTX_MST_BUF_RST_MASK 0x00000080
#define MPTX_MST2_BUF_PTR_OFFSET 6
#define MPTX_MST2_BUF_PTR_MASK 0x00000040
#define MPTX_MST1_BUF_PTR_OFFSET 5
#define MPTX_MST1_BUF_PTR_MASK 0x00000020
#define MPTX_MST0_BUF_PTR_OFFSET 4
#define MPTX_MST0_BUF_PTR_MASK 0x00000010
#define MPTX_FIFO2_UNDF_OFFSET 2
#define MPTX_FIFO2_UNDF_MASK 0x00000004
#define MPTX_FIFO1_UNDF_OFFSET 1
#define MPTX_FIFO1_UNDF_MASK 0x00000002
#define MPTX_FIFO0_UNDF_OFFSET 0
#define MPTX_FIFO0_UNDF_MASK 0x00000001

//-----------------------------------
#define CFG_MPTX_BUF3_ADDR_ADDR 0x0034
#define MPTX_BUF3_PTR_OFFSET 0
#define MPTX_BUF3_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_BUF4_ADDR_ADDR 0x0038
#define MPTX_BUF4_PTR_OFFSET 0
#define MPTX_BUF4_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_BUF5_ADDR_ADDR 0x003c
#define MPTX_BUF5_PTR_OFFSET 0
#define MPTX_BUF5_PTR_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_K3D_DIV_CFG_ADDR 0x0040
#define MPTX_K3D_DIV_B_OFFSET 16
#define MPTX_K3D_DIV_B_MASK 0xFFFF0000
#define MPTX_K3D_DIV_A_OFFSET 0
#define MPTX_K3D_DIV_A_MASK 0x0000FFFF

//-----------------------------------
#define CFG_MPTX_DBG_D0_ADDR 0x0044
#define MPTX_DEBUG_DATA0_OFFSET 0
#define MPTX_DEBUG_DATA0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_DBG_D1_ADDR 0x0048
#define MPTX_DEBUG_DATA1_OFFSET 0
#define MPTX_DEBUG_DATA1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_DBG_D2_ADDR 0x004c
#define MPTX_DEBUG_DATA2_OFFSET 0
#define MPTX_DEBUG_DATA2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_MPTX_DBG_D3_ADDR 0x0050
#define MPTX_DEBUG_DATA3_OFFSET 0
#define MPTX_DEBUG_DATA3_MASK 0xFFFFFFFF

//HW module read/write macro
#define MPTX_GLB_READ_REG(addr) SOC_READ_REG(MPTX_GLB_BASEADDR + addr)
#define MPTX_GLB_WRITE_REG(addr,value) SOC_WRITE_REG(MPTX_GLB_BASEADDR + addr,value)