//-----------------------------------
#define CFG_CMM_CMM_MATRIX_A_CFG0_ADDR 0x00
#define CMM_MATRIX_A_IS_DIAGONAL_OFFSET 31
#define CMM_MATRIX_A_IS_DIAGONAL_MASK 0x80000000
#define CMM_MATRIX_A_IS_REAL_OFFSET 15
#define CMM_MATRIX_A_IS_REAL_MASK 0x00008000
#define CMM_MATRIX_A_COL_SIZE_OFFSET 8
#define CMM_MATRIX_A_COL_SIZE_MASK 0x00007F00
#define CMM_MATRIX_A_ROW_SIZE_OFFSET 0
#define CMM_MATRIX_A_ROW_SIZE_MASK 0x0000007F

//-----------------------------------
#define CFG_CMM_CMM_MATRIX_A_CFG1_ADDR 0x04
#define CMM_MATRIX_A_START_ADDRESS_OFFSET 0
#define CMM_MATRIX_A_START_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CMM_CMM_MATRIX_A_CFG2_ADDR 0x08
#define CMM_MATRIX_A_SIZE_OFFSET 0
#define CMM_MATRIX_A_SIZE_MASK 0x000003FF

//-----------------------------------
#define CFG_CMM_CMM_MATRIX_B_CFG0_ADDR 0x0C
#define CMM_MATRIX_B_IS_DIAGONAL_OFFSET 31
#define CMM_MATRIX_B_IS_DIAGONAL_MASK 0x80000000
#define CMM_MATRIX_B_IS_REAL_OFFSET 15
#define CMM_MATRIX_B_IS_REAL_MASK 0x00008000
#define CMM_MATRIX_B_COL_SIZE_OFFSET 8
#define CMM_MATRIX_B_COL_SIZE_MASK 0x00007F00
#define CMM_MATRIX_B_ROW_SIZE_OFFSET 0
#define CMM_MATRIX_B_ROW_SIZE_MASK 0x0000007F

//-----------------------------------
#define CFG_CMM_CMM_MATRIX_B_CFG1_ADDR 0x10
#define CMM_MATRIX_B_START_ADDRESS_OFFSET 0
#define CMM_MATRIX_B_START_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CMM_CMM_MATRIX_B_CFG2_ADDR 0x14
#define CMM_MATRIX_B_SIZE_OFFSET 0
#define CMM_MATRIX_B_SIZE_MASK 0x000003FF

//-----------------------------------
#define CFG_CMM_CMM_CFG0_ADDR 0x18
#define CMM_FORCE_ON_OFFSET 31
#define CMM_FORCE_ON_MASK 0x80000000
#define CMM_NUM_MULTIPLICATION_OFFSET 16
#define CMM_NUM_MULTIPLICATION_MASK 0x7FFF0000
#define CMM_FP_RND_OFFSET 0
#define CMM_FP_RND_MASK 0x00000007

//-----------------------------------
#define CFG_CMM_CMM_CFG1_ADDR 0x1C
#define CMM_NUM_OPERATOR_OFFSET 14
#define CMM_NUM_OPERATOR_MASK 0x00004000
#define CMM_OP3_CTRL_OFFSET 10
#define CMM_OP3_CTRL_MASK 0x00003C00
#define CMM_OP2_CTRL_OFFSET 6
#define CMM_OP2_CTRL_MASK 0x000003C0
#define CMM_OP1_CTRL_OFFSET 3
#define CMM_OP1_CTRL_MASK 0x00000038
#define CMM_OP0_CTRL_OFFSET 0
#define CMM_OP0_CTRL_MASK 0x00000007

//-----------------------------------
#define CFG_CMM_CMM_CFG2_ADDR 0x20
#define CMM_RESULT_START_ADDRESS_OFFSET 0
#define CMM_RESULT_START_ADDRESS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_CMM_CMM_STATUS_ADDR 0x24
#define CMM_COMPLETE_COUNT_OFFSET 16
#define CMM_COMPLETE_COUNT_MASK 0x7FFF0000
#define CMM_COMPLETE_OFFSET 0
#define CMM_COMPLETE_MASK 0x00000001

//-----------------------------------
#define CFG_CMM_CMM_START_ADDR 0x28
#define CMM_CMM_START_TRIGGER_OFFSET 0
#define CMM_CMM_START_TRIGGER_MASK 0x00000001

//-----------------------------------
#define CFG_CMM_CMM_INT_CLR_ADDR 0x2C
#define CMM_CMM_INT_CLR_OFFSET 0
#define CMM_CMM_INT_CLR_MASK 0x00000001

//HW module read/write macro
#define RGF_CMM0_READ_REG(addr) SOC_READ_REG(RGF_CMM0_BASEADDR + addr)
#define RGF_CMM0_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_CMM0_BASEADDR + addr,value)
#define RGF_CMM1_READ_REG(addr) SOC_READ_REG(RGF_CMM1_BASEADDR + addr)
#define RGF_CMM1_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_CMM1_BASEADDR + addr,value)