//----------------------------------- #define WPHY_CODEC_CLK_CFG_ADDR 0x0000 #define CODEC_RX_CLK_ON_OFFSET 1 #define CODEC_RX_CLK_ON_MASK 0x00000002 #define CODEC_TX_CLK_ON_OFFSET 0 #define CODEC_TX_CLK_ON_MASK 0x00000001 //----------------------------------- #define WPHY_CODEC_SRST_CFG_ADDR 0x0004 #define CODEC_RX_SRST_L_OFFSET 1 #define CODEC_RX_SRST_L_MASK 0x00000002 #define CODEC_TX_SRST_L_OFFSET 0 #define CODEC_TX_SRST_L_MASK 0x00000001 //----------------------------------- #define WPHY_AHB_IF_CFG_ADDR 0x000C #define RX_FIFO_CLR_OFFSET 17 #define RX_FIFO_CLR_MASK 0x000020000 #define TX_FIFO_CLR_OFFSET 16 #define TX_FIFO_CLR_MASK 0x000010000 #define RX_BRDY_THD_OFFSET 8 #define RX_BRDY_THD_MASK 0x0000FF00 #define TX_BRDY_THD_OFFSET 0 #define TX_BRDY_THD_MASK 0x000000FF //----------------------------------- #define WPHY_CRC32_EN_ADDR 0x0018 #define CRC32_EN_OFFSET 0 #define CRC32_EN_MASK 0x00000001 //----------------------------------- #define WPHY_PHR_TX_INFO0_ADDR 0x0100 #define PHR_TX_INFO_0_OFFSET 0 #define PHR_TX_INFO_0_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_TX_INFO1_ADDR 0x0104 #define PHR_TX_INFO_1_OFFSET 0 #define PHR_TX_INFO_1_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_TX_INFO2_ADDR 0x0108 #define PHR_TX_INFO_2_OFFSET 0 #define PHR_TX_INFO_2_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_TX_INFO3_ADDR 0x010c #define PHR_TX_INFO_3_OFFSET 0 #define PHR_TX_INFO_3_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_RX_INFO0_ADDR 0x0110 #define PHR_RX_INFO_0_OFFSET 0 #define PHR_RX_INFO_0_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_RX_INFO1_ADDR 0x0114 #define PHR_RX_INFO_1_OFFSET 0 #define PHR_RX_INFO_1_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_RX_INFO2_ADDR 0x0118 #define PHR_RX_INFO_2_OFFSET 0 #define PHR_RX_INFO_2_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_RX_INFO3_ADDR 0x011c #define PHR_RX_INFO_3_OFFSET 0 #define PHR_RX_INFO_3_MASK 0xFFFFFFFF //----------------------------------- #define WPHY_PHR_BASIC_CFG_ADDR 0x0120 #define PHR_FEC_NCOPY_OFFSET 12 #define PHR_FEC_NCOPY_MASK 0x0000F000 #define PHR_FEC_MODT_OFFSET 8 #define PHR_FEC_MODT_MASK 0x00000F00 #define PHR_FEC_RATE_OFFSET 4 #define PHR_FEC_RATE_MASK 0x00000030 #define PHR_FEC_BLKZ_OFFSET 0 #define PHR_FEC_BLKZ_MASK 0x00000003 //----------------------------------- #define WPHY_PHR_CHAN_INTL_ADDR 0x0124 #define PHR_CHAN_OFFSET_OFFSET 12 #define PHR_CHAN_OFFSET_MASK 0x003FF000 #define PHR_CHAN_STEP_SIZE_OFFSET 4 #define PHR_CHAN_STEP_SIZE_MASK 0x000001F0 #define PHR_CHAN_INTL_MODE_OFFSET 0 #define PHR_CHAN_INTL_MODE_MASK 0x00000007 //----------------------------------- #define WPHY_PHR_ROBO_INTL0_ADDR 0x0128 #define PHR_GROUP_SHIFT_MODE_OFFSET 24 #define PHR_GROUP_SHIFT_MODE_MASK 0x03000000 #define PHR_GROUP_NUM_PER_COPY_OFFSET 12 #define PHR_GROUP_NUM_PER_COPY_MASK 0x00FFF000 #define PHR_SC_NUM_PER_SYMB_OFFSET 0 #define PHR_SC_NUM_PER_SYMB_MASK 0x000001FF //----------------------------------- #define WPHY_PHR_ROBO_INTL1_ADDR 0x012C #define PHR_BIT_NUM_IN_PAD_OFFSET 16 #define PHR_BIT_NUM_IN_PAD_MASK 0x0FFF0000 #define PHR_BIT_NUM_PER_GROUP_OFFSET 0 #define PHR_BIT_NUM_PER_GROUP_MASK 0x00000FFF //----------------------------------- #define WPHY_PHR_ROBO_INTL2_ADDR 0x0130 #define PHR_INTER_SHIFT_STEP_OFFSET 24 #define PHR_INTER_SHIFT_STEP_MASK 0x0F000000 #define PHR_SC_NUM_PER_INTER_OFFSET 16 #define PHR_SC_NUM_PER_INTER_MASK 0x00FF0000 #define PHR_INTER_NUM_PER_GROUP_OFFSET 8 #define PHR_INTER_NUM_PER_GROUP_MASK 0x00000F00 #define PHR_INTER_NUM_PER_SYMB_OFFSET 0 #define PHR_INTER_NUM_PER_SYMB_MASK 0x000000FF //----------------------------------- #define WPHY_PLD_BASIC_CFG_ADDR 0x0200 #define PLD_FEC_NCOPY_OFFSET 12 #define PLD_FEC_NCOPY_MASK 0x0000F000 #define PLD_FEC_MODT_OFFSET 8 #define PLD_FEC_MODT_MASK 0x00000F00 #define PLD_FEC_RATE_OFFSET 4 #define PLD_FEC_RATE_MASK 0x00000030 #define PLD_FEC_BLKZ_OFFSET 0 #define PLD_FEC_BLKZ_MASK 0x00000007 //----------------------------------- #define WPHY_PLD_CHAN_INTL_ADDR 0x0204 #define PLD_CHAN_OFFSET_OFFSET 12 #define PLD_CHAN_OFFSET_MASK 0x003FF000 #define PLD_CHAN_STEP_SIZE_OFFSET 4 #define PLD_CHAN_STEP_SIZE_MASK 0x000001F0 #define PLD_CHAN_INTL_MODE_OFFSET 0 #define PLD_CHAN_INTL_MODE_MASK 0x00000001 //----------------------------------- #define WPHY_PLD_ROBO_INTL0_ADDR 0x0208 #define PLD_GROUP_SHIFT_MODE_OFFSET 24 #define PLD_GROUP_SHIFT_MODE_MASK 0x03000000 #define PLD_GROUP_NUM_PER_COPY_OFFSET 12 #define PLD_GROUP_NUM_PER_COPY_MASK 0x00FFF000 #define PLD_SC_NUM_PER_SYMB_OFFSET 0 #define PLD_SC_NUM_PER_SYMB_MASK 0x000001FF //----------------------------------- #define WPHY_PLD_ROBO_INTL1_ADDR 0x020C #define PLD_BIT_NUM_IN_PAD_OFFSET 16 #define PLD_BIT_NUM_IN_PAD_MASK 0x0FFF0000 #define PLD_BIT_NUM_PER_GROUP_OFFSET 0 #define PLD_BIT_NUM_PER_GROUP_MASK 0x00000FFF //----------------------------------- #define WPHY_PLD_ROBO_INTL2_ADDR 0x0210 #define PLD_INTER_SHIFT_STEP_OFFSET 24 #define PLD_INTER_SHIFT_STEP_MASK 0x0F000000 #define PLD_SC_NUM_PER_INTER_OFFSET 16 #define PLD_SC_NUM_PER_INTER_MASK 0x00FF0000 #define PLD_INTER_NUM_PER_GROUP_OFFSET 8 #define PLD_INTER_NUM_PER_GROUP_MASK 0x00000F00 #define PLD_INTER_NUM_PER_SYMB_OFFSET 0 #define PLD_INTER_NUM_PER_SYMB_MASK 0x000000FF //----------------------------------- #define WPHY_PLD_PB_NUM_ADDR 0x0214 #define PLD_PB_NUM_OFFSET 0 #define PLD_PB_NUM_MASK 0x0000000F //----------------------------------- #define WPHY_DEC_CTRL_ADDR 0x0300 #define DEC_STOP_OFFSET 1 #define DEC_STOP_MASK 0x00000002 #define DEC_CONT_OFFSET 0 #define DEC_CONT_MASK 0x00000001 //----------------------------------- #define WPHY_DEC_CRC_RDY_ADDR 0x0304 #define PLD_CRC32_ERR_OFFSET 20 #define PLD_CRC32_ERR_MASK 0xFFF00000 #define PLD_CRC24_ERR_OFFSET 8 #define PLD_CRC24_ERR_MASK 0x000FFF00 #define PLD_RDY_OFFSET 4 #define PLD_RDY_MASK 0x00000010 #define PHR_CRC24_ERR_OFFSET 1 #define PHR_CRC24_ERR_MASK 0x00000002 #define PHR_RDY_OFFSET 0 #define PHR_RDY_MASK 0x00000001 //----------------------------------- #define WPHY_MODEM_CLK_CFG_ADDR 0x1000 #define MODEM_RX_CLK_ON_OFFSET 1 #define MODEM_RX_CLK_ON_MASK 0x00000002 #define MODEM_TX_CLK_ON_OFFSET 0 #define MODEM_TX_CLK_ON_MASK 0x00000001 //----------------------------------- #define WPHY_MODEM_SRST_CFG_ADDR 0x1004 #define MODEM_RX_SRST_L_OFFSET 1 #define MODEM_RX_SRST_L_MASK 0x00000002 #define MODEM_TX_SRST_L_OFFSET 0 #define MODEM_TX_SRST_L_MASK 0x00000001 //----------------------------------- #define WPHY_MLTX_CTRL_ADDR 0x1100 #define SOTX_TTMR_CLR_OFFSET 9 #define SOTX_TTMR_CLR_MASK 0x00000200 #define AOTX_TTMR_CLR_OFFSET 8 #define AOTX_TTMR_CLR_MASK 0x00000100 #define SOTX_TTMR_EN_OFFSET 5 #define SOTX_TTMR_EN_MASK 0x00000020 #define AOTX_TTMR_EN_OFFSET 4 #define AOTX_TTMR_EN_MASK 0x00000010 #define SOTX_IMMD_OFFSET 1 #define SOTX_IMMD_MASK 0x00000002 #define AOTX_IMMD_OFFSET 0 #define AOTX_IMMD_MASK 0x00000001 //----------------------------------- #define WPHY_MLTX_STAT_ADDR 0x1108 #define ATX_BUSY_OFFSET 4 #define ATX_BUSY_MASK 0x00000010 //----------------------------------- #define WPHY_MLTX_SIG_INFO_ADDR 0x1114 #define TX_SIG_INFO_OFFSET 0 #define TX_SIG_INFO_MASK 0x00000007 //----------------------------------- #define WPHY_MLTX_PHR_CFG_ADDR 0x1118 #define TX_PHR_SYMB_NUM_OFFSET 12 #define TX_PHR_SYMB_NUM_MASK 0x000FF000 #define TX_PHR_BL_NUM_OFFSET 8 #define TX_PHR_BL_NUM_MASK 0x00000700 #define TX_PHR_SC_NUM_DATA_USED_OFFSET 0 #define TX_PHR_SC_NUM_DATA_USED_MASK 0x000000FF //----------------------------------- #define WPHY_MLTX_PLD_CFG_ADDR 0x111C #define TX_PLD_SYMB_NUM_OFFSET 12 #define TX_PLD_SYMB_NUM_MASK 0x0FFFF000 #define TX_PLD_BL_NUM_OFFSET 8 #define TX_PLD_BL_NUM_MASK 0x00000700 #define TX_PLD_SC_NUM_DATA_USED_OFFSET 0 #define TX_PLD_SC_NUM_DATA_USED_MASK 0x000000FF //----------------------------------- #define WPHY_MLRX_CTRL_ADDR 0x1200 #define EOCS_TTMR_CLR_OFFSET 10 #define EOCS_TTMR_CLR_MASK 0x00000400 #define SOCS_TTMR_CLR_OFFSET 9 #define SOCS_TTMR_CLR_MASK 0x00000200 #define AOCS_TTMR_CLR_OFFSET 8 #define AOCS_TTMR_CLR_MASK 0x00000100 #define EOCS_TTMR_EN_OFFSET 6 #define EOCS_TTMR_EN_MASK 0x00000040 #define SOCS_TTMR_EN_OFFSET 5 #define SOCS_TTMR_EN_MASK 0x00000020 #define AOCS_TTMR_EN_OFFSET 4 #define AOCS_TTMR_EN_MASK 0x00000010 #define EOCS_IMMD_OFFSET 2 #define EOCS_IMMD_MASK 0x00000004 #define SOCS_IMMD_OFFSET 1 #define SOCS_IMMD_MASK 0x00000002 #define AOCS_IMMD_OFFSET 0 #define AOCS_IMMD_MASK 0x00000001 //----------------------------------- #define WPHY_MLRX_STATE_CTRL_ADDR 0x1208 #define RX_STATE_STOP_OFFSET 1 #define RX_STATE_STOP_MASK 0x00000002 #define RX_STATE_CONT_OFFSET 0 #define RX_STATE_CONT_MASK 0x00000001 //----------------------------------- #define WPHY_MLRX_STAT_ADDR 0x120C #define ARX_BUSY_OFFSET 16 #define ARX_BUSY_MASK 0x00010000 //----------------------------------- #define WPHY_MLRX_SIG_INFO_ADDR 0x121C #define RX_SIG_INFO_OFFSET 4 #define RX_SIG_INFO_MASK 0x00000070 #define RX_SIG_ERR_OFFSET 1 #define RX_SIG_ERR_MASK 0x00000002 #define RX_SIG_RDY_OFFSET 0 #define RX_SIG_RDY_MASK 0x00000001 //----------------------------------- #define WPHY_MLRX_PHR_CFG_ADDR 0x1220 #define RX_PHR_SYMB_NUM_OFFSET 12 #define RX_PHR_SYMB_NUM_MASK 0x000FF000 #define RX_PHR_BL_NUM_OFFSET 8 #define RX_PHR_BL_NUM_MASK 0x00000700 #define RX_PHR_SC_NUM_DATA_USED_OFFSET 0 #define RX_PHR_SC_NUM_DATA_USED_MASK 0x000000FF //----------------------------------- #define WPHY_MLRX_PLD_CFG_ADDR 0x1224 #define RX_PLD_SYMB_NUM_OFFSET 12 #define RX_PLD_SYMB_NUM_MASK 0x0FFFF000 #define RX_PLD_BL_NUM_OFFSET 8 #define RX_PLD_BL_NUM_MASK 0x00000700 #define RX_PLD_SC_NUM_DATA_USED_OFFSET 0 #define RX_PLD_SC_NUM_DATA_USED_MASK 0x000000FF //HW module read/write macro #define WPHY_READ_REG(addr) SOC_READ_REG(RF_PHY_CFG_BASEADDR + addr) #define WPHY_WRITE_REG(addr,value) SOC_WRITE_REG(RF_PHY_CFG_BASEADDR + addr,value) #define WPHY_INIT_READ_REG(addr) SOC_READ_REG(RF_MAC_BASEADDR + addr) #define WPHY_INIT_WRITE_REG(addr,value) SOC_WRITE_REG(RF_MAC_BASEADDR + addr,value) #define WPHY_WRITE_MEM_SCIDX(idx,value) \ SOC_WRITE_REG((RF_PHY_CSIDX_BASEADDR+(idx<<2)), value) #define WPHY_WRITE_MEM_SCPHASE(idx,value) \ SOC_WRITE_REG((RF_PHY_CSPHASE_BASEADDR+(idx<<2)), value)