/****************************************************************************
 *
 * Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
 *
 * This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
 * be copied by any method or incorporated into another program without
 * the express written consent of Aerospace C.Power. This Information or any portion
 * thereof remains the property of Aerospace C.Power. The Information contained herein
 * is believed to be accurate and Aerospace C.Power assumes no responsibility or
 * liability for its use in any way and conveys no license or title under
 * any patent or copyright and makes no representation or warranty that this
 * Information is free from patent or copyright infringement.
 *
 * ****************************************************************************/
/* os shim includes */
#include "os_types.h"
#include "iot_irq.h"
#include "iot_wdg.h"
#include "efuse.h"
#include "iot_system.h"
#include "sec_glb.h"

#include "platform.h"
#include "encoding.h"

extern void def_trap_entry_1();
extern void intc_handler(uint32_t cpu);
extern void trigger_zero_addr_access_detect();

extern void ahb_core0_enable();


uintptr_t handle_trap_1(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
{
    if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
        intc_handler(HAL_INTR_CPU_1);
    }else {
    }

    return epc;
}

void _init_1()
{
    //disable cpu1 branch prediction
    sec_glb_core1_branch_pred_enable(0);

    //disable cpu0, cpu2 instruction master access to dmc cache slave
    sec_glb_mtx_mst_acc(19, 14, 0);
    sec_glb_mtx_mst_acc(19, 16, 0);

    sec_glb_mtx_mst_acc(20, 14, 0);
    sec_glb_mtx_mst_acc(20, 16, 0);

    write_csr(mtvec, &def_trap_entry_1);

    clear_csr(mie, MIP_MEIP);
    clear_csr(mie, MIP_MTIP);

    iot_interrupt_init(HAL_INTR_CPU_1);

    set_csr(mie, MIP_MEIP);

    // Enable interrupts in general.
    set_csr(mstatus, MSTATUS_MIE);

    wdg_deinit(HAL_WDG_CPU_0);
    //wdg_deinit(HAL_WDG_CPU_1);
    wdg_deinit(HAL_WDG_CPU_2);
    wdg_deinit(HAL_WDG_CPU_3);
    wdg_deinit(HAL_WDG_CPU_4);
}

void _fini()
{

}