/****************************************************************************

Copyright(c) 2024 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.

This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.

****************************************************************************/

#include "os_types.h"
#include "os_mem_api.h"
#include "iot_irq.h"
#include "hw_reg_api.h"
#include "cpu.h"
#include "sec_cpu_phy_isr.h"
#include "phy_reg.h"
#include "plc_mpdu_header.h"
#include "iot_crypto_share.h"
#include "sec_cpu_utils.h"
#include "mac_sys_reg.h"
#include "phy_bb.h"
#include "phy_isr.h"
#include "phy_phase.h"

phy_cpu_share_ctxt_t g_phy_cpu_share_ctxt;
static iot_irq_t phy_irq_int_0;

void sec_cpu_get_rx_frm_msg_from_fc(void *fc, rx_fc_msg_t *msg)
{
    /* used for spg */
    spg_frame_control_t *spg_fc = (spg_frame_control_t *)fc;
    uint8_t delimiter = spg_fc->delimiter_type;

    msg->delimiter = delimiter;
    if (delimiter == FC_DELIM_BEACON) {
        msg->tmi = spg_fc->vf.bcn.tmi;
        msg->numsym = spg_fc->vf.bcn.sym_num;
    } else if (delimiter == FC_DELIM_SOF) {
        msg->tmi = spg_fc->vf.sof.tmi;
        msg->tmi_ext = spg_fc->vf.sof.tmi_ext;
        msg->pb_num = (uint8_t)spg_fc->vf.sof.pb_num;
        msg->numsym = spg_fc->vf.sof.sym_num;
    } else {

    }

    /* TODO used for sg */
    return;
}

uint32_t sec_cpu_get_phy_interrupt_type(void)
{
    return PHY_READ_REG(CFG_BB_INT_MASK_0_ADDR);
}

void sec_cpu_disable_phy_interrupt(uint32_t irq_type)
{
    uint32_t reg_int = PHY_READ_REG(CFG_BB_INT_EN_0_ADDR);

    reg_int &= (~irq_type);
    PHY_WRITE_REG(CFG_BB_INT_EN_0_ADDR, reg_int);
}

void sec_cpu_clear_phy_interrupt(uint32_t irq_type)
{
    PHY_WRITE_REG(CFG_BB_INT_CLR_0_ADDR, irq_type);
}

void sec_cpu_enable_phy_interrupt(uint32_t irq_type)
{
    uint32_t reg_int = PHY_READ_REG(CFG_BB_INT_EN_0_ADDR);

    reg_int |= irq_type;
    PHY_WRITE_REG(CFG_BB_INT_EN_0_ADDR, reg_int);
}

uint32_t sec_cpu_phy_isr_handler(uint32_t vector, iot_addrword_t data)
{
    (void)vector;
    (void)data;
    uint32_t isr_flag = sec_cpu_get_phy_interrupt_type();
#if MAC_SYM_NUM_FIX
    uint32_t bb_fc[4];
    rx_fc_msg_t msg;
#endif

    if (isr_flag & PHY_RECV_FD_CH_EST_DONE) {
#if MAC_SYM_NUM_FIX
        if (!g_phy_cpu_share_ctxt.sym_num_fix_dis) {
            uint32_t tmp = RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR);
            g_phy_cpu_share_ctxt.multiband = REG_FIELD_GET(PHY_RX_BANDSEL, tmp);
        }
#endif
    }

    if (isr_flag & PHY_RECV_FD_FC_OK) {
        g_phy_cpu_share_ctxt.reg_phase = phy_get_mac_rx_phase();
#if MAC_SYM_NUM_FIX
        if (!g_phy_cpu_share_ctxt.sym_num_fix_dis) {
            bb_fc[0] = PHY_READ_REG(CFG_BB_RX_FC_RAW_0_ADDR);
            bb_fc[1] = PHY_READ_REG(CFG_BB_RX_FC_RAW_1_ADDR);
            bb_fc[2] = PHY_READ_REG(CFG_BB_RX_FC_RAW_2_ADDR);
            bb_fc[3] = PHY_READ_REG(CFG_BB_RX_FC_RAW_3_ADDR);

            sec_cpu_get_rx_frm_msg_from_fc(bb_fc, &msg);

            if (((msg.delimiter == FC_DELIM_SOF) ||
                (msg.delimiter == FC_DELIM_BEACON))) {
                uint16_t total_sym_num, sym_num;
                uint16_t *p_symppb =
                    (uint16_t *)g_phy_cpu_share_ctxt.p_g_symppb;
                uint8_t tmi = msg.tmi;

                if (msg.delimiter == FC_DELIM_SOF) {
                    tmi += msg.tmi_ext;
                }
                sym_num = *(p_symppb + g_phy_cpu_share_ctxt.multiband *
                    SG_OFDM_MAX + tmi);
                if (sym_num != msg.numsym) {
                    if (msg.delimiter == FC_DELIM_SOF) {
                        total_sym_num = sym_num * msg.pb_num;
                    } else {
                        total_sym_num = sym_num;
                    }
                    uint32_t tmp =
                        PHY_READ_REG(CFG_BB_CONFIG_FC_PARSE_0_ADDR);
                    REG_FIELD_SET(SW_CONFIG_PB_SYMB_NUM, tmp, sym_num);
                    REG_FIELD_SET(SW_CONFIG_PLD_SYMB_NUM, tmp,
                        total_sym_num);
                    REG_FIELD_SET(SW_CONFIG_PB_SYMB_NUM_EN, tmp, 1);
                    REG_FIELD_SET(SW_CONFIG_PLD_SYMB_NUM_EN, tmp, 1);
                    PHY_WRITE_REG(CFG_BB_CONFIG_FC_PARSE_0_ADDR, tmp);
                }
            }
        }
#endif
    }

    if (isr_flag & PHY_RECV_FD_PLD_OK ||
        isr_flag & PHY_RECV_FD_PLD_FAIL) {
#if MAC_SYM_NUM_FIX
        uint32_t tmp = PHY_READ_REG(CFG_BB_CONFIG_FC_PARSE_0_ADDR);
        if (REG_FIELD_GET(SW_CONFIG_PB_SYMB_NUM_EN, tmp) ||
            REG_FIELD_GET(SW_CONFIG_PLD_SYMB_NUM_EN, tmp)) {
            REG_FIELD_SET(SW_CONFIG_PB_SYMB_NUM_EN, tmp, 0);
            REG_FIELD_SET(SW_CONFIG_PLD_SYMB_NUM_EN, tmp, 0);
            PHY_WRITE_REG(CFG_BB_CONFIG_FC_PARSE_0_ADDR, tmp);
        }
#endif
#if MAC_TIMESTAMPING
        /* PLD ok or fail interrupt */
        g_phy_cpu_share_ctxt.phy_pld_int_ntb =
            RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
#endif
    }

    sec_cpu_clear_phy_interrupt(isr_flag);

    return 0;
}

void sec_cpu_phy_isr_start(void)
{
    iot_interrupt_unmask(phy_irq_int_0);
}

void sec_cpu_phy_isr_stop(void)
{
    iot_interrupt_mask(phy_irq_int_0);
}

void sec_cpu_phy_isr_init(void)
{
    uint32_t cpu_id = cpu_get_mhartid();

    phy_irq_int_0 = iot_interrupt_create(HAL_VECTOR_PHY_0, HAL_INTR_PRI_6,
        0, sec_cpu_phy_isr_handler);

    iot_interrupt_set_cpu(phy_irq_int_0, cpu_id);

    iot_interrupt_attach(phy_irq_int_0);

    /* start intc */
    sec_cpu_phy_isr_start();
}