103 lines
3.6 KiB
C
103 lines
3.6 KiB
C
/****************************************************************************
|
|
|
|
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
|
|
|
|
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
|
|
be copied by any method or incorporated into another program without
|
|
the express written consent of Aerospace C.Power. This Information or any portion
|
|
thereof remains the property of Aerospace C.Power. The Information contained herein
|
|
is believed to be accurate and Aerospace C.Power assumes no responsibility or
|
|
liability for its use in any way and conveys no license or title under
|
|
any patent or copyright and makes no representation or warranty that this
|
|
Information is free from patent or copyright infringement.
|
|
|
|
****************************************************************************/
|
|
|
|
#ifndef _BB_CPU_CONFIG_H_
|
|
#define _BB_CPU_CONFIG_H_
|
|
|
|
/* os shim includes */
|
|
#include "os_types.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/* define rf chip version */
|
|
/* define the micro indicate version 1 available before 2022.8.15 */
|
|
#define RF_VER1_2022_8_15 1
|
|
|
|
/* define txrx use the way of DMA or not */
|
|
#define BB_CPU_TXRX_USE_DMA 0
|
|
|
|
/* define bbcpu debug print enable or not */
|
|
#define BB_CPU_DEBUG_PRINT 1
|
|
|
|
/* this define indecate hw ring enable for debug rx flow of bbcpu */
|
|
#define BB_CPU_HW_RING_ENABLE 1
|
|
|
|
/* rx exception notify plc cpu
|
|
* eg: BB_CPU_RX_RING_SIG_ERR, BB_CPU_RX_RING_PHR_ERR...
|
|
*/
|
|
#define BB_CPU_RX_EXCEPTION_NOTIFY_PLC_CPU 0
|
|
|
|
/* delay between txcfg step 1 and txcfg step 2, unit us */
|
|
#define BB_CPU_TXCFG1_TXCFG2_DELAY_US 105
|
|
|
|
/* option2 special mode delay between txcfg step 2 and aotx, unit us, 100us */
|
|
#define BB_CPU_AOTX_TXCFG_SPC_OP2_DELAY_US 95
|
|
|
|
/* option3 special mode delay between txcfg step 3 and aotx, unit us, 500us */
|
|
#define BB_CPU_AOTX_TXCFG_SPC_OP3_DELAY_US 495
|
|
|
|
/* option2 10db power delay between txcfg step 2 and aotx, unit us, 5us */
|
|
#define BB_CPU_AOTX_TXCFG_OP2_DELAY_US 0
|
|
|
|
/* option3 10db power delay between txcfg step 3 and aotx, unit us, 150us */
|
|
#define BB_CPU_AOTX_TXCFG_OP3_DELAY_US 145
|
|
|
|
/* time --------------------------------> **
|
|
* start_ntb--->notx--->aotx--->sotx
|
|
*/
|
|
/* define the time of notx timer(sw define), uint ntb.
|
|
* need immediately start.
|
|
*/
|
|
#define BB_CPU_NOTX_TIME 1
|
|
|
|
/* define the time of aotx timer, uint ntb.
|
|
* time reserved for sw config beacon timestamp. 4us*25.
|
|
*/
|
|
#define BB_CPU_AOTX_TIME 100
|
|
|
|
/* define the time of sotx timer, uint ntb.
|
|
* sotx time - aotx time > 50us.
|
|
* 50us*25 + BB_CPU_AOTX_TIME = 1350.
|
|
*/
|
|
#define BB_CPU_SOTX_TIME 1350
|
|
|
|
/* define the time of gap for sotx to singal start, uint ntb */
|
|
#define BB_CPU_TX_GOLDEN_GAP_OPT1 375
|
|
#define BB_CPU_TX_GOLDEN_GAP_OPT2 725
|
|
#define BB_CPU_TX_GOLDEN_GAP_OPT3 1400
|
|
|
|
/* define the time of gap for tx start */
|
|
#define bb_cpu_get_tx_golden_gap(opt) (BB_CPU_SOTX_TIME \
|
|
- BB_CPU_NOTX_TIME + (((opt) == 1) ? BB_CPU_TX_GOLDEN_GAP_OPT1 \
|
|
: (((opt) == 2) ? BB_CPU_TX_GOLDEN_GAP_OPT2 : BB_CPU_TX_GOLDEN_GAP_OPT3)))
|
|
|
|
|
|
/* define the time of gap for stf interrupt to signal start, uint ntb */
|
|
#define BB_CPU_RX_GOLDEN_GAP_OPT1 15950
|
|
#define BB_CPU_RX_GOLDEN_GAP_OPT2 16400
|
|
#define BB_CPU_RX_GOLDEN_GAP_OPT3 17250
|
|
/* define the time of gap for rx start, uint ntb */
|
|
#define BB_CPU_RX_GOLDEN_GAP(opt) (((opt) == 1) ? \
|
|
BB_CPU_RX_GOLDEN_GAP_OPT1 : (((opt) == 2) ? \
|
|
BB_CPU_RX_GOLDEN_GAP_OPT2 : BB_CPU_RX_GOLDEN_GAP_OPT3))
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // _BB_CPU_CONFIG_H_
|