255 lines
7.2 KiB
C
255 lines
7.2 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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#include "os_utils.h"
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#include "os_mem.h"
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#include "dbg_io.h"
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#include "iot_diag.h"
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#include "iot_io.h"
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#include "ddr_reg_rf.h"
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#include "dmc_reg_rf.h"
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#include "hw_reg_api.h"
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#include "ahb.h"
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#include "k3d_reg.h"
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#include "ai_glb_reg.h"
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#include "mac_sys_reg.h"
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#include "cpu.h"
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#include "ddrc.h"
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#include "flash.h"
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#include "pmu_hw.h"
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#include "ana.h"
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#include "clk.h"
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#include "efuse.h"
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#include "efuse_mapping.h"
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// ############################################################################
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// common define
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#define REG32(a) (*((volatile uint32_t *)(a)))
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#define EFUSE_MAC_TEST_ERR (1 << 0)
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#define DDR_MEM_TEST_ERR (1 << 1)
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#define FLASH_TEST_ERR (1 << 2)
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uint32_t err_id = 0;
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void efuse_mac_read()
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{
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uint32_t tmp;
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uint8_t mac[6] = {0};
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tmp = efuse_read(CFG_EFUSE_BITS32_2_ADDR);
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mac[0] = REG_FIELD_GET(MAC_ADDR_B0, tmp);
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tmp = efuse_read(CFG_EFUSE_BITS32_3_ADDR);
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mac[1] = REG_FIELD_GET(MAC_ADDR_B1, tmp);
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mac[2] = REG_FIELD_GET(MAC_ADDR_B2, tmp);
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mac[3] = REG_FIELD_GET(MAC_ADDR_B3, tmp);
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mac[4] = REG_FIELD_GET(MAC_ADDR_B4, tmp);
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tmp = efuse_read(CFG_EFUSE_BITS32_4_ADDR);
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mac[5] = REG_FIELD_GET(MAC_ADDR_B5, tmp);
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iot_printf("[MAC_ID_TEST]efuse read MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
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mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
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if (mac[0] != 0x48 || mac[1] != 0x55 || mac[2] != 0x5c) {
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err_id |= EFUSE_MAC_TEST_ERR;
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iot_printf("####MAC ID TEST FAILED.####\n");
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} else {
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iot_printf("####MAC ID TEST OK.####\n");
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}
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}
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#define DDR_MEM_START_ADDR (0)
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#define DDR_MEM_ICACHE_ADDR (0x18000000)
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#define DDR_MEM_DCACHE_ADDR (0x10000000)
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#define DDR_MEM_SIZE_32MB (8*1024*1024) // unit is word, total size: 32MB
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#define DDR_MEM_SIZE_8MB (2*1024*1024) // unit is word, total size: 8MB
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#define DDR_MEM_TEST_ADDR (DDR_MEM_ICACHE_ADDR + DDR_MEM_START_ADDR)
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void dump_dmc_reg()
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{
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volatile uint32_t *reg = (volatile uint32_t *) DDR_RF_BASEADDR;
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iot_printf("dump ddr reg(%p):\n", reg);
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for(uint32_t i = 0; i < 0x300/4; i++) {
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if ((i % 4) == 0) {
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iot_printf("\n%p: ", (reg+i+1));
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}
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iot_printf("0x%08x ", *(reg+i));
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}
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iot_printf("\n");
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reg = (volatile uint32_t *) DMC_RF_BASEADDR;
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iot_printf("dump dmc reg(%p):\n", reg);
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for(uint32_t i = 0; i < 0x300/4; i++) {
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if ((i % 4) == 0) {
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iot_printf("\n%p: ", (reg+i+1));
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}
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iot_printf("0x%08x ", *(reg+i));
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}
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iot_printf("\n");
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}
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void ddr_mem_dtest(uint32_t mode, uint32_t cnt)
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{
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iot_printf("\n-------DDR MEMORY TEST---------\n");
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volatile uint32_t *src = (volatile uint32_t *) DDR_MEM_TEST_ADDR;
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uint32_t test_size = 0;
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if (mode == DEV_X16_MODE) {
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test_size = DDR_MEM_SIZE_32MB;
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} else {
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test_size = DDR_MEM_SIZE_8MB;
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}
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/* write */
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for(uint32_t i = 0; i < test_size; i++) {
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*(src + i) = i;
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}
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/* read */
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uint8_t err = 0;
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uint32_t tmp;
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for(uint32_t i = 0; i < test_size; i++) {
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tmp = *(src + i);
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if (tmp != i) {
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iot_printf("read error....addr-0x%08x: 0x%08x-0x%08x\n",
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i*4, i, tmp);
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err_id |= DDR_MEM_TEST_ERR;
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err = 1;
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}
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}
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if (err == 1) {
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dump_dmc_reg();
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iot_printf("failed cnt: %d\n", cnt);
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iot_printf("####DDR MEMORY TEST FAILED.####\n");
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while(1);
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} else {
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iot_printf("####DDR MEMORY TEST OK.####\n");
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}
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}
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static uint8_t rdata[0x100] = {0};
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static uint8_t wdata[0x100] = {0};
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#define FLASH_TEST_OFFSET (0x0)
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#define FLASH_VENDOR_ID_GD 0xc8
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#define FLASH_VENDOR_ID_PUYA 0x85
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#define FLASH_VENDOR_ID_ZBIT 0x5e
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#define FLASH_VENDOR_ID_WINBOND 0xef
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void flash_test(uint32_t mode)
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{
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iot_printf("\n-------FLASH TEST---------\n");
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uint8_t flag = 0;
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if (mode == DEV_X8_MODE) {
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uint8_t data;
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g_sfc_ctrl->get_dev_id(&data);
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iot_printf("[FLASH_TEST]get id: %02x\n", data);
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if (data != FLASH_VENDOR_ID_GD && data != FLASH_VENDOR_ID_PUYA\
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&& data != FLASH_VENDOR_ID_ZBIT && data != FLASH_VENDOR_ID_WINBOND){
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iot_printf("[FLASH_TEST]id is not match.\n");
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flag = 1;
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goto err;
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}
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for(uint32_t i = 0; i < 0x100; i++) {
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wdata[i] = i;
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}
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g_sfc_ctrl->erase_sector(FLASH_TEST_OFFSET, MOD_SW_MODE_DIS);
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g_sfc_ctrl->write(wdata,FLASH_TEST_OFFSET, sizeof(wdata),
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MOD_SFC_PROG_STAND, MOD_SW_MODE_DIS);
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g_sfc_ctrl->read(rdata,FLASH_TEST_OFFSET,sizeof(wdata), MOD_SFC_READ_SIG);
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for(uint32_t i = 0; i < 0x100; i++) {
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if (wdata[i] != rdata[i]) {
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flag = 1;
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iot_printf("[FLASH_TEST]not match, index: %d, \
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write:%02x, read: %02x\n", wdata[i], rdata[i]);
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break;
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}
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}
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} else {
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flag = 2;
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}
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err:
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if (flag == 2) {
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iot_printf("####FLASH TEST TEST BYPASS.####\n");
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} else if (flag == 1) {
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err_id |= FLASH_TEST_ERR;
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iot_printf("####FLASH TEST TEST FAILED.####\n");
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} else {
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iot_printf("####FLASH TEST TEST OK.####\n");
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}
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}
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int main(void)
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{
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dbg_uart_init();
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iot_printf("\n-------EFUSE MAC TEST---------\n");
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efuse_mac_read();
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iot_printf("####EFUSE MAC TEST FINISHED.####\n");
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iot_printf("\n-------DDR TRAINING TEST---------\n");
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//disable auto-baud;
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REG32(0x44001020) &= ~0x1;
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//change CPU core to 150M.
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clk_core_freq_set(CPU_FREQ_150M);
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//flash init;
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flash_init(1);
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// disable cache
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ahb_cache_disable();
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ddr_cache_init();
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// enable ahb cache
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ahb_cache_enable();
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//ahb_cache_reset();
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//enable dmc cache;
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ahb_dmc_cache_enable();
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//cache space init;
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ahb_cache_fill_valid_space();
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iot_printf("####DDR TRAINING TEST FINISHED.####\n");
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uint32_t mode;
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uint32_t pkt_type = ahb_get_pkg_type();
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if (pkt_type == AHB_PKG_AI) {
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mode = DEV_X16_MODE;
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} else {
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mode = DEV_X8_MODE;
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}
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ddr_mem_dtest(mode, 0);
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flash_test(mode);
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iot_printf("\n[TEST]result: %08x\n", err_id);
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if (err_id) {
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iot_printf("[TEST]test failed.\n");
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} else {
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iot_printf("[TEST]test ok.\n");
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}
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iot_printf("\n****TEST FINISHED.****\n");
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return 0;
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}
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