327 lines
11 KiB
C
Executable File
327 lines
11 KiB
C
Executable File
|
|
//-----------------------------------
|
|
#define CFG_AI_GLB_CFG0_ADDR 0x0000
|
|
#define REF_PIC_CAPTURE_OFFSET 4
|
|
#define REF_PIC_CAPTURE_MASK 0x00000010
|
|
#define CNN_RAM_MTRANS_OFFSET 3
|
|
#define CNN_RAM_MTRANS_MASK 0x00000008
|
|
#define CNN_RAM_FEYE_OFFSET 2
|
|
#define CNN_RAM_FEYE_MASK 0x00000004
|
|
#define CNN_ENA_OFFSET 1
|
|
#define CNN_ENA_MASK 0x00000002
|
|
#define K3D_ENA_OFFSET 0
|
|
#define K3D_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RST_CFG0_ADDR 0x0004
|
|
#define CNN_SOFT_RST_OFFSET 1
|
|
#define CNN_SOFT_RST_MASK 0x00000002
|
|
#define K3D_SOFT_RST_OFFSET 0
|
|
#define K3D_SOFT_RST_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_MST_CFG0_ADDR 0x0008
|
|
#define AI_MST_BURST_LEN_OFFSET 8
|
|
#define AI_MST_BURST_LEN_MASK 0x00007F00
|
|
#define AI_MST_K3D_MODE_OFFSET 2
|
|
#define AI_MST_K3D_MODE_MASK 0x00000004
|
|
#define AI_MST_RW_OFFSET 1
|
|
#define AI_MST_RW_MASK 0x00000002
|
|
#define AI_MST_ENA_OFFSET 0
|
|
#define AI_MST_ENA_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_MST_CFG1_ADDR 0x000C
|
|
#define AI_MST_TRANS_LEN_OFFSET 0
|
|
#define AI_MST_TRANS_LEN_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_MST_CFG2_ADDR 0x0010
|
|
#define AI_K3D_16L_LEN_OFFSET 0
|
|
#define AI_K3D_16L_LEN_MASK 0x0001FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_SADDR_ADDR 0x0014
|
|
#define AI_MST_RAM_SADDR_OFFSET 0
|
|
#define AI_MST_RAM_SADDR_MASK 0x0001FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_EADDR_ADDR 0x0018
|
|
#define AI_MST_RAM_EADDR_OFFSET 0
|
|
#define AI_MST_RAM_EADDR_MASK 0x0001FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_DMC_SADDR0_ADDR 0x001c
|
|
#define AI_MST_DMC_SADDR0_OFFSET 0
|
|
#define AI_MST_DMC_SADDR0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_MST_ST_ADDR 0x0020
|
|
#define K3D_FRM_FORCE_DONE_OFFSET 22
|
|
#define K3D_FRM_FORCE_DONE_MASK 0x00400000
|
|
#define DMC_SADDR_SEL_SOFT_RST_OFFSET 21
|
|
#define DMC_SADDR_SEL_SOFT_RST_MASK 0x00200000
|
|
#define DMC_SADDR_SEL_OFFSET 20
|
|
#define DMC_SADDR_SEL_MASK 0x00100000
|
|
#define K3D_16LINE_FORCE_DONE_OFFSET 19
|
|
#define K3D_16LINE_FORCE_DONE_MASK 0x00080000
|
|
#define K3D_OUT_RAM_SOFT_RST_OFFSET 18
|
|
#define K3D_OUT_RAM_SOFT_RST_MASK 0x00040000
|
|
#define K3D_OUT_RAM_EMP_OFFSET 17
|
|
#define K3D_OUT_RAM_EMP_MASK 0x00020000
|
|
#define K3D_OUT_RAM_FULL_OFFSET 16
|
|
#define K3D_OUT_RAM_FULL_MASK 0x00010000
|
|
#define K3D_OUT_RAM_RPTR_OFFSET 14
|
|
#define K3D_OUT_RAM_RPTR_MASK 0x0000C000
|
|
#define K3D_OUT_RAM_WPTR_OFFSET 12
|
|
#define K3D_OUT_RAM_WPTR_MASK 0x00003000
|
|
#define DCAM_FRM_FORCE_DONE_OFFSET 11
|
|
#define DCAM_FRM_FORCE_DONE_MASK 0x00000800
|
|
#define DCAM_BIN_RAM_SOFT_RST_OFFSET 10
|
|
#define DCAM_BIN_RAM_SOFT_RST_MASK 0x00000400
|
|
#define DCAM_BIN_RAM_EMP_OFFSET 9
|
|
#define DCAM_BIN_RAM_EMP_MASK 0x00000200
|
|
#define DCAM_BIN_RAM_FULL_OFFSET 8
|
|
#define DCAM_BIN_RAM_FULL_MASK 0x00000100
|
|
#define DCAM_BIN_RAM_RPTR_OFFSET 6
|
|
#define DCAM_BIN_RAM_RPTR_MASK 0x000000C0
|
|
#define DCAM_BIN_RAM_WPTR_OFFSET 4
|
|
#define DCAM_BIN_RAM_WPTR_MASK 0x00000030
|
|
#define AI_MST_DONE_OFFSET 0
|
|
#define AI_MST_DONE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_MST_DBG_ADDR 0x0024
|
|
#define AI_MST_STS_OFFSET 0
|
|
#define AI_MST_STS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_DMC_SADDR1_ADDR 0x0028
|
|
#define AI_MST_DMC_SADDR1_OFFSET 0
|
|
#define AI_MST_DMC_SADDR1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_MEM_CLK_ADDR 0x002c
|
|
#define AI_MEM_CLK_CFG_OFFSET 0
|
|
#define AI_MEM_CLK_CFG_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG0_ADDR 0x0030
|
|
#define MUX_RAM3_TEST1_OFFSET 29
|
|
#define MUX_RAM3_TEST1_MASK 0x20000000
|
|
#define MUX_RAM3_RME_OFFSET 28
|
|
#define MUX_RAM3_RME_MASK 0x10000000
|
|
#define MUX_RAM3_RM_OFFSET 24
|
|
#define MUX_RAM3_RM_MASK 0x0F000000
|
|
#define MUX_RAM2_TEST1_OFFSET 21
|
|
#define MUX_RAM2_TEST1_MASK 0x00200000
|
|
#define MUX_RAM2_RME_OFFSET 20
|
|
#define MUX_RAM2_RME_MASK 0x00100000
|
|
#define MUX_RAM2_RM_OFFSET 16
|
|
#define MUX_RAM2_RM_MASK 0x000F0000
|
|
#define MUX_RAM1_TEST1_OFFSET 13
|
|
#define MUX_RAM1_TEST1_MASK 0x00002000
|
|
#define MUX_RAM1_RME_OFFSET 12
|
|
#define MUX_RAM1_RME_MASK 0x00001000
|
|
#define MUX_RAM1_RM_OFFSET 8
|
|
#define MUX_RAM1_RM_MASK 0x00000F00
|
|
#define MUX_RAM0_TEST1_OFFSET 5
|
|
#define MUX_RAM0_TEST1_MASK 0x00000020
|
|
#define MUX_RAM0_RME_OFFSET 4
|
|
#define MUX_RAM0_RME_MASK 0x00000010
|
|
#define MUX_RAM0_RM_OFFSET 0
|
|
#define MUX_RAM0_RM_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG1_ADDR 0x0034
|
|
#define MUX_RAM7_TEST1_OFFSET 29
|
|
#define MUX_RAM7_TEST1_MASK 0x20000000
|
|
#define MUX_RAM7_RME_OFFSET 28
|
|
#define MUX_RAM7_RME_MASK 0x10000000
|
|
#define MUX_RAM7_RM_OFFSET 24
|
|
#define MUX_RAM7_RM_MASK 0x0F000000
|
|
#define MUX_RAM6_TEST1_OFFSET 21
|
|
#define MUX_RAM6_TEST1_MASK 0x00200000
|
|
#define MUX_RAM6_RME_OFFSET 20
|
|
#define MUX_RAM6_RME_MASK 0x00100000
|
|
#define MUX_RAM6_RM_OFFSET 16
|
|
#define MUX_RAM6_RM_MASK 0x000F0000
|
|
#define MUX_RAM5_TEST1_OFFSET 13
|
|
#define MUX_RAM5_TEST1_MASK 0x00002000
|
|
#define MUX_RAM5_RME_OFFSET 12
|
|
#define MUX_RAM5_RME_MASK 0x00001000
|
|
#define MUX_RAM5_RM_OFFSET 8
|
|
#define MUX_RAM5_RM_MASK 0x00000F00
|
|
#define MUX_RAM4_TEST1_OFFSET 5
|
|
#define MUX_RAM4_TEST1_MASK 0x00000020
|
|
#define MUX_RAM4_RME_OFFSET 4
|
|
#define MUX_RAM4_RME_MASK 0x00000010
|
|
#define MUX_RAM4_RM_OFFSET 0
|
|
#define MUX_RAM4_RM_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG2_ADDR 0x0038
|
|
#define MUX_RAM11_TEST1_OFFSET 29
|
|
#define MUX_RAM11_TEST1_MASK 0x20000000
|
|
#define MUX_RAM11_RME_OFFSET 28
|
|
#define MUX_RAM11_RME_MASK 0x10000000
|
|
#define MUX_RAM11_RM_OFFSET 24
|
|
#define MUX_RAM11_RM_MASK 0x0F000000
|
|
#define MUX_RAM10_TEST1_OFFSET 21
|
|
#define MUX_RAM10_TEST1_MASK 0x00200000
|
|
#define MUX_RAM10_RME_OFFSET 20
|
|
#define MUX_RAM10_RME_MASK 0x00100000
|
|
#define MUX_RAM10_RM_OFFSET 16
|
|
#define MUX_RAM10_RM_MASK 0x000F0000
|
|
#define MUX_RAM9_TEST1_OFFSET 13
|
|
#define MUX_RAM9_TEST1_MASK 0x00002000
|
|
#define MUX_RAM9_RME_OFFSET 12
|
|
#define MUX_RAM9_RME_MASK 0x00001000
|
|
#define MUX_RAM9_RM_OFFSET 8
|
|
#define MUX_RAM9_RM_MASK 0x00000F00
|
|
#define MUX_RAM8_TEST1_OFFSET 5
|
|
#define MUX_RAM8_TEST1_MASK 0x00000020
|
|
#define MUX_RAM8_RME_OFFSET 4
|
|
#define MUX_RAM8_RME_MASK 0x00000010
|
|
#define MUX_RAM8_RM_OFFSET 0
|
|
#define MUX_RAM8_RM_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG3_ADDR 0x003c
|
|
#define MUX_RAM15_TEST1_OFFSET 29
|
|
#define MUX_RAM15_TEST1_MASK 0x20000000
|
|
#define MUX_RAM15_RME_OFFSET 28
|
|
#define MUX_RAM15_RME_MASK 0x10000000
|
|
#define MUX_RAM15_RM_OFFSET 24
|
|
#define MUX_RAM15_RM_MASK 0x0F000000
|
|
#define MUX_RAM14_TEST1_OFFSET 21
|
|
#define MUX_RAM14_TEST1_MASK 0x00200000
|
|
#define MUX_RAM14_RME_OFFSET 20
|
|
#define MUX_RAM14_RME_MASK 0x00100000
|
|
#define MUX_RAM14_RM_OFFSET 16
|
|
#define MUX_RAM14_RM_MASK 0x000F0000
|
|
#define MUX_RAM13_TEST1_OFFSET 13
|
|
#define MUX_RAM13_TEST1_MASK 0x00002000
|
|
#define MUX_RAM13_RME_OFFSET 12
|
|
#define MUX_RAM13_RME_MASK 0x00001000
|
|
#define MUX_RAM13_RM_OFFSET 8
|
|
#define MUX_RAM13_RM_MASK 0x00000F00
|
|
#define MUX_RAM12_TEST1_OFFSET 5
|
|
#define MUX_RAM12_TEST1_MASK 0x00000020
|
|
#define MUX_RAM12_RME_OFFSET 4
|
|
#define MUX_RAM12_RME_MASK 0x00000010
|
|
#define MUX_RAM12_RM_OFFSET 0
|
|
#define MUX_RAM12_RM_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG4_ADDR 0x0040
|
|
#define MUX_RAM19_TEST1_OFFSET 29
|
|
#define MUX_RAM19_TEST1_MASK 0x20000000
|
|
#define MUX_RAM19_RME_OFFSET 28
|
|
#define MUX_RAM19_RME_MASK 0x10000000
|
|
#define MUX_RAM19_RM_OFFSET 24
|
|
#define MUX_RAM19_RM_MASK 0x0F000000
|
|
#define MUX_RAM18_TEST1_OFFSET 21
|
|
#define MUX_RAM18_TEST1_MASK 0x00200000
|
|
#define MUX_RAM18_RME_OFFSET 20
|
|
#define MUX_RAM18_RME_MASK 0x00100000
|
|
#define MUX_RAM18_RM_OFFSET 16
|
|
#define MUX_RAM18_RM_MASK 0x000F0000
|
|
#define MUX_RAM17_TEST1_OFFSET 13
|
|
#define MUX_RAM17_TEST1_MASK 0x00002000
|
|
#define MUX_RAM17_RME_OFFSET 12
|
|
#define MUX_RAM17_RME_MASK 0x00001000
|
|
#define MUX_RAM17_RM_OFFSET 8
|
|
#define MUX_RAM17_RM_MASK 0x00000F00
|
|
#define MUX_RAM16_TEST1_OFFSET 5
|
|
#define MUX_RAM16_TEST1_MASK 0x00000020
|
|
#define MUX_RAM16_RME_OFFSET 4
|
|
#define MUX_RAM16_RME_MASK 0x00000010
|
|
#define MUX_RAM16_RM_OFFSET 0
|
|
#define MUX_RAM16_RM_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG5_ADDR 0x0044
|
|
#define MUX_RAM23_TEST1_OFFSET 29
|
|
#define MUX_RAM23_TEST1_MASK 0x20000000
|
|
#define MUX_RAM23_RME_OFFSET 28
|
|
#define MUX_RAM23_RME_MASK 0x10000000
|
|
#define MUX_RAM23_RM_OFFSET 24
|
|
#define MUX_RAM23_RM_MASK 0x0F000000
|
|
#define MUX_RAM22_TEST1_OFFSET 21
|
|
#define MUX_RAM22_TEST1_MASK 0x00200000
|
|
#define MUX_RAM22_RME_OFFSET 20
|
|
#define MUX_RAM22_RME_MASK 0x00100000
|
|
#define MUX_RAM22_RM_OFFSET 16
|
|
#define MUX_RAM22_RM_MASK 0x000F0000
|
|
#define MUX_RAM21_TEST1_OFFSET 13
|
|
#define MUX_RAM21_TEST1_MASK 0x00002000
|
|
#define MUX_RAM21_RME_OFFSET 12
|
|
#define MUX_RAM21_RME_MASK 0x00001000
|
|
#define MUX_RAM21_RM_OFFSET 8
|
|
#define MUX_RAM21_RM_MASK 0x00000F00
|
|
#define MUX_RAM20_TEST1_OFFSET 5
|
|
#define MUX_RAM20_TEST1_MASK 0x00000020
|
|
#define MUX_RAM20_RME_OFFSET 4
|
|
#define MUX_RAM20_RME_MASK 0x00000010
|
|
#define MUX_RAM20_RM_OFFSET 0
|
|
#define MUX_RAM20_RM_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG6_ADDR 0x0048
|
|
#define MUX_RAM27_TEST1_OFFSET 29
|
|
#define MUX_RAM27_TEST1_MASK 0x20000000
|
|
#define MUX_RAM27_RME_OFFSET 28
|
|
#define MUX_RAM27_RME_MASK 0x10000000
|
|
#define MUX_RAM27_RM_OFFSET 24
|
|
#define MUX_RAM27_RM_MASK 0x0F000000
|
|
#define MUX_RAM26_TEST1_OFFSET 21
|
|
#define MUX_RAM26_TEST1_MASK 0x00200000
|
|
#define MUX_RAM26_RME_OFFSET 20
|
|
#define MUX_RAM26_RME_MASK 0x00100000
|
|
#define MUX_RAM26_RM_OFFSET 16
|
|
#define MUX_RAM26_RM_MASK 0x000F0000
|
|
#define MUX_RAM25_TEST1_OFFSET 13
|
|
#define MUX_RAM25_TEST1_MASK 0x00002000
|
|
#define MUX_RAM25_RME_OFFSET 12
|
|
#define MUX_RAM25_RME_MASK 0x00001000
|
|
#define MUX_RAM25_RM_OFFSET 8
|
|
#define MUX_RAM25_RM_MASK 0x00000F00
|
|
#define MUX_RAM24_TEST1_OFFSET 5
|
|
#define MUX_RAM24_TEST1_MASK 0x00000020
|
|
#define MUX_RAM24_RME_OFFSET 4
|
|
#define MUX_RAM24_RME_MASK 0x00000010
|
|
#define MUX_RAM24_RM_OFFSET 0
|
|
#define MUX_RAM24_RM_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_AI_RAM_CFG7_ADDR 0x004C
|
|
#define MUX_RAM31_TEST1_OFFSET 29
|
|
#define MUX_RAM31_TEST1_MASK 0x20000000
|
|
#define MUX_RAM31_RME_OFFSET 28
|
|
#define MUX_RAM31_RME_MASK 0x10000000
|
|
#define MUX_RAM31_RM_OFFSET 24
|
|
#define MUX_RAM31_RM_MASK 0x0F000000
|
|
#define MUX_RAM30_TEST1_OFFSET 21
|
|
#define MUX_RAM30_TEST1_MASK 0x00200000
|
|
#define MUX_RAM30_RME_OFFSET 20
|
|
#define MUX_RAM30_RME_MASK 0x00100000
|
|
#define MUX_RAM30_RM_OFFSET 16
|
|
#define MUX_RAM30_RM_MASK 0x000F0000
|
|
#define MUX_RAM29_TEST1_OFFSET 13
|
|
#define MUX_RAM29_TEST1_MASK 0x00002000
|
|
#define MUX_RAM29_RME_OFFSET 12
|
|
#define MUX_RAM29_RME_MASK 0x00001000
|
|
#define MUX_RAM29_RM_OFFSET 8
|
|
#define MUX_RAM29_RM_MASK 0x00000F00
|
|
#define MUX_RAM28_TEST1_OFFSET 5
|
|
#define MUX_RAM28_TEST1_MASK 0x00000020
|
|
#define MUX_RAM28_RME_OFFSET 4
|
|
#define MUX_RAM28_RME_MASK 0x00000010
|
|
#define MUX_RAM28_RM_OFFSET 0
|
|
#define MUX_RAM28_RM_MASK 0x0000000F
|
|
|
|
//HW module read/write macro
|
|
#define AI_GLB_READ_REG(addr) SOC_READ_REG(AI_GLB_BASEADDR + addr)
|
|
#define AI_GLB_WRITE_REG(addr,value) SOC_WRITE_REG(AI_GLB_BASEADDR + addr,value)
|