1915 lines
61 KiB
C
1915 lines
61 KiB
C
|
|
//-----------------------------------
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|
#define CFG_GPIO_INT0_ENA0_ADDR 0x0
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#define GPIO_INT0_ENA0_OFFSET 0
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#define GPIO_INT0_ENA0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT0_ENA1_ADDR 0x4
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#define GPIO_INT0_ENA1_OFFSET 0
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#define GPIO_INT0_ENA1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT0_ENA2_ADDR 0x8
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#define GPIO_INT0_ENA2_OFFSET 0
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#define GPIO_INT0_ENA2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT1_ENA0_ADDR 0xc
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#define GPIO_INT1_ENA0_OFFSET 0
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#define GPIO_INT1_ENA0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT1_ENA1_ADDR 0x10
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#define GPIO_INT1_ENA1_OFFSET 0
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#define GPIO_INT1_ENA1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT1_ENA2_ADDR 0x14
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#define GPIO_INT1_ENA2_OFFSET 0
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#define GPIO_INT1_ENA2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT0_STS0_ADDR 0x18
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#define GPIO_INT0_STS0_OFFSET 0
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#define GPIO_INT0_STS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT0_STS1_ADDR 0x1c
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#define GPIO_INT0_STS1_OFFSET 0
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#define GPIO_INT0_STS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT0_STS2_ADDR 0x20
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#define GPIO_INT0_STS2_OFFSET 0
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#define GPIO_INT0_STS2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT1_STS0_ADDR 0x24
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#define GPIO_INT1_STS0_OFFSET 0
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#define GPIO_INT1_STS0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT1_STS1_ADDR 0x28
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#define GPIO_INT1_STS1_OFFSET 0
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#define GPIO_INT1_STS1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO_INT1_STS2_ADDR 0x2c
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#define GPIO_INT1_STS2_OFFSET 0
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#define GPIO_INT1_STS2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_GPIO0_CFG_ADDR 0x40
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#define GPIO0_OD_MODE_OFFSET 12
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#define GPIO0_OD_MODE_MASK 0x00003000
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#define GPIO0_OUT_OFFSET 11
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#define GPIO0_OUT_MASK 0x00000800
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#define GPIO0_OE_OFFSET 10
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#define GPIO0_OE_MASK 0x00000400
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#define GPIO0_IE_OFFSET 9
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#define GPIO0_IE_MASK 0x00000200
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#define GPIO0_IN_OFFSET 8
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#define GPIO0_IN_MASK 0x00000100
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#define GPIO0_WAKEUP_ENA_OFFSET 7
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#define GPIO0_WAKEUP_ENA_MASK 0x00000080
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#define GPIO0_INT_TYPE_OFFSET 4
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#define GPIO0_INT_TYPE_MASK 0x00000070
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#define GPIO0_INT_RAW_OFFSET 3
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#define GPIO0_INT_RAW_MASK 0x00000008
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#define GPIO0_INT_STS_OFFSET 2
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#define GPIO0_INT_STS_MASK 0x00000004
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#define GPIO0_INT_ENA_OFFSET 1
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#define GPIO0_INT_ENA_MASK 0x00000002
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#define GPIO0_INT_CLR_OFFSET 0
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#define GPIO0_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO1_CFG_ADDR 0x44
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#define GPIO1_OD_MODE_OFFSET 12
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#define GPIO1_OD_MODE_MASK 0x00003000
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#define GPIO1_OUT_OFFSET 11
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#define GPIO1_OUT_MASK 0x00000800
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#define GPIO1_OE_OFFSET 10
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#define GPIO1_OE_MASK 0x00000400
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#define GPIO1_IE_OFFSET 9
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#define GPIO1_IE_MASK 0x00000200
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#define GPIO1_IN_OFFSET 8
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#define GPIO1_IN_MASK 0x00000100
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#define GPIO1_WAKEUP_ENA_OFFSET 7
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#define GPIO1_WAKEUP_ENA_MASK 0x00000080
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#define GPIO1_INT_TYPE_OFFSET 4
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#define GPIO1_INT_TYPE_MASK 0x00000070
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#define GPIO1_INT_RAW_OFFSET 3
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#define GPIO1_INT_RAW_MASK 0x00000008
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#define GPIO1_INT_STS_OFFSET 2
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#define GPIO1_INT_STS_MASK 0x00000004
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#define GPIO1_INT_ENA_OFFSET 1
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#define GPIO1_INT_ENA_MASK 0x00000002
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#define GPIO1_INT_CLR_OFFSET 0
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#define GPIO1_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO2_CFG_ADDR 0x48
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#define GPIO2_OD_MODE_OFFSET 12
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#define GPIO2_OD_MODE_MASK 0x00003000
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#define GPIO2_OUT_OFFSET 11
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#define GPIO2_OUT_MASK 0x00000800
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#define GPIO2_OE_OFFSET 10
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#define GPIO2_OE_MASK 0x00000400
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#define GPIO2_IE_OFFSET 9
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#define GPIO2_IE_MASK 0x00000200
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#define GPIO2_IN_OFFSET 8
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#define GPIO2_IN_MASK 0x00000100
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#define GPIO2_WAKEUP_ENA_OFFSET 7
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#define GPIO2_WAKEUP_ENA_MASK 0x00000080
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#define GPIO2_INT_TYPE_OFFSET 4
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#define GPIO2_INT_TYPE_MASK 0x00000070
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#define GPIO2_INT_RAW_OFFSET 3
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#define GPIO2_INT_RAW_MASK 0x00000008
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#define GPIO2_INT_STS_OFFSET 2
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#define GPIO2_INT_STS_MASK 0x00000004
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#define GPIO2_INT_ENA_OFFSET 1
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#define GPIO2_INT_ENA_MASK 0x00000002
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#define GPIO2_INT_CLR_OFFSET 0
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#define GPIO2_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO3_CFG_ADDR 0x4c
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#define GPIO3_OD_MODE_OFFSET 12
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#define GPIO3_OD_MODE_MASK 0x00003000
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#define GPIO3_OUT_OFFSET 11
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#define GPIO3_OUT_MASK 0x00000800
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#define GPIO3_OE_OFFSET 10
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#define GPIO3_OE_MASK 0x00000400
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#define GPIO3_IE_OFFSET 9
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#define GPIO3_IE_MASK 0x00000200
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#define GPIO3_IN_OFFSET 8
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#define GPIO3_IN_MASK 0x00000100
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#define GPIO3_WAKEUP_ENA_OFFSET 7
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#define GPIO3_WAKEUP_ENA_MASK 0x00000080
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#define GPIO3_INT_TYPE_OFFSET 4
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#define GPIO3_INT_TYPE_MASK 0x00000070
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#define GPIO3_INT_RAW_OFFSET 3
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#define GPIO3_INT_RAW_MASK 0x00000008
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#define GPIO3_INT_STS_OFFSET 2
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#define GPIO3_INT_STS_MASK 0x00000004
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#define GPIO3_INT_ENA_OFFSET 1
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#define GPIO3_INT_ENA_MASK 0x00000002
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#define GPIO3_INT_CLR_OFFSET 0
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#define GPIO3_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO4_CFG_ADDR 0x50
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#define GPIO4_OD_MODE_OFFSET 12
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#define GPIO4_OD_MODE_MASK 0x00003000
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#define GPIO4_OUT_OFFSET 11
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#define GPIO4_OUT_MASK 0x00000800
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#define GPIO4_OE_OFFSET 10
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#define GPIO4_OE_MASK 0x00000400
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#define GPIO4_IE_OFFSET 9
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#define GPIO4_IE_MASK 0x00000200
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#define GPIO4_IN_OFFSET 8
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#define GPIO4_IN_MASK 0x00000100
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#define GPIO4_WAKEUP_ENA_OFFSET 7
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#define GPIO4_WAKEUP_ENA_MASK 0x00000080
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#define GPIO4_INT_TYPE_OFFSET 4
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#define GPIO4_INT_TYPE_MASK 0x00000070
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#define GPIO4_INT_RAW_OFFSET 3
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#define GPIO4_INT_RAW_MASK 0x00000008
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#define GPIO4_INT_STS_OFFSET 2
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#define GPIO4_INT_STS_MASK 0x00000004
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#define GPIO4_INT_ENA_OFFSET 1
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#define GPIO4_INT_ENA_MASK 0x00000002
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#define GPIO4_INT_CLR_OFFSET 0
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#define GPIO4_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO5_CFG_ADDR 0x54
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#define GPIO5_OD_MODE_OFFSET 12
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#define GPIO5_OD_MODE_MASK 0x00003000
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#define GPIO5_OUT_OFFSET 11
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#define GPIO5_OUT_MASK 0x00000800
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#define GPIO5_OE_OFFSET 10
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#define GPIO5_OE_MASK 0x00000400
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#define GPIO5_IE_OFFSET 9
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#define GPIO5_IE_MASK 0x00000200
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#define GPIO5_IN_OFFSET 8
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#define GPIO5_IN_MASK 0x00000100
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#define GPIO5_WAKEUP_ENA_OFFSET 7
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#define GPIO5_WAKEUP_ENA_MASK 0x00000080
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#define GPIO5_INT_TYPE_OFFSET 4
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#define GPIO5_INT_TYPE_MASK 0x00000070
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#define GPIO5_INT_RAW_OFFSET 3
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#define GPIO5_INT_RAW_MASK 0x00000008
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#define GPIO5_INT_STS_OFFSET 2
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#define GPIO5_INT_STS_MASK 0x00000004
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#define GPIO5_INT_ENA_OFFSET 1
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#define GPIO5_INT_ENA_MASK 0x00000002
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#define GPIO5_INT_CLR_OFFSET 0
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#define GPIO5_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO6_CFG_ADDR 0x58
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#define GPIO6_OD_MODE_OFFSET 12
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#define GPIO6_OD_MODE_MASK 0x00003000
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#define GPIO6_OUT_OFFSET 11
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#define GPIO6_OUT_MASK 0x00000800
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#define GPIO6_OE_OFFSET 10
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#define GPIO6_OE_MASK 0x00000400
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#define GPIO6_IE_OFFSET 9
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#define GPIO6_IE_MASK 0x00000200
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#define GPIO6_IN_OFFSET 8
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#define GPIO6_IN_MASK 0x00000100
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#define GPIO6_WAKEUP_ENA_OFFSET 7
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#define GPIO6_WAKEUP_ENA_MASK 0x00000080
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#define GPIO6_INT_TYPE_OFFSET 4
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#define GPIO6_INT_TYPE_MASK 0x00000070
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#define GPIO6_INT_RAW_OFFSET 3
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#define GPIO6_INT_RAW_MASK 0x00000008
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#define GPIO6_INT_STS_OFFSET 2
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#define GPIO6_INT_STS_MASK 0x00000004
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#define GPIO6_INT_ENA_OFFSET 1
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#define GPIO6_INT_ENA_MASK 0x00000002
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#define GPIO6_INT_CLR_OFFSET 0
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#define GPIO6_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO7_CFG_ADDR 0x5c
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#define GPIO7_OD_MODE_OFFSET 12
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#define GPIO7_OD_MODE_MASK 0x00003000
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#define GPIO7_OUT_OFFSET 11
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#define GPIO7_OUT_MASK 0x00000800
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#define GPIO7_OE_OFFSET 10
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#define GPIO7_OE_MASK 0x00000400
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#define GPIO7_IE_OFFSET 9
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#define GPIO7_IE_MASK 0x00000200
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#define GPIO7_IN_OFFSET 8
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#define GPIO7_IN_MASK 0x00000100
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#define GPIO7_WAKEUP_ENA_OFFSET 7
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#define GPIO7_WAKEUP_ENA_MASK 0x00000080
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#define GPIO7_INT_TYPE_OFFSET 4
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#define GPIO7_INT_TYPE_MASK 0x00000070
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#define GPIO7_INT_RAW_OFFSET 3
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#define GPIO7_INT_RAW_MASK 0x00000008
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#define GPIO7_INT_STS_OFFSET 2
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#define GPIO7_INT_STS_MASK 0x00000004
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#define GPIO7_INT_ENA_OFFSET 1
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#define GPIO7_INT_ENA_MASK 0x00000002
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#define GPIO7_INT_CLR_OFFSET 0
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#define GPIO7_INT_CLR_MASK 0x00000001
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|
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//-----------------------------------
|
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#define CFG_GPIO8_CFG_ADDR 0x60
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#define GPIO8_OD_MODE_OFFSET 12
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#define GPIO8_OD_MODE_MASK 0x00003000
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#define GPIO8_OUT_OFFSET 11
|
|
#define GPIO8_OUT_MASK 0x00000800
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#define GPIO8_OE_OFFSET 10
|
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#define GPIO8_OE_MASK 0x00000400
|
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#define GPIO8_IE_OFFSET 9
|
|
#define GPIO8_IE_MASK 0x00000200
|
|
#define GPIO8_IN_OFFSET 8
|
|
#define GPIO8_IN_MASK 0x00000100
|
|
#define GPIO8_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO8_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO8_INT_TYPE_OFFSET 4
|
|
#define GPIO8_INT_TYPE_MASK 0x00000070
|
|
#define GPIO8_INT_RAW_OFFSET 3
|
|
#define GPIO8_INT_RAW_MASK 0x00000008
|
|
#define GPIO8_INT_STS_OFFSET 2
|
|
#define GPIO8_INT_STS_MASK 0x00000004
|
|
#define GPIO8_INT_ENA_OFFSET 1
|
|
#define GPIO8_INT_ENA_MASK 0x00000002
|
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#define GPIO8_INT_CLR_OFFSET 0
|
|
#define GPIO8_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
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#define CFG_GPIO9_CFG_ADDR 0x64
|
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#define GPIO9_OD_MODE_OFFSET 12
|
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#define GPIO9_OD_MODE_MASK 0x00003000
|
|
#define GPIO9_OUT_OFFSET 11
|
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#define GPIO9_OUT_MASK 0x00000800
|
|
#define GPIO9_OE_OFFSET 10
|
|
#define GPIO9_OE_MASK 0x00000400
|
|
#define GPIO9_IE_OFFSET 9
|
|
#define GPIO9_IE_MASK 0x00000200
|
|
#define GPIO9_IN_OFFSET 8
|
|
#define GPIO9_IN_MASK 0x00000100
|
|
#define GPIO9_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO9_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO9_INT_TYPE_OFFSET 4
|
|
#define GPIO9_INT_TYPE_MASK 0x00000070
|
|
#define GPIO9_INT_RAW_OFFSET 3
|
|
#define GPIO9_INT_RAW_MASK 0x00000008
|
|
#define GPIO9_INT_STS_OFFSET 2
|
|
#define GPIO9_INT_STS_MASK 0x00000004
|
|
#define GPIO9_INT_ENA_OFFSET 1
|
|
#define GPIO9_INT_ENA_MASK 0x00000002
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#define GPIO9_INT_CLR_OFFSET 0
|
|
#define GPIO9_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
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#define CFG_GPIO10_CFG_ADDR 0x68
|
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#define GPIO10_OD_MODE_OFFSET 12
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#define GPIO10_OD_MODE_MASK 0x00003000
|
|
#define GPIO10_OUT_OFFSET 11
|
|
#define GPIO10_OUT_MASK 0x00000800
|
|
#define GPIO10_OE_OFFSET 10
|
|
#define GPIO10_OE_MASK 0x00000400
|
|
#define GPIO10_IE_OFFSET 9
|
|
#define GPIO10_IE_MASK 0x00000200
|
|
#define GPIO10_IN_OFFSET 8
|
|
#define GPIO10_IN_MASK 0x00000100
|
|
#define GPIO10_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO10_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO10_INT_TYPE_OFFSET 4
|
|
#define GPIO10_INT_TYPE_MASK 0x00000070
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#define GPIO10_INT_RAW_OFFSET 3
|
|
#define GPIO10_INT_RAW_MASK 0x00000008
|
|
#define GPIO10_INT_STS_OFFSET 2
|
|
#define GPIO10_INT_STS_MASK 0x00000004
|
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#define GPIO10_INT_ENA_OFFSET 1
|
|
#define GPIO10_INT_ENA_MASK 0x00000002
|
|
#define GPIO10_INT_CLR_OFFSET 0
|
|
#define GPIO10_INT_CLR_MASK 0x00000001
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|
|
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//-----------------------------------
|
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#define CFG_GPIO11_CFG_ADDR 0x6c
|
|
#define GPIO11_OD_MODE_OFFSET 12
|
|
#define GPIO11_OD_MODE_MASK 0x00003000
|
|
#define GPIO11_OUT_OFFSET 11
|
|
#define GPIO11_OUT_MASK 0x00000800
|
|
#define GPIO11_OE_OFFSET 10
|
|
#define GPIO11_OE_MASK 0x00000400
|
|
#define GPIO11_IE_OFFSET 9
|
|
#define GPIO11_IE_MASK 0x00000200
|
|
#define GPIO11_IN_OFFSET 8
|
|
#define GPIO11_IN_MASK 0x00000100
|
|
#define GPIO11_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO11_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO11_INT_TYPE_OFFSET 4
|
|
#define GPIO11_INT_TYPE_MASK 0x00000070
|
|
#define GPIO11_INT_RAW_OFFSET 3
|
|
#define GPIO11_INT_RAW_MASK 0x00000008
|
|
#define GPIO11_INT_STS_OFFSET 2
|
|
#define GPIO11_INT_STS_MASK 0x00000004
|
|
#define GPIO11_INT_ENA_OFFSET 1
|
|
#define GPIO11_INT_ENA_MASK 0x00000002
|
|
#define GPIO11_INT_CLR_OFFSET 0
|
|
#define GPIO11_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO12_CFG_ADDR 0x70
|
|
#define GPIO12_OD_MODE_OFFSET 12
|
|
#define GPIO12_OD_MODE_MASK 0x00003000
|
|
#define GPIO12_OUT_OFFSET 11
|
|
#define GPIO12_OUT_MASK 0x00000800
|
|
#define GPIO12_OE_OFFSET 10
|
|
#define GPIO12_OE_MASK 0x00000400
|
|
#define GPIO12_IE_OFFSET 9
|
|
#define GPIO12_IE_MASK 0x00000200
|
|
#define GPIO12_IN_OFFSET 8
|
|
#define GPIO12_IN_MASK 0x00000100
|
|
#define GPIO12_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO12_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO12_INT_TYPE_OFFSET 4
|
|
#define GPIO12_INT_TYPE_MASK 0x00000070
|
|
#define GPIO12_INT_RAW_OFFSET 3
|
|
#define GPIO12_INT_RAW_MASK 0x00000008
|
|
#define GPIO12_INT_STS_OFFSET 2
|
|
#define GPIO12_INT_STS_MASK 0x00000004
|
|
#define GPIO12_INT_ENA_OFFSET 1
|
|
#define GPIO12_INT_ENA_MASK 0x00000002
|
|
#define GPIO12_INT_CLR_OFFSET 0
|
|
#define GPIO12_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO13_CFG_ADDR 0x74
|
|
#define GPIO13_OD_MODE_OFFSET 12
|
|
#define GPIO13_OD_MODE_MASK 0x00003000
|
|
#define GPIO13_OUT_OFFSET 11
|
|
#define GPIO13_OUT_MASK 0x00000800
|
|
#define GPIO13_OE_OFFSET 10
|
|
#define GPIO13_OE_MASK 0x00000400
|
|
#define GPIO13_IE_OFFSET 9
|
|
#define GPIO13_IE_MASK 0x00000200
|
|
#define GPIO13_IN_OFFSET 8
|
|
#define GPIO13_IN_MASK 0x00000100
|
|
#define GPIO13_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO13_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO13_INT_TYPE_OFFSET 4
|
|
#define GPIO13_INT_TYPE_MASK 0x00000070
|
|
#define GPIO13_INT_RAW_OFFSET 3
|
|
#define GPIO13_INT_RAW_MASK 0x00000008
|
|
#define GPIO13_INT_STS_OFFSET 2
|
|
#define GPIO13_INT_STS_MASK 0x00000004
|
|
#define GPIO13_INT_ENA_OFFSET 1
|
|
#define GPIO13_INT_ENA_MASK 0x00000002
|
|
#define GPIO13_INT_CLR_OFFSET 0
|
|
#define GPIO13_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO14_CFG_ADDR 0x78
|
|
#define GPIO14_OD_MODE_OFFSET 12
|
|
#define GPIO14_OD_MODE_MASK 0x00003000
|
|
#define GPIO14_OUT_OFFSET 11
|
|
#define GPIO14_OUT_MASK 0x00000800
|
|
#define GPIO14_OE_OFFSET 10
|
|
#define GPIO14_OE_MASK 0x00000400
|
|
#define GPIO14_IE_OFFSET 9
|
|
#define GPIO14_IE_MASK 0x00000200
|
|
#define GPIO14_IN_OFFSET 8
|
|
#define GPIO14_IN_MASK 0x00000100
|
|
#define GPIO14_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO14_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO14_INT_TYPE_OFFSET 4
|
|
#define GPIO14_INT_TYPE_MASK 0x00000070
|
|
#define GPIO14_INT_RAW_OFFSET 3
|
|
#define GPIO14_INT_RAW_MASK 0x00000008
|
|
#define GPIO14_INT_STS_OFFSET 2
|
|
#define GPIO14_INT_STS_MASK 0x00000004
|
|
#define GPIO14_INT_ENA_OFFSET 1
|
|
#define GPIO14_INT_ENA_MASK 0x00000002
|
|
#define GPIO14_INT_CLR_OFFSET 0
|
|
#define GPIO14_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO15_CFG_ADDR 0x7c
|
|
#define GPIO15_OD_MODE_OFFSET 12
|
|
#define GPIO15_OD_MODE_MASK 0x00003000
|
|
#define GPIO15_OUT_OFFSET 11
|
|
#define GPIO15_OUT_MASK 0x00000800
|
|
#define GPIO15_OE_OFFSET 10
|
|
#define GPIO15_OE_MASK 0x00000400
|
|
#define GPIO15_IE_OFFSET 9
|
|
#define GPIO15_IE_MASK 0x00000200
|
|
#define GPIO15_IN_OFFSET 8
|
|
#define GPIO15_IN_MASK 0x00000100
|
|
#define GPIO15_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO15_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO15_INT_TYPE_OFFSET 4
|
|
#define GPIO15_INT_TYPE_MASK 0x00000070
|
|
#define GPIO15_INT_RAW_OFFSET 3
|
|
#define GPIO15_INT_RAW_MASK 0x00000008
|
|
#define GPIO15_INT_STS_OFFSET 2
|
|
#define GPIO15_INT_STS_MASK 0x00000004
|
|
#define GPIO15_INT_ENA_OFFSET 1
|
|
#define GPIO15_INT_ENA_MASK 0x00000002
|
|
#define GPIO15_INT_CLR_OFFSET 0
|
|
#define GPIO15_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO16_CFG_ADDR 0x80
|
|
#define GPIO16_OD_MODE_OFFSET 12
|
|
#define GPIO16_OD_MODE_MASK 0x00003000
|
|
#define GPIO16_OUT_OFFSET 11
|
|
#define GPIO16_OUT_MASK 0x00000800
|
|
#define GPIO16_OE_OFFSET 10
|
|
#define GPIO16_OE_MASK 0x00000400
|
|
#define GPIO16_IE_OFFSET 9
|
|
#define GPIO16_IE_MASK 0x00000200
|
|
#define GPIO16_IN_OFFSET 8
|
|
#define GPIO16_IN_MASK 0x00000100
|
|
#define GPIO16_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO16_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO16_INT_TYPE_OFFSET 4
|
|
#define GPIO16_INT_TYPE_MASK 0x00000070
|
|
#define GPIO16_INT_RAW_OFFSET 3
|
|
#define GPIO16_INT_RAW_MASK 0x00000008
|
|
#define GPIO16_INT_STS_OFFSET 2
|
|
#define GPIO16_INT_STS_MASK 0x00000004
|
|
#define GPIO16_INT_ENA_OFFSET 1
|
|
#define GPIO16_INT_ENA_MASK 0x00000002
|
|
#define GPIO16_INT_CLR_OFFSET 0
|
|
#define GPIO16_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO17_CFG_ADDR 0x84
|
|
#define GPIO17_OD_MODE_OFFSET 12
|
|
#define GPIO17_OD_MODE_MASK 0x00003000
|
|
#define GPIO17_OUT_OFFSET 11
|
|
#define GPIO17_OUT_MASK 0x00000800
|
|
#define GPIO17_OE_OFFSET 10
|
|
#define GPIO17_OE_MASK 0x00000400
|
|
#define GPIO17_IE_OFFSET 9
|
|
#define GPIO17_IE_MASK 0x00000200
|
|
#define GPIO17_IN_OFFSET 8
|
|
#define GPIO17_IN_MASK 0x00000100
|
|
#define GPIO17_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO17_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO17_INT_TYPE_OFFSET 4
|
|
#define GPIO17_INT_TYPE_MASK 0x00000070
|
|
#define GPIO17_INT_RAW_OFFSET 3
|
|
#define GPIO17_INT_RAW_MASK 0x00000008
|
|
#define GPIO17_INT_STS_OFFSET 2
|
|
#define GPIO17_INT_STS_MASK 0x00000004
|
|
#define GPIO17_INT_ENA_OFFSET 1
|
|
#define GPIO17_INT_ENA_MASK 0x00000002
|
|
#define GPIO17_INT_CLR_OFFSET 0
|
|
#define GPIO17_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO18_CFG_ADDR 0x88
|
|
#define GPIO18_OD_MODE_OFFSET 12
|
|
#define GPIO18_OD_MODE_MASK 0x00003000
|
|
#define GPIO18_OUT_OFFSET 11
|
|
#define GPIO18_OUT_MASK 0x00000800
|
|
#define GPIO18_OE_OFFSET 10
|
|
#define GPIO18_OE_MASK 0x00000400
|
|
#define GPIO18_IE_OFFSET 9
|
|
#define GPIO18_IE_MASK 0x00000200
|
|
#define GPIO18_IN_OFFSET 8
|
|
#define GPIO18_IN_MASK 0x00000100
|
|
#define GPIO18_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO18_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO18_INT_TYPE_OFFSET 4
|
|
#define GPIO18_INT_TYPE_MASK 0x00000070
|
|
#define GPIO18_INT_RAW_OFFSET 3
|
|
#define GPIO18_INT_RAW_MASK 0x00000008
|
|
#define GPIO18_INT_STS_OFFSET 2
|
|
#define GPIO18_INT_STS_MASK 0x00000004
|
|
#define GPIO18_INT_ENA_OFFSET 1
|
|
#define GPIO18_INT_ENA_MASK 0x00000002
|
|
#define GPIO18_INT_CLR_OFFSET 0
|
|
#define GPIO18_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO19_CFG_ADDR 0x8c
|
|
#define GPIO19_OD_MODE_OFFSET 12
|
|
#define GPIO19_OD_MODE_MASK 0x00003000
|
|
#define GPIO19_OUT_OFFSET 11
|
|
#define GPIO19_OUT_MASK 0x00000800
|
|
#define GPIO19_OE_OFFSET 10
|
|
#define GPIO19_OE_MASK 0x00000400
|
|
#define GPIO19_IE_OFFSET 9
|
|
#define GPIO19_IE_MASK 0x00000200
|
|
#define GPIO19_IN_OFFSET 8
|
|
#define GPIO19_IN_MASK 0x00000100
|
|
#define GPIO19_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO19_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO19_INT_TYPE_OFFSET 4
|
|
#define GPIO19_INT_TYPE_MASK 0x00000070
|
|
#define GPIO19_INT_RAW_OFFSET 3
|
|
#define GPIO19_INT_RAW_MASK 0x00000008
|
|
#define GPIO19_INT_STS_OFFSET 2
|
|
#define GPIO19_INT_STS_MASK 0x00000004
|
|
#define GPIO19_INT_ENA_OFFSET 1
|
|
#define GPIO19_INT_ENA_MASK 0x00000002
|
|
#define GPIO19_INT_CLR_OFFSET 0
|
|
#define GPIO19_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO20_CFG_ADDR 0x90
|
|
#define GPIO20_OD_MODE_OFFSET 12
|
|
#define GPIO20_OD_MODE_MASK 0x00003000
|
|
#define GPIO20_OUT_OFFSET 11
|
|
#define GPIO20_OUT_MASK 0x00000800
|
|
#define GPIO20_OE_OFFSET 10
|
|
#define GPIO20_OE_MASK 0x00000400
|
|
#define GPIO20_IE_OFFSET 9
|
|
#define GPIO20_IE_MASK 0x00000200
|
|
#define GPIO20_IN_OFFSET 8
|
|
#define GPIO20_IN_MASK 0x00000100
|
|
#define GPIO20_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO20_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO20_INT_TYPE_OFFSET 4
|
|
#define GPIO20_INT_TYPE_MASK 0x00000070
|
|
#define GPIO20_INT_RAW_OFFSET 3
|
|
#define GPIO20_INT_RAW_MASK 0x00000008
|
|
#define GPIO20_INT_STS_OFFSET 2
|
|
#define GPIO20_INT_STS_MASK 0x00000004
|
|
#define GPIO20_INT_ENA_OFFSET 1
|
|
#define GPIO20_INT_ENA_MASK 0x00000002
|
|
#define GPIO20_INT_CLR_OFFSET 0
|
|
#define GPIO20_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO21_CFG_ADDR 0x94
|
|
#define GPIO21_OD_MODE_OFFSET 12
|
|
#define GPIO21_OD_MODE_MASK 0x00003000
|
|
#define GPIO21_OUT_OFFSET 11
|
|
#define GPIO21_OUT_MASK 0x00000800
|
|
#define GPIO21_OE_OFFSET 10
|
|
#define GPIO21_OE_MASK 0x00000400
|
|
#define GPIO21_IE_OFFSET 9
|
|
#define GPIO21_IE_MASK 0x00000200
|
|
#define GPIO21_IN_OFFSET 8
|
|
#define GPIO21_IN_MASK 0x00000100
|
|
#define GPIO21_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO21_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO21_INT_TYPE_OFFSET 4
|
|
#define GPIO21_INT_TYPE_MASK 0x00000070
|
|
#define GPIO21_INT_RAW_OFFSET 3
|
|
#define GPIO21_INT_RAW_MASK 0x00000008
|
|
#define GPIO21_INT_STS_OFFSET 2
|
|
#define GPIO21_INT_STS_MASK 0x00000004
|
|
#define GPIO21_INT_ENA_OFFSET 1
|
|
#define GPIO21_INT_ENA_MASK 0x00000002
|
|
#define GPIO21_INT_CLR_OFFSET 0
|
|
#define GPIO21_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO22_CFG_ADDR 0x98
|
|
#define GPIO22_OD_MODE_OFFSET 12
|
|
#define GPIO22_OD_MODE_MASK 0x00003000
|
|
#define GPIO22_OUT_OFFSET 11
|
|
#define GPIO22_OUT_MASK 0x00000800
|
|
#define GPIO22_OE_OFFSET 10
|
|
#define GPIO22_OE_MASK 0x00000400
|
|
#define GPIO22_IE_OFFSET 9
|
|
#define GPIO22_IE_MASK 0x00000200
|
|
#define GPIO22_IN_OFFSET 8
|
|
#define GPIO22_IN_MASK 0x00000100
|
|
#define GPIO22_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO22_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO22_INT_TYPE_OFFSET 4
|
|
#define GPIO22_INT_TYPE_MASK 0x00000070
|
|
#define GPIO22_INT_RAW_OFFSET 3
|
|
#define GPIO22_INT_RAW_MASK 0x00000008
|
|
#define GPIO22_INT_STS_OFFSET 2
|
|
#define GPIO22_INT_STS_MASK 0x00000004
|
|
#define GPIO22_INT_ENA_OFFSET 1
|
|
#define GPIO22_INT_ENA_MASK 0x00000002
|
|
#define GPIO22_INT_CLR_OFFSET 0
|
|
#define GPIO22_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO23_CFG_ADDR 0x9c
|
|
#define GPIO23_OD_MODE_OFFSET 12
|
|
#define GPIO23_OD_MODE_MASK 0x00003000
|
|
#define GPIO23_OUT_OFFSET 11
|
|
#define GPIO23_OUT_MASK 0x00000800
|
|
#define GPIO23_OE_OFFSET 10
|
|
#define GPIO23_OE_MASK 0x00000400
|
|
#define GPIO23_IE_OFFSET 9
|
|
#define GPIO23_IE_MASK 0x00000200
|
|
#define GPIO23_IN_OFFSET 8
|
|
#define GPIO23_IN_MASK 0x00000100
|
|
#define GPIO23_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO23_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO23_INT_TYPE_OFFSET 4
|
|
#define GPIO23_INT_TYPE_MASK 0x00000070
|
|
#define GPIO23_INT_RAW_OFFSET 3
|
|
#define GPIO23_INT_RAW_MASK 0x00000008
|
|
#define GPIO23_INT_STS_OFFSET 2
|
|
#define GPIO23_INT_STS_MASK 0x00000004
|
|
#define GPIO23_INT_ENA_OFFSET 1
|
|
#define GPIO23_INT_ENA_MASK 0x00000002
|
|
#define GPIO23_INT_CLR_OFFSET 0
|
|
#define GPIO23_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO24_CFG_ADDR 0xa0
|
|
#define GPIO24_OD_MODE_OFFSET 12
|
|
#define GPIO24_OD_MODE_MASK 0x00003000
|
|
#define GPIO24_OUT_OFFSET 11
|
|
#define GPIO24_OUT_MASK 0x00000800
|
|
#define GPIO24_OE_OFFSET 10
|
|
#define GPIO24_OE_MASK 0x00000400
|
|
#define GPIO24_IE_OFFSET 9
|
|
#define GPIO24_IE_MASK 0x00000200
|
|
#define GPIO24_IN_OFFSET 8
|
|
#define GPIO24_IN_MASK 0x00000100
|
|
#define GPIO24_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO24_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO24_INT_TYPE_OFFSET 4
|
|
#define GPIO24_INT_TYPE_MASK 0x00000070
|
|
#define GPIO24_INT_RAW_OFFSET 3
|
|
#define GPIO24_INT_RAW_MASK 0x00000008
|
|
#define GPIO24_INT_STS_OFFSET 2
|
|
#define GPIO24_INT_STS_MASK 0x00000004
|
|
#define GPIO24_INT_ENA_OFFSET 1
|
|
#define GPIO24_INT_ENA_MASK 0x00000002
|
|
#define GPIO24_INT_CLR_OFFSET 0
|
|
#define GPIO24_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO25_CFG_ADDR 0xa4
|
|
#define GPIO25_OD_MODE_OFFSET 12
|
|
#define GPIO25_OD_MODE_MASK 0x00003000
|
|
#define GPIO25_OUT_OFFSET 11
|
|
#define GPIO25_OUT_MASK 0x00000800
|
|
#define GPIO25_OE_OFFSET 10
|
|
#define GPIO25_OE_MASK 0x00000400
|
|
#define GPIO25_IE_OFFSET 9
|
|
#define GPIO25_IE_MASK 0x00000200
|
|
#define GPIO25_IN_OFFSET 8
|
|
#define GPIO25_IN_MASK 0x00000100
|
|
#define GPIO25_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO25_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO25_INT_TYPE_OFFSET 4
|
|
#define GPIO25_INT_TYPE_MASK 0x00000070
|
|
#define GPIO25_INT_RAW_OFFSET 3
|
|
#define GPIO25_INT_RAW_MASK 0x00000008
|
|
#define GPIO25_INT_STS_OFFSET 2
|
|
#define GPIO25_INT_STS_MASK 0x00000004
|
|
#define GPIO25_INT_ENA_OFFSET 1
|
|
#define GPIO25_INT_ENA_MASK 0x00000002
|
|
#define GPIO25_INT_CLR_OFFSET 0
|
|
#define GPIO25_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO26_CFG_ADDR 0xa8
|
|
#define GPIO26_OD_MODE_OFFSET 12
|
|
#define GPIO26_OD_MODE_MASK 0x00003000
|
|
#define GPIO26_OUT_OFFSET 11
|
|
#define GPIO26_OUT_MASK 0x00000800
|
|
#define GPIO26_OE_OFFSET 10
|
|
#define GPIO26_OE_MASK 0x00000400
|
|
#define GPIO26_IE_OFFSET 9
|
|
#define GPIO26_IE_MASK 0x00000200
|
|
#define GPIO26_IN_OFFSET 8
|
|
#define GPIO26_IN_MASK 0x00000100
|
|
#define GPIO26_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO26_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO26_INT_TYPE_OFFSET 4
|
|
#define GPIO26_INT_TYPE_MASK 0x00000070
|
|
#define GPIO26_INT_RAW_OFFSET 3
|
|
#define GPIO26_INT_RAW_MASK 0x00000008
|
|
#define GPIO26_INT_STS_OFFSET 2
|
|
#define GPIO26_INT_STS_MASK 0x00000004
|
|
#define GPIO26_INT_ENA_OFFSET 1
|
|
#define GPIO26_INT_ENA_MASK 0x00000002
|
|
#define GPIO26_INT_CLR_OFFSET 0
|
|
#define GPIO26_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO27_CFG_ADDR 0xac
|
|
#define GPIO27_OD_MODE_OFFSET 12
|
|
#define GPIO27_OD_MODE_MASK 0x00003000
|
|
#define GPIO27_OUT_OFFSET 11
|
|
#define GPIO27_OUT_MASK 0x00000800
|
|
#define GPIO27_OE_OFFSET 10
|
|
#define GPIO27_OE_MASK 0x00000400
|
|
#define GPIO27_IE_OFFSET 9
|
|
#define GPIO27_IE_MASK 0x00000200
|
|
#define GPIO27_IN_OFFSET 8
|
|
#define GPIO27_IN_MASK 0x00000100
|
|
#define GPIO27_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO27_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO27_INT_TYPE_OFFSET 4
|
|
#define GPIO27_INT_TYPE_MASK 0x00000070
|
|
#define GPIO27_INT_RAW_OFFSET 3
|
|
#define GPIO27_INT_RAW_MASK 0x00000008
|
|
#define GPIO27_INT_STS_OFFSET 2
|
|
#define GPIO27_INT_STS_MASK 0x00000004
|
|
#define GPIO27_INT_ENA_OFFSET 1
|
|
#define GPIO27_INT_ENA_MASK 0x00000002
|
|
#define GPIO27_INT_CLR_OFFSET 0
|
|
#define GPIO27_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO28_CFG_ADDR 0xb0
|
|
#define GPIO28_OD_MODE_OFFSET 12
|
|
#define GPIO28_OD_MODE_MASK 0x00003000
|
|
#define GPIO28_OUT_OFFSET 11
|
|
#define GPIO28_OUT_MASK 0x00000800
|
|
#define GPIO28_OE_OFFSET 10
|
|
#define GPIO28_OE_MASK 0x00000400
|
|
#define GPIO28_IE_OFFSET 9
|
|
#define GPIO28_IE_MASK 0x00000200
|
|
#define GPIO28_IN_OFFSET 8
|
|
#define GPIO28_IN_MASK 0x00000100
|
|
#define GPIO28_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO28_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO28_INT_TYPE_OFFSET 4
|
|
#define GPIO28_INT_TYPE_MASK 0x00000070
|
|
#define GPIO28_INT_RAW_OFFSET 3
|
|
#define GPIO28_INT_RAW_MASK 0x00000008
|
|
#define GPIO28_INT_STS_OFFSET 2
|
|
#define GPIO28_INT_STS_MASK 0x00000004
|
|
#define GPIO28_INT_ENA_OFFSET 1
|
|
#define GPIO28_INT_ENA_MASK 0x00000002
|
|
#define GPIO28_INT_CLR_OFFSET 0
|
|
#define GPIO28_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO29_CFG_ADDR 0xb4
|
|
#define GPIO29_OD_MODE_OFFSET 12
|
|
#define GPIO29_OD_MODE_MASK 0x00003000
|
|
#define GPIO29_OUT_OFFSET 11
|
|
#define GPIO29_OUT_MASK 0x00000800
|
|
#define GPIO29_OE_OFFSET 10
|
|
#define GPIO29_OE_MASK 0x00000400
|
|
#define GPIO29_IE_OFFSET 9
|
|
#define GPIO29_IE_MASK 0x00000200
|
|
#define GPIO29_IN_OFFSET 8
|
|
#define GPIO29_IN_MASK 0x00000100
|
|
#define GPIO29_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO29_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO29_INT_TYPE_OFFSET 4
|
|
#define GPIO29_INT_TYPE_MASK 0x00000070
|
|
#define GPIO29_INT_RAW_OFFSET 3
|
|
#define GPIO29_INT_RAW_MASK 0x00000008
|
|
#define GPIO29_INT_STS_OFFSET 2
|
|
#define GPIO29_INT_STS_MASK 0x00000004
|
|
#define GPIO29_INT_ENA_OFFSET 1
|
|
#define GPIO29_INT_ENA_MASK 0x00000002
|
|
#define GPIO29_INT_CLR_OFFSET 0
|
|
#define GPIO29_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO30_CFG_ADDR 0xb8
|
|
#define GPIO30_OD_MODE_OFFSET 12
|
|
#define GPIO30_OD_MODE_MASK 0x00003000
|
|
#define GPIO30_OUT_OFFSET 11
|
|
#define GPIO30_OUT_MASK 0x00000800
|
|
#define GPIO30_OE_OFFSET 10
|
|
#define GPIO30_OE_MASK 0x00000400
|
|
#define GPIO30_IE_OFFSET 9
|
|
#define GPIO30_IE_MASK 0x00000200
|
|
#define GPIO30_IN_OFFSET 8
|
|
#define GPIO30_IN_MASK 0x00000100
|
|
#define GPIO30_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO30_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO30_INT_TYPE_OFFSET 4
|
|
#define GPIO30_INT_TYPE_MASK 0x00000070
|
|
#define GPIO30_INT_RAW_OFFSET 3
|
|
#define GPIO30_INT_RAW_MASK 0x00000008
|
|
#define GPIO30_INT_STS_OFFSET 2
|
|
#define GPIO30_INT_STS_MASK 0x00000004
|
|
#define GPIO30_INT_ENA_OFFSET 1
|
|
#define GPIO30_INT_ENA_MASK 0x00000002
|
|
#define GPIO30_INT_CLR_OFFSET 0
|
|
#define GPIO30_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO31_CFG_ADDR 0xbc
|
|
#define GPIO31_OD_MODE_OFFSET 12
|
|
#define GPIO31_OD_MODE_MASK 0x00003000
|
|
#define GPIO31_OUT_OFFSET 11
|
|
#define GPIO31_OUT_MASK 0x00000800
|
|
#define GPIO31_OE_OFFSET 10
|
|
#define GPIO31_OE_MASK 0x00000400
|
|
#define GPIO31_IE_OFFSET 9
|
|
#define GPIO31_IE_MASK 0x00000200
|
|
#define GPIO31_IN_OFFSET 8
|
|
#define GPIO31_IN_MASK 0x00000100
|
|
#define GPIO31_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO31_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO31_INT_TYPE_OFFSET 4
|
|
#define GPIO31_INT_TYPE_MASK 0x00000070
|
|
#define GPIO31_INT_RAW_OFFSET 3
|
|
#define GPIO31_INT_RAW_MASK 0x00000008
|
|
#define GPIO31_INT_STS_OFFSET 2
|
|
#define GPIO31_INT_STS_MASK 0x00000004
|
|
#define GPIO31_INT_ENA_OFFSET 1
|
|
#define GPIO31_INT_ENA_MASK 0x00000002
|
|
#define GPIO31_INT_CLR_OFFSET 0
|
|
#define GPIO31_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO32_CFG_ADDR 0xc0
|
|
#define GPIO32_OD_MODE_OFFSET 12
|
|
#define GPIO32_OD_MODE_MASK 0x00003000
|
|
#define GPIO32_OUT_OFFSET 11
|
|
#define GPIO32_OUT_MASK 0x00000800
|
|
#define GPIO32_OE_OFFSET 10
|
|
#define GPIO32_OE_MASK 0x00000400
|
|
#define GPIO32_IE_OFFSET 9
|
|
#define GPIO32_IE_MASK 0x00000200
|
|
#define GPIO32_IN_OFFSET 8
|
|
#define GPIO32_IN_MASK 0x00000100
|
|
#define GPIO32_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO32_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO32_INT_TYPE_OFFSET 4
|
|
#define GPIO32_INT_TYPE_MASK 0x00000070
|
|
#define GPIO32_INT_RAW_OFFSET 3
|
|
#define GPIO32_INT_RAW_MASK 0x00000008
|
|
#define GPIO32_INT_STS_OFFSET 2
|
|
#define GPIO32_INT_STS_MASK 0x00000004
|
|
#define GPIO32_INT_ENA_OFFSET 1
|
|
#define GPIO32_INT_ENA_MASK 0x00000002
|
|
#define GPIO32_INT_CLR_OFFSET 0
|
|
#define GPIO32_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO33_CFG_ADDR 0xc4
|
|
#define GPIO33_OD_MODE_OFFSET 12
|
|
#define GPIO33_OD_MODE_MASK 0x00003000
|
|
#define GPIO33_OUT_OFFSET 11
|
|
#define GPIO33_OUT_MASK 0x00000800
|
|
#define GPIO33_OE_OFFSET 10
|
|
#define GPIO33_OE_MASK 0x00000400
|
|
#define GPIO33_IE_OFFSET 9
|
|
#define GPIO33_IE_MASK 0x00000200
|
|
#define GPIO33_IN_OFFSET 8
|
|
#define GPIO33_IN_MASK 0x00000100
|
|
#define GPIO33_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO33_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO33_INT_TYPE_OFFSET 4
|
|
#define GPIO33_INT_TYPE_MASK 0x00000070
|
|
#define GPIO33_INT_RAW_OFFSET 3
|
|
#define GPIO33_INT_RAW_MASK 0x00000008
|
|
#define GPIO33_INT_STS_OFFSET 2
|
|
#define GPIO33_INT_STS_MASK 0x00000004
|
|
#define GPIO33_INT_ENA_OFFSET 1
|
|
#define GPIO33_INT_ENA_MASK 0x00000002
|
|
#define GPIO33_INT_CLR_OFFSET 0
|
|
#define GPIO33_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO34_CFG_ADDR 0xc8
|
|
#define GPIO34_OD_MODE_OFFSET 12
|
|
#define GPIO34_OD_MODE_MASK 0x00003000
|
|
#define GPIO34_OUT_OFFSET 11
|
|
#define GPIO34_OUT_MASK 0x00000800
|
|
#define GPIO34_OE_OFFSET 10
|
|
#define GPIO34_OE_MASK 0x00000400
|
|
#define GPIO34_IE_OFFSET 9
|
|
#define GPIO34_IE_MASK 0x00000200
|
|
#define GPIO34_IN_OFFSET 8
|
|
#define GPIO34_IN_MASK 0x00000100
|
|
#define GPIO34_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO34_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO34_INT_TYPE_OFFSET 4
|
|
#define GPIO34_INT_TYPE_MASK 0x00000070
|
|
#define GPIO34_INT_RAW_OFFSET 3
|
|
#define GPIO34_INT_RAW_MASK 0x00000008
|
|
#define GPIO34_INT_STS_OFFSET 2
|
|
#define GPIO34_INT_STS_MASK 0x00000004
|
|
#define GPIO34_INT_ENA_OFFSET 1
|
|
#define GPIO34_INT_ENA_MASK 0x00000002
|
|
#define GPIO34_INT_CLR_OFFSET 0
|
|
#define GPIO34_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO35_CFG_ADDR 0xcc
|
|
#define GPIO35_OD_MODE_OFFSET 12
|
|
#define GPIO35_OD_MODE_MASK 0x00003000
|
|
#define GPIO35_OUT_OFFSET 11
|
|
#define GPIO35_OUT_MASK 0x00000800
|
|
#define GPIO35_OE_OFFSET 10
|
|
#define GPIO35_OE_MASK 0x00000400
|
|
#define GPIO35_IE_OFFSET 9
|
|
#define GPIO35_IE_MASK 0x00000200
|
|
#define GPIO35_IN_OFFSET 8
|
|
#define GPIO35_IN_MASK 0x00000100
|
|
#define GPIO35_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO35_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO35_INT_TYPE_OFFSET 4
|
|
#define GPIO35_INT_TYPE_MASK 0x00000070
|
|
#define GPIO35_INT_RAW_OFFSET 3
|
|
#define GPIO35_INT_RAW_MASK 0x00000008
|
|
#define GPIO35_INT_STS_OFFSET 2
|
|
#define GPIO35_INT_STS_MASK 0x00000004
|
|
#define GPIO35_INT_ENA_OFFSET 1
|
|
#define GPIO35_INT_ENA_MASK 0x00000002
|
|
#define GPIO35_INT_CLR_OFFSET 0
|
|
#define GPIO35_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO36_CFG_ADDR 0xd0
|
|
#define GPIO36_OD_MODE_OFFSET 12
|
|
#define GPIO36_OD_MODE_MASK 0x00003000
|
|
#define GPIO36_OUT_OFFSET 11
|
|
#define GPIO36_OUT_MASK 0x00000800
|
|
#define GPIO36_OE_OFFSET 10
|
|
#define GPIO36_OE_MASK 0x00000400
|
|
#define GPIO36_IE_OFFSET 9
|
|
#define GPIO36_IE_MASK 0x00000200
|
|
#define GPIO36_IN_OFFSET 8
|
|
#define GPIO36_IN_MASK 0x00000100
|
|
#define GPIO36_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO36_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO36_INT_TYPE_OFFSET 4
|
|
#define GPIO36_INT_TYPE_MASK 0x00000070
|
|
#define GPIO36_INT_RAW_OFFSET 3
|
|
#define GPIO36_INT_RAW_MASK 0x00000008
|
|
#define GPIO36_INT_STS_OFFSET 2
|
|
#define GPIO36_INT_STS_MASK 0x00000004
|
|
#define GPIO36_INT_ENA_OFFSET 1
|
|
#define GPIO36_INT_ENA_MASK 0x00000002
|
|
#define GPIO36_INT_CLR_OFFSET 0
|
|
#define GPIO36_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO37_CFG_ADDR 0xd4
|
|
#define GPIO37_OD_MODE_OFFSET 12
|
|
#define GPIO37_OD_MODE_MASK 0x00003000
|
|
#define GPIO37_OUT_OFFSET 11
|
|
#define GPIO37_OUT_MASK 0x00000800
|
|
#define GPIO37_OE_OFFSET 10
|
|
#define GPIO37_OE_MASK 0x00000400
|
|
#define GPIO37_IE_OFFSET 9
|
|
#define GPIO37_IE_MASK 0x00000200
|
|
#define GPIO37_IN_OFFSET 8
|
|
#define GPIO37_IN_MASK 0x00000100
|
|
#define GPIO37_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO37_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO37_INT_TYPE_OFFSET 4
|
|
#define GPIO37_INT_TYPE_MASK 0x00000070
|
|
#define GPIO37_INT_RAW_OFFSET 3
|
|
#define GPIO37_INT_RAW_MASK 0x00000008
|
|
#define GPIO37_INT_STS_OFFSET 2
|
|
#define GPIO37_INT_STS_MASK 0x00000004
|
|
#define GPIO37_INT_ENA_OFFSET 1
|
|
#define GPIO37_INT_ENA_MASK 0x00000002
|
|
#define GPIO37_INT_CLR_OFFSET 0
|
|
#define GPIO37_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO38_CFG_ADDR 0xd8
|
|
#define GPIO38_OD_MODE_OFFSET 12
|
|
#define GPIO38_OD_MODE_MASK 0x00003000
|
|
#define GPIO38_OUT_OFFSET 11
|
|
#define GPIO38_OUT_MASK 0x00000800
|
|
#define GPIO38_OE_OFFSET 10
|
|
#define GPIO38_OE_MASK 0x00000400
|
|
#define GPIO38_IE_OFFSET 9
|
|
#define GPIO38_IE_MASK 0x00000200
|
|
#define GPIO38_IN_OFFSET 8
|
|
#define GPIO38_IN_MASK 0x00000100
|
|
#define GPIO38_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO38_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO38_INT_TYPE_OFFSET 4
|
|
#define GPIO38_INT_TYPE_MASK 0x00000070
|
|
#define GPIO38_INT_RAW_OFFSET 3
|
|
#define GPIO38_INT_RAW_MASK 0x00000008
|
|
#define GPIO38_INT_STS_OFFSET 2
|
|
#define GPIO38_INT_STS_MASK 0x00000004
|
|
#define GPIO38_INT_ENA_OFFSET 1
|
|
#define GPIO38_INT_ENA_MASK 0x00000002
|
|
#define GPIO38_INT_CLR_OFFSET 0
|
|
#define GPIO38_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO39_CFG_ADDR 0xdc
|
|
#define GPIO39_OD_MODE_OFFSET 12
|
|
#define GPIO39_OD_MODE_MASK 0x00003000
|
|
#define GPIO39_OUT_OFFSET 11
|
|
#define GPIO39_OUT_MASK 0x00000800
|
|
#define GPIO39_OE_OFFSET 10
|
|
#define GPIO39_OE_MASK 0x00000400
|
|
#define GPIO39_IE_OFFSET 9
|
|
#define GPIO39_IE_MASK 0x00000200
|
|
#define GPIO39_IN_OFFSET 8
|
|
#define GPIO39_IN_MASK 0x00000100
|
|
#define GPIO39_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO39_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO39_INT_TYPE_OFFSET 4
|
|
#define GPIO39_INT_TYPE_MASK 0x00000070
|
|
#define GPIO39_INT_RAW_OFFSET 3
|
|
#define GPIO39_INT_RAW_MASK 0x00000008
|
|
#define GPIO39_INT_STS_OFFSET 2
|
|
#define GPIO39_INT_STS_MASK 0x00000004
|
|
#define GPIO39_INT_ENA_OFFSET 1
|
|
#define GPIO39_INT_ENA_MASK 0x00000002
|
|
#define GPIO39_INT_CLR_OFFSET 0
|
|
#define GPIO39_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO40_CFG_ADDR 0xe0
|
|
#define GPIO40_OD_MODE_OFFSET 12
|
|
#define GPIO40_OD_MODE_MASK 0x00003000
|
|
#define GPIO40_OUT_OFFSET 11
|
|
#define GPIO40_OUT_MASK 0x00000800
|
|
#define GPIO40_OE_OFFSET 10
|
|
#define GPIO40_OE_MASK 0x00000400
|
|
#define GPIO40_IE_OFFSET 9
|
|
#define GPIO40_IE_MASK 0x00000200
|
|
#define GPIO40_IN_OFFSET 8
|
|
#define GPIO40_IN_MASK 0x00000100
|
|
#define GPIO40_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO40_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO40_INT_TYPE_OFFSET 4
|
|
#define GPIO40_INT_TYPE_MASK 0x00000070
|
|
#define GPIO40_INT_RAW_OFFSET 3
|
|
#define GPIO40_INT_RAW_MASK 0x00000008
|
|
#define GPIO40_INT_STS_OFFSET 2
|
|
#define GPIO40_INT_STS_MASK 0x00000004
|
|
#define GPIO40_INT_ENA_OFFSET 1
|
|
#define GPIO40_INT_ENA_MASK 0x00000002
|
|
#define GPIO40_INT_CLR_OFFSET 0
|
|
#define GPIO40_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO41_CFG_ADDR 0xe4
|
|
#define GPIO41_OD_MODE_OFFSET 12
|
|
#define GPIO41_OD_MODE_MASK 0x00003000
|
|
#define GPIO41_OUT_OFFSET 11
|
|
#define GPIO41_OUT_MASK 0x00000800
|
|
#define GPIO41_OE_OFFSET 10
|
|
#define GPIO41_OE_MASK 0x00000400
|
|
#define GPIO41_IE_OFFSET 9
|
|
#define GPIO41_IE_MASK 0x00000200
|
|
#define GPIO41_IN_OFFSET 8
|
|
#define GPIO41_IN_MASK 0x00000100
|
|
#define GPIO41_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO41_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO41_INT_TYPE_OFFSET 4
|
|
#define GPIO41_INT_TYPE_MASK 0x00000070
|
|
#define GPIO41_INT_RAW_OFFSET 3
|
|
#define GPIO41_INT_RAW_MASK 0x00000008
|
|
#define GPIO41_INT_STS_OFFSET 2
|
|
#define GPIO41_INT_STS_MASK 0x00000004
|
|
#define GPIO41_INT_ENA_OFFSET 1
|
|
#define GPIO41_INT_ENA_MASK 0x00000002
|
|
#define GPIO41_INT_CLR_OFFSET 0
|
|
#define GPIO41_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO42_CFG_ADDR 0xe8
|
|
#define GPIO42_OD_MODE_OFFSET 12
|
|
#define GPIO42_OD_MODE_MASK 0x00003000
|
|
#define GPIO42_OUT_OFFSET 11
|
|
#define GPIO42_OUT_MASK 0x00000800
|
|
#define GPIO42_OE_OFFSET 10
|
|
#define GPIO42_OE_MASK 0x00000400
|
|
#define GPIO42_IE_OFFSET 9
|
|
#define GPIO42_IE_MASK 0x00000200
|
|
#define GPIO42_IN_OFFSET 8
|
|
#define GPIO42_IN_MASK 0x00000100
|
|
#define GPIO42_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO42_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO42_INT_TYPE_OFFSET 4
|
|
#define GPIO42_INT_TYPE_MASK 0x00000070
|
|
#define GPIO42_INT_RAW_OFFSET 3
|
|
#define GPIO42_INT_RAW_MASK 0x00000008
|
|
#define GPIO42_INT_STS_OFFSET 2
|
|
#define GPIO42_INT_STS_MASK 0x00000004
|
|
#define GPIO42_INT_ENA_OFFSET 1
|
|
#define GPIO42_INT_ENA_MASK 0x00000002
|
|
#define GPIO42_INT_CLR_OFFSET 0
|
|
#define GPIO42_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO43_CFG_ADDR 0xec
|
|
#define GPIO43_OD_MODE_OFFSET 12
|
|
#define GPIO43_OD_MODE_MASK 0x00003000
|
|
#define GPIO43_OUT_OFFSET 11
|
|
#define GPIO43_OUT_MASK 0x00000800
|
|
#define GPIO43_OE_OFFSET 10
|
|
#define GPIO43_OE_MASK 0x00000400
|
|
#define GPIO43_IE_OFFSET 9
|
|
#define GPIO43_IE_MASK 0x00000200
|
|
#define GPIO43_IN_OFFSET 8
|
|
#define GPIO43_IN_MASK 0x00000100
|
|
#define GPIO43_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO43_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO43_INT_TYPE_OFFSET 4
|
|
#define GPIO43_INT_TYPE_MASK 0x00000070
|
|
#define GPIO43_INT_RAW_OFFSET 3
|
|
#define GPIO43_INT_RAW_MASK 0x00000008
|
|
#define GPIO43_INT_STS_OFFSET 2
|
|
#define GPIO43_INT_STS_MASK 0x00000004
|
|
#define GPIO43_INT_ENA_OFFSET 1
|
|
#define GPIO43_INT_ENA_MASK 0x00000002
|
|
#define GPIO43_INT_CLR_OFFSET 0
|
|
#define GPIO43_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO44_CFG_ADDR 0xf0
|
|
#define GPIO44_OD_MODE_OFFSET 12
|
|
#define GPIO44_OD_MODE_MASK 0x00003000
|
|
#define GPIO44_OUT_OFFSET 11
|
|
#define GPIO44_OUT_MASK 0x00000800
|
|
#define GPIO44_OE_OFFSET 10
|
|
#define GPIO44_OE_MASK 0x00000400
|
|
#define GPIO44_IE_OFFSET 9
|
|
#define GPIO44_IE_MASK 0x00000200
|
|
#define GPIO44_IN_OFFSET 8
|
|
#define GPIO44_IN_MASK 0x00000100
|
|
#define GPIO44_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO44_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO44_INT_TYPE_OFFSET 4
|
|
#define GPIO44_INT_TYPE_MASK 0x00000070
|
|
#define GPIO44_INT_RAW_OFFSET 3
|
|
#define GPIO44_INT_RAW_MASK 0x00000008
|
|
#define GPIO44_INT_STS_OFFSET 2
|
|
#define GPIO44_INT_STS_MASK 0x00000004
|
|
#define GPIO44_INT_ENA_OFFSET 1
|
|
#define GPIO44_INT_ENA_MASK 0x00000002
|
|
#define GPIO44_INT_CLR_OFFSET 0
|
|
#define GPIO44_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO45_CFG_ADDR 0xf4
|
|
#define GPIO45_OD_MODE_OFFSET 12
|
|
#define GPIO45_OD_MODE_MASK 0x00003000
|
|
#define GPIO45_OUT_OFFSET 11
|
|
#define GPIO45_OUT_MASK 0x00000800
|
|
#define GPIO45_OE_OFFSET 10
|
|
#define GPIO45_OE_MASK 0x00000400
|
|
#define GPIO45_IE_OFFSET 9
|
|
#define GPIO45_IE_MASK 0x00000200
|
|
#define GPIO45_IN_OFFSET 8
|
|
#define GPIO45_IN_MASK 0x00000100
|
|
#define GPIO45_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO45_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO45_INT_TYPE_OFFSET 4
|
|
#define GPIO45_INT_TYPE_MASK 0x00000070
|
|
#define GPIO45_INT_RAW_OFFSET 3
|
|
#define GPIO45_INT_RAW_MASK 0x00000008
|
|
#define GPIO45_INT_STS_OFFSET 2
|
|
#define GPIO45_INT_STS_MASK 0x00000004
|
|
#define GPIO45_INT_ENA_OFFSET 1
|
|
#define GPIO45_INT_ENA_MASK 0x00000002
|
|
#define GPIO45_INT_CLR_OFFSET 0
|
|
#define GPIO45_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO46_CFG_ADDR 0xf8
|
|
#define GPIO46_OD_MODE_OFFSET 12
|
|
#define GPIO46_OD_MODE_MASK 0x00003000
|
|
#define GPIO46_OUT_OFFSET 11
|
|
#define GPIO46_OUT_MASK 0x00000800
|
|
#define GPIO46_OE_OFFSET 10
|
|
#define GPIO46_OE_MASK 0x00000400
|
|
#define GPIO46_IE_OFFSET 9
|
|
#define GPIO46_IE_MASK 0x00000200
|
|
#define GPIO46_IN_OFFSET 8
|
|
#define GPIO46_IN_MASK 0x00000100
|
|
#define GPIO46_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO46_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO46_INT_TYPE_OFFSET 4
|
|
#define GPIO46_INT_TYPE_MASK 0x00000070
|
|
#define GPIO46_INT_RAW_OFFSET 3
|
|
#define GPIO46_INT_RAW_MASK 0x00000008
|
|
#define GPIO46_INT_STS_OFFSET 2
|
|
#define GPIO46_INT_STS_MASK 0x00000004
|
|
#define GPIO46_INT_ENA_OFFSET 1
|
|
#define GPIO46_INT_ENA_MASK 0x00000002
|
|
#define GPIO46_INT_CLR_OFFSET 0
|
|
#define GPIO46_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO47_CFG_ADDR 0xfc
|
|
#define GPIO47_OD_MODE_OFFSET 12
|
|
#define GPIO47_OD_MODE_MASK 0x00003000
|
|
#define GPIO47_OUT_OFFSET 11
|
|
#define GPIO47_OUT_MASK 0x00000800
|
|
#define GPIO47_OE_OFFSET 10
|
|
#define GPIO47_OE_MASK 0x00000400
|
|
#define GPIO47_IE_OFFSET 9
|
|
#define GPIO47_IE_MASK 0x00000200
|
|
#define GPIO47_IN_OFFSET 8
|
|
#define GPIO47_IN_MASK 0x00000100
|
|
#define GPIO47_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO47_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO47_INT_TYPE_OFFSET 4
|
|
#define GPIO47_INT_TYPE_MASK 0x00000070
|
|
#define GPIO47_INT_RAW_OFFSET 3
|
|
#define GPIO47_INT_RAW_MASK 0x00000008
|
|
#define GPIO47_INT_STS_OFFSET 2
|
|
#define GPIO47_INT_STS_MASK 0x00000004
|
|
#define GPIO47_INT_ENA_OFFSET 1
|
|
#define GPIO47_INT_ENA_MASK 0x00000002
|
|
#define GPIO47_INT_CLR_OFFSET 0
|
|
#define GPIO47_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO48_CFG_ADDR 0x100
|
|
#define GPIO48_OD_MODE_OFFSET 12
|
|
#define GPIO48_OD_MODE_MASK 0x00003000
|
|
#define GPIO48_OUT_OFFSET 11
|
|
#define GPIO48_OUT_MASK 0x00000800
|
|
#define GPIO48_OE_OFFSET 10
|
|
#define GPIO48_OE_MASK 0x00000400
|
|
#define GPIO48_IE_OFFSET 9
|
|
#define GPIO48_IE_MASK 0x00000200
|
|
#define GPIO48_IN_OFFSET 8
|
|
#define GPIO48_IN_MASK 0x00000100
|
|
#define GPIO48_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO48_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO48_INT_TYPE_OFFSET 4
|
|
#define GPIO48_INT_TYPE_MASK 0x00000070
|
|
#define GPIO48_INT_RAW_OFFSET 3
|
|
#define GPIO48_INT_RAW_MASK 0x00000008
|
|
#define GPIO48_INT_STS_OFFSET 2
|
|
#define GPIO48_INT_STS_MASK 0x00000004
|
|
#define GPIO48_INT_ENA_OFFSET 1
|
|
#define GPIO48_INT_ENA_MASK 0x00000002
|
|
#define GPIO48_INT_CLR_OFFSET 0
|
|
#define GPIO48_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO49_CFG_ADDR 0x104
|
|
#define GPIO49_OD_MODE_OFFSET 12
|
|
#define GPIO49_OD_MODE_MASK 0x00003000
|
|
#define GPIO49_OUT_OFFSET 11
|
|
#define GPIO49_OUT_MASK 0x00000800
|
|
#define GPIO49_OE_OFFSET 10
|
|
#define GPIO49_OE_MASK 0x00000400
|
|
#define GPIO49_IE_OFFSET 9
|
|
#define GPIO49_IE_MASK 0x00000200
|
|
#define GPIO49_IN_OFFSET 8
|
|
#define GPIO49_IN_MASK 0x00000100
|
|
#define GPIO49_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO49_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO49_INT_TYPE_OFFSET 4
|
|
#define GPIO49_INT_TYPE_MASK 0x00000070
|
|
#define GPIO49_INT_RAW_OFFSET 3
|
|
#define GPIO49_INT_RAW_MASK 0x00000008
|
|
#define GPIO49_INT_STS_OFFSET 2
|
|
#define GPIO49_INT_STS_MASK 0x00000004
|
|
#define GPIO49_INT_ENA_OFFSET 1
|
|
#define GPIO49_INT_ENA_MASK 0x00000002
|
|
#define GPIO49_INT_CLR_OFFSET 0
|
|
#define GPIO49_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO50_CFG_ADDR 0x108
|
|
#define GPIO50_OD_MODE_OFFSET 12
|
|
#define GPIO50_OD_MODE_MASK 0x00003000
|
|
#define GPIO50_OUT_OFFSET 11
|
|
#define GPIO50_OUT_MASK 0x00000800
|
|
#define GPIO50_OE_OFFSET 10
|
|
#define GPIO50_OE_MASK 0x00000400
|
|
#define GPIO50_IE_OFFSET 9
|
|
#define GPIO50_IE_MASK 0x00000200
|
|
#define GPIO50_IN_OFFSET 8
|
|
#define GPIO50_IN_MASK 0x00000100
|
|
#define GPIO50_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO50_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO50_INT_TYPE_OFFSET 4
|
|
#define GPIO50_INT_TYPE_MASK 0x00000070
|
|
#define GPIO50_INT_RAW_OFFSET 3
|
|
#define GPIO50_INT_RAW_MASK 0x00000008
|
|
#define GPIO50_INT_STS_OFFSET 2
|
|
#define GPIO50_INT_STS_MASK 0x00000004
|
|
#define GPIO50_INT_ENA_OFFSET 1
|
|
#define GPIO50_INT_ENA_MASK 0x00000002
|
|
#define GPIO50_INT_CLR_OFFSET 0
|
|
#define GPIO50_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO51_CFG_ADDR 0x10c
|
|
#define GPIO51_OD_MODE_OFFSET 12
|
|
#define GPIO51_OD_MODE_MASK 0x00003000
|
|
#define GPIO51_OUT_OFFSET 11
|
|
#define GPIO51_OUT_MASK 0x00000800
|
|
#define GPIO51_OE_OFFSET 10
|
|
#define GPIO51_OE_MASK 0x00000400
|
|
#define GPIO51_IE_OFFSET 9
|
|
#define GPIO51_IE_MASK 0x00000200
|
|
#define GPIO51_IN_OFFSET 8
|
|
#define GPIO51_IN_MASK 0x00000100
|
|
#define GPIO51_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO51_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO51_INT_TYPE_OFFSET 4
|
|
#define GPIO51_INT_TYPE_MASK 0x00000070
|
|
#define GPIO51_INT_RAW_OFFSET 3
|
|
#define GPIO51_INT_RAW_MASK 0x00000008
|
|
#define GPIO51_INT_STS_OFFSET 2
|
|
#define GPIO51_INT_STS_MASK 0x00000004
|
|
#define GPIO51_INT_ENA_OFFSET 1
|
|
#define GPIO51_INT_ENA_MASK 0x00000002
|
|
#define GPIO51_INT_CLR_OFFSET 0
|
|
#define GPIO51_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO52_CFG_ADDR 0x110
|
|
#define GPIO52_OD_MODE_OFFSET 12
|
|
#define GPIO52_OD_MODE_MASK 0x00003000
|
|
#define GPIO52_OUT_OFFSET 11
|
|
#define GPIO52_OUT_MASK 0x00000800
|
|
#define GPIO52_OE_OFFSET 10
|
|
#define GPIO52_OE_MASK 0x00000400
|
|
#define GPIO52_IE_OFFSET 9
|
|
#define GPIO52_IE_MASK 0x00000200
|
|
#define GPIO52_IN_OFFSET 8
|
|
#define GPIO52_IN_MASK 0x00000100
|
|
#define GPIO52_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO52_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO52_INT_TYPE_OFFSET 4
|
|
#define GPIO52_INT_TYPE_MASK 0x00000070
|
|
#define GPIO52_INT_RAW_OFFSET 3
|
|
#define GPIO52_INT_RAW_MASK 0x00000008
|
|
#define GPIO52_INT_STS_OFFSET 2
|
|
#define GPIO52_INT_STS_MASK 0x00000004
|
|
#define GPIO52_INT_ENA_OFFSET 1
|
|
#define GPIO52_INT_ENA_MASK 0x00000002
|
|
#define GPIO52_INT_CLR_OFFSET 0
|
|
#define GPIO52_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO53_CFG_ADDR 0x114
|
|
#define GPIO53_OD_MODE_OFFSET 12
|
|
#define GPIO53_OD_MODE_MASK 0x00003000
|
|
#define GPIO53_OUT_OFFSET 11
|
|
#define GPIO53_OUT_MASK 0x00000800
|
|
#define GPIO53_OE_OFFSET 10
|
|
#define GPIO53_OE_MASK 0x00000400
|
|
#define GPIO53_IE_OFFSET 9
|
|
#define GPIO53_IE_MASK 0x00000200
|
|
#define GPIO53_IN_OFFSET 8
|
|
#define GPIO53_IN_MASK 0x00000100
|
|
#define GPIO53_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO53_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO53_INT_TYPE_OFFSET 4
|
|
#define GPIO53_INT_TYPE_MASK 0x00000070
|
|
#define GPIO53_INT_RAW_OFFSET 3
|
|
#define GPIO53_INT_RAW_MASK 0x00000008
|
|
#define GPIO53_INT_STS_OFFSET 2
|
|
#define GPIO53_INT_STS_MASK 0x00000004
|
|
#define GPIO53_INT_ENA_OFFSET 1
|
|
#define GPIO53_INT_ENA_MASK 0x00000002
|
|
#define GPIO53_INT_CLR_OFFSET 0
|
|
#define GPIO53_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO54_CFG_ADDR 0x118
|
|
#define GPIO54_OD_MODE_OFFSET 12
|
|
#define GPIO54_OD_MODE_MASK 0x00003000
|
|
#define GPIO54_OUT_OFFSET 11
|
|
#define GPIO54_OUT_MASK 0x00000800
|
|
#define GPIO54_OE_OFFSET 10
|
|
#define GPIO54_OE_MASK 0x00000400
|
|
#define GPIO54_IE_OFFSET 9
|
|
#define GPIO54_IE_MASK 0x00000200
|
|
#define GPIO54_IN_OFFSET 8
|
|
#define GPIO54_IN_MASK 0x00000100
|
|
#define GPIO54_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO54_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO54_INT_TYPE_OFFSET 4
|
|
#define GPIO54_INT_TYPE_MASK 0x00000070
|
|
#define GPIO54_INT_RAW_OFFSET 3
|
|
#define GPIO54_INT_RAW_MASK 0x00000008
|
|
#define GPIO54_INT_STS_OFFSET 2
|
|
#define GPIO54_INT_STS_MASK 0x00000004
|
|
#define GPIO54_INT_ENA_OFFSET 1
|
|
#define GPIO54_INT_ENA_MASK 0x00000002
|
|
#define GPIO54_INT_CLR_OFFSET 0
|
|
#define GPIO54_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO55_CFG_ADDR 0x11c
|
|
#define GPIO55_OD_MODE_OFFSET 12
|
|
#define GPIO55_OD_MODE_MASK 0x00003000
|
|
#define GPIO55_OUT_OFFSET 11
|
|
#define GPIO55_OUT_MASK 0x00000800
|
|
#define GPIO55_OE_OFFSET 10
|
|
#define GPIO55_OE_MASK 0x00000400
|
|
#define GPIO55_IE_OFFSET 9
|
|
#define GPIO55_IE_MASK 0x00000200
|
|
#define GPIO55_IN_OFFSET 8
|
|
#define GPIO55_IN_MASK 0x00000100
|
|
#define GPIO55_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO55_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO55_INT_TYPE_OFFSET 4
|
|
#define GPIO55_INT_TYPE_MASK 0x00000070
|
|
#define GPIO55_INT_RAW_OFFSET 3
|
|
#define GPIO55_INT_RAW_MASK 0x00000008
|
|
#define GPIO55_INT_STS_OFFSET 2
|
|
#define GPIO55_INT_STS_MASK 0x00000004
|
|
#define GPIO55_INT_ENA_OFFSET 1
|
|
#define GPIO55_INT_ENA_MASK 0x00000002
|
|
#define GPIO55_INT_CLR_OFFSET 0
|
|
#define GPIO55_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO56_CFG_ADDR 0x120
|
|
#define GPIO56_OD_MODE_OFFSET 12
|
|
#define GPIO56_OD_MODE_MASK 0x00003000
|
|
#define GPIO56_OUT_OFFSET 11
|
|
#define GPIO56_OUT_MASK 0x00000800
|
|
#define GPIO56_OE_OFFSET 10
|
|
#define GPIO56_OE_MASK 0x00000400
|
|
#define GPIO56_IE_OFFSET 9
|
|
#define GPIO56_IE_MASK 0x00000200
|
|
#define GPIO56_IN_OFFSET 8
|
|
#define GPIO56_IN_MASK 0x00000100
|
|
#define GPIO56_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO56_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO56_INT_TYPE_OFFSET 4
|
|
#define GPIO56_INT_TYPE_MASK 0x00000070
|
|
#define GPIO56_INT_RAW_OFFSET 3
|
|
#define GPIO56_INT_RAW_MASK 0x00000008
|
|
#define GPIO56_INT_STS_OFFSET 2
|
|
#define GPIO56_INT_STS_MASK 0x00000004
|
|
#define GPIO56_INT_ENA_OFFSET 1
|
|
#define GPIO56_INT_ENA_MASK 0x00000002
|
|
#define GPIO56_INT_CLR_OFFSET 0
|
|
#define GPIO56_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO57_CFG_ADDR 0x124
|
|
#define GPIO57_OD_MODE_OFFSET 12
|
|
#define GPIO57_OD_MODE_MASK 0x00003000
|
|
#define GPIO57_OUT_OFFSET 11
|
|
#define GPIO57_OUT_MASK 0x00000800
|
|
#define GPIO57_OE_OFFSET 10
|
|
#define GPIO57_OE_MASK 0x00000400
|
|
#define GPIO57_IE_OFFSET 9
|
|
#define GPIO57_IE_MASK 0x00000200
|
|
#define GPIO57_IN_OFFSET 8
|
|
#define GPIO57_IN_MASK 0x00000100
|
|
#define GPIO57_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO57_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO57_INT_TYPE_OFFSET 4
|
|
#define GPIO57_INT_TYPE_MASK 0x00000070
|
|
#define GPIO57_INT_RAW_OFFSET 3
|
|
#define GPIO57_INT_RAW_MASK 0x00000008
|
|
#define GPIO57_INT_STS_OFFSET 2
|
|
#define GPIO57_INT_STS_MASK 0x00000004
|
|
#define GPIO57_INT_ENA_OFFSET 1
|
|
#define GPIO57_INT_ENA_MASK 0x00000002
|
|
#define GPIO57_INT_CLR_OFFSET 0
|
|
#define GPIO57_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO58_CFG_ADDR 0x128
|
|
#define GPIO58_OD_MODE_OFFSET 12
|
|
#define GPIO58_OD_MODE_MASK 0x00003000
|
|
#define GPIO58_OUT_OFFSET 11
|
|
#define GPIO58_OUT_MASK 0x00000800
|
|
#define GPIO58_OE_OFFSET 10
|
|
#define GPIO58_OE_MASK 0x00000400
|
|
#define GPIO58_IE_OFFSET 9
|
|
#define GPIO58_IE_MASK 0x00000200
|
|
#define GPIO58_IN_OFFSET 8
|
|
#define GPIO58_IN_MASK 0x00000100
|
|
#define GPIO58_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO58_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO58_INT_TYPE_OFFSET 4
|
|
#define GPIO58_INT_TYPE_MASK 0x00000070
|
|
#define GPIO58_INT_RAW_OFFSET 3
|
|
#define GPIO58_INT_RAW_MASK 0x00000008
|
|
#define GPIO58_INT_STS_OFFSET 2
|
|
#define GPIO58_INT_STS_MASK 0x00000004
|
|
#define GPIO58_INT_ENA_OFFSET 1
|
|
#define GPIO58_INT_ENA_MASK 0x00000002
|
|
#define GPIO58_INT_CLR_OFFSET 0
|
|
#define GPIO58_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO59_CFG_ADDR 0x12c
|
|
#define GPIO59_OD_MODE_OFFSET 12
|
|
#define GPIO59_OD_MODE_MASK 0x00003000
|
|
#define GPIO59_OUT_OFFSET 11
|
|
#define GPIO59_OUT_MASK 0x00000800
|
|
#define GPIO59_OE_OFFSET 10
|
|
#define GPIO59_OE_MASK 0x00000400
|
|
#define GPIO59_IE_OFFSET 9
|
|
#define GPIO59_IE_MASK 0x00000200
|
|
#define GPIO59_IN_OFFSET 8
|
|
#define GPIO59_IN_MASK 0x00000100
|
|
#define GPIO59_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO59_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO59_INT_TYPE_OFFSET 4
|
|
#define GPIO59_INT_TYPE_MASK 0x00000070
|
|
#define GPIO59_INT_RAW_OFFSET 3
|
|
#define GPIO59_INT_RAW_MASK 0x00000008
|
|
#define GPIO59_INT_STS_OFFSET 2
|
|
#define GPIO59_INT_STS_MASK 0x00000004
|
|
#define GPIO59_INT_ENA_OFFSET 1
|
|
#define GPIO59_INT_ENA_MASK 0x00000002
|
|
#define GPIO59_INT_CLR_OFFSET 0
|
|
#define GPIO59_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO60_CFG_ADDR 0x130
|
|
#define GPIO60_OD_MODE_OFFSET 12
|
|
#define GPIO60_OD_MODE_MASK 0x00003000
|
|
#define GPIO60_OUT_OFFSET 11
|
|
#define GPIO60_OUT_MASK 0x00000800
|
|
#define GPIO60_OE_OFFSET 10
|
|
#define GPIO60_OE_MASK 0x00000400
|
|
#define GPIO60_IE_OFFSET 9
|
|
#define GPIO60_IE_MASK 0x00000200
|
|
#define GPIO60_IN_OFFSET 8
|
|
#define GPIO60_IN_MASK 0x00000100
|
|
#define GPIO60_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO60_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO60_INT_TYPE_OFFSET 4
|
|
#define GPIO60_INT_TYPE_MASK 0x00000070
|
|
#define GPIO60_INT_RAW_OFFSET 3
|
|
#define GPIO60_INT_RAW_MASK 0x00000008
|
|
#define GPIO60_INT_STS_OFFSET 2
|
|
#define GPIO60_INT_STS_MASK 0x00000004
|
|
#define GPIO60_INT_ENA_OFFSET 1
|
|
#define GPIO60_INT_ENA_MASK 0x00000002
|
|
#define GPIO60_INT_CLR_OFFSET 0
|
|
#define GPIO60_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO61_CFG_ADDR 0x134
|
|
#define GPIO61_OD_MODE_OFFSET 12
|
|
#define GPIO61_OD_MODE_MASK 0x00003000
|
|
#define GPIO61_OUT_OFFSET 11
|
|
#define GPIO61_OUT_MASK 0x00000800
|
|
#define GPIO61_OE_OFFSET 10
|
|
#define GPIO61_OE_MASK 0x00000400
|
|
#define GPIO61_IE_OFFSET 9
|
|
#define GPIO61_IE_MASK 0x00000200
|
|
#define GPIO61_IN_OFFSET 8
|
|
#define GPIO61_IN_MASK 0x00000100
|
|
#define GPIO61_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO61_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO61_INT_TYPE_OFFSET 4
|
|
#define GPIO61_INT_TYPE_MASK 0x00000070
|
|
#define GPIO61_INT_RAW_OFFSET 3
|
|
#define GPIO61_INT_RAW_MASK 0x00000008
|
|
#define GPIO61_INT_STS_OFFSET 2
|
|
#define GPIO61_INT_STS_MASK 0x00000004
|
|
#define GPIO61_INT_ENA_OFFSET 1
|
|
#define GPIO61_INT_ENA_MASK 0x00000002
|
|
#define GPIO61_INT_CLR_OFFSET 0
|
|
#define GPIO61_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO62_CFG_ADDR 0x138
|
|
#define GPIO62_OD_MODE_OFFSET 12
|
|
#define GPIO62_OD_MODE_MASK 0x00003000
|
|
#define GPIO62_OUT_OFFSET 11
|
|
#define GPIO62_OUT_MASK 0x00000800
|
|
#define GPIO62_OE_OFFSET 10
|
|
#define GPIO62_OE_MASK 0x00000400
|
|
#define GPIO62_IE_OFFSET 9
|
|
#define GPIO62_IE_MASK 0x00000200
|
|
#define GPIO62_IN_OFFSET 8
|
|
#define GPIO62_IN_MASK 0x00000100
|
|
#define GPIO62_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO62_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO62_INT_TYPE_OFFSET 4
|
|
#define GPIO62_INT_TYPE_MASK 0x00000070
|
|
#define GPIO62_INT_RAW_OFFSET 3
|
|
#define GPIO62_INT_RAW_MASK 0x00000008
|
|
#define GPIO62_INT_STS_OFFSET 2
|
|
#define GPIO62_INT_STS_MASK 0x00000004
|
|
#define GPIO62_INT_ENA_OFFSET 1
|
|
#define GPIO62_INT_ENA_MASK 0x00000002
|
|
#define GPIO62_INT_CLR_OFFSET 0
|
|
#define GPIO62_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO63_CFG_ADDR 0x13c
|
|
#define GPIO63_OD_MODE_OFFSET 12
|
|
#define GPIO63_OD_MODE_MASK 0x00003000
|
|
#define GPIO63_OUT_OFFSET 11
|
|
#define GPIO63_OUT_MASK 0x00000800
|
|
#define GPIO63_OE_OFFSET 10
|
|
#define GPIO63_OE_MASK 0x00000400
|
|
#define GPIO63_IE_OFFSET 9
|
|
#define GPIO63_IE_MASK 0x00000200
|
|
#define GPIO63_IN_OFFSET 8
|
|
#define GPIO63_IN_MASK 0x00000100
|
|
#define GPIO63_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO63_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO63_INT_TYPE_OFFSET 4
|
|
#define GPIO63_INT_TYPE_MASK 0x00000070
|
|
#define GPIO63_INT_RAW_OFFSET 3
|
|
#define GPIO63_INT_RAW_MASK 0x00000008
|
|
#define GPIO63_INT_STS_OFFSET 2
|
|
#define GPIO63_INT_STS_MASK 0x00000004
|
|
#define GPIO63_INT_ENA_OFFSET 1
|
|
#define GPIO63_INT_ENA_MASK 0x00000002
|
|
#define GPIO63_INT_CLR_OFFSET 0
|
|
#define GPIO63_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO64_CFG_ADDR 0x140
|
|
#define GPIO64_OD_MODE_OFFSET 12
|
|
#define GPIO64_OD_MODE_MASK 0x00003000
|
|
#define GPIO64_OUT_OFFSET 11
|
|
#define GPIO64_OUT_MASK 0x00000800
|
|
#define GPIO64_OE_OFFSET 10
|
|
#define GPIO64_OE_MASK 0x00000400
|
|
#define GPIO64_IE_OFFSET 9
|
|
#define GPIO64_IE_MASK 0x00000200
|
|
#define GPIO64_IN_OFFSET 8
|
|
#define GPIO64_IN_MASK 0x00000100
|
|
#define GPIO64_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO64_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO64_INT_TYPE_OFFSET 4
|
|
#define GPIO64_INT_TYPE_MASK 0x00000070
|
|
#define GPIO64_INT_RAW_OFFSET 3
|
|
#define GPIO64_INT_RAW_MASK 0x00000008
|
|
#define GPIO64_INT_STS_OFFSET 2
|
|
#define GPIO64_INT_STS_MASK 0x00000004
|
|
#define GPIO64_INT_ENA_OFFSET 1
|
|
#define GPIO64_INT_ENA_MASK 0x00000002
|
|
#define GPIO64_INT_CLR_OFFSET 0
|
|
#define GPIO64_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO65_CFG_ADDR 0x144
|
|
#define GPIO65_OD_MODE_OFFSET 12
|
|
#define GPIO65_OD_MODE_MASK 0x00003000
|
|
#define GPIO65_OUT_OFFSET 11
|
|
#define GPIO65_OUT_MASK 0x00000800
|
|
#define GPIO65_OE_OFFSET 10
|
|
#define GPIO65_OE_MASK 0x00000400
|
|
#define GPIO65_IE_OFFSET 9
|
|
#define GPIO65_IE_MASK 0x00000200
|
|
#define GPIO65_IN_OFFSET 8
|
|
#define GPIO65_IN_MASK 0x00000100
|
|
#define GPIO65_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO65_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO65_INT_TYPE_OFFSET 4
|
|
#define GPIO65_INT_TYPE_MASK 0x00000070
|
|
#define GPIO65_INT_RAW_OFFSET 3
|
|
#define GPIO65_INT_RAW_MASK 0x00000008
|
|
#define GPIO65_INT_STS_OFFSET 2
|
|
#define GPIO65_INT_STS_MASK 0x00000004
|
|
#define GPIO65_INT_ENA_OFFSET 1
|
|
#define GPIO65_INT_ENA_MASK 0x00000002
|
|
#define GPIO65_INT_CLR_OFFSET 0
|
|
#define GPIO65_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO66_CFG_ADDR 0x148
|
|
#define GPIO66_OD_MODE_OFFSET 12
|
|
#define GPIO66_OD_MODE_MASK 0x00003000
|
|
#define GPIO66_OUT_OFFSET 11
|
|
#define GPIO66_OUT_MASK 0x00000800
|
|
#define GPIO66_OE_OFFSET 10
|
|
#define GPIO66_OE_MASK 0x00000400
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#define GPIO66_IE_OFFSET 9
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#define GPIO66_IE_MASK 0x00000200
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#define GPIO66_IN_OFFSET 8
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#define GPIO66_IN_MASK 0x00000100
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#define GPIO66_WAKEUP_ENA_OFFSET 7
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#define GPIO66_WAKEUP_ENA_MASK 0x00000080
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#define GPIO66_INT_TYPE_OFFSET 4
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#define GPIO66_INT_TYPE_MASK 0x00000070
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#define GPIO66_INT_RAW_OFFSET 3
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#define GPIO66_INT_RAW_MASK 0x00000008
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#define GPIO66_INT_STS_OFFSET 2
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#define GPIO66_INT_STS_MASK 0x00000004
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#define GPIO66_INT_ENA_OFFSET 1
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#define GPIO66_INT_ENA_MASK 0x00000002
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#define GPIO66_INT_CLR_OFFSET 0
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#define GPIO66_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_GPIO67_CFG_ADDR 0x14c
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#define GPIO67_OD_MODE_OFFSET 12
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#define GPIO67_OD_MODE_MASK 0x00003000
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#define GPIO67_OUT_OFFSET 11
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#define GPIO67_OUT_MASK 0x00000800
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#define GPIO67_OE_OFFSET 10
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#define GPIO67_OE_MASK 0x00000400
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#define GPIO67_IE_OFFSET 9
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#define GPIO67_IE_MASK 0x00000200
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#define GPIO67_IN_OFFSET 8
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#define GPIO67_IN_MASK 0x00000100
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#define GPIO67_WAKEUP_ENA_OFFSET 7
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#define GPIO67_WAKEUP_ENA_MASK 0x00000080
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#define GPIO67_INT_TYPE_OFFSET 4
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#define GPIO67_INT_TYPE_MASK 0x00000070
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#define GPIO67_INT_RAW_OFFSET 3
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#define GPIO67_INT_RAW_MASK 0x00000008
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#define GPIO67_INT_STS_OFFSET 2
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#define GPIO67_INT_STS_MASK 0x00000004
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#define GPIO67_INT_ENA_OFFSET 1
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#define GPIO67_INT_ENA_MASK 0x00000002
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#define GPIO67_INT_CLR_OFFSET 0
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#define GPIO67_INT_CLR_MASK 0x00000001
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|
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//-----------------------------------
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#define CFG_GPIO68_CFG_ADDR 0x150
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#define GPIO68_OD_MODE_OFFSET 12
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#define GPIO68_OD_MODE_MASK 0x00003000
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#define GPIO68_OUT_OFFSET 11
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#define GPIO68_OUT_MASK 0x00000800
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#define GPIO68_OE_OFFSET 10
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#define GPIO68_OE_MASK 0x00000400
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#define GPIO68_IE_OFFSET 9
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#define GPIO68_IE_MASK 0x00000200
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#define GPIO68_IN_OFFSET 8
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#define GPIO68_IN_MASK 0x00000100
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#define GPIO68_WAKEUP_ENA_OFFSET 7
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#define GPIO68_WAKEUP_ENA_MASK 0x00000080
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#define GPIO68_INT_TYPE_OFFSET 4
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#define GPIO68_INT_TYPE_MASK 0x00000070
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#define GPIO68_INT_RAW_OFFSET 3
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#define GPIO68_INT_RAW_MASK 0x00000008
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#define GPIO68_INT_STS_OFFSET 2
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#define GPIO68_INT_STS_MASK 0x00000004
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#define GPIO68_INT_ENA_OFFSET 1
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#define GPIO68_INT_ENA_MASK 0x00000002
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#define GPIO68_INT_CLR_OFFSET 0
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#define GPIO68_INT_CLR_MASK 0x00000001
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|
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//-----------------------------------
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#define CFG_GPIO69_CFG_ADDR 0x154
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#define GPIO69_OD_MODE_OFFSET 12
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|
#define GPIO69_OD_MODE_MASK 0x00003000
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|
#define GPIO69_OUT_OFFSET 11
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|
#define GPIO69_OUT_MASK 0x00000800
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|
#define GPIO69_OE_OFFSET 10
|
|
#define GPIO69_OE_MASK 0x00000400
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|
#define GPIO69_IE_OFFSET 9
|
|
#define GPIO69_IE_MASK 0x00000200
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#define GPIO69_IN_OFFSET 8
|
|
#define GPIO69_IN_MASK 0x00000100
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|
#define GPIO69_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO69_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO69_INT_TYPE_OFFSET 4
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|
#define GPIO69_INT_TYPE_MASK 0x00000070
|
|
#define GPIO69_INT_RAW_OFFSET 3
|
|
#define GPIO69_INT_RAW_MASK 0x00000008
|
|
#define GPIO69_INT_STS_OFFSET 2
|
|
#define GPIO69_INT_STS_MASK 0x00000004
|
|
#define GPIO69_INT_ENA_OFFSET 1
|
|
#define GPIO69_INT_ENA_MASK 0x00000002
|
|
#define GPIO69_INT_CLR_OFFSET 0
|
|
#define GPIO69_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
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|
#define CFG_GPIO70_CFG_ADDR 0x158
|
|
#define GPIO70_OD_MODE_OFFSET 12
|
|
#define GPIO70_OD_MODE_MASK 0x00003000
|
|
#define GPIO70_OUT_OFFSET 11
|
|
#define GPIO70_OUT_MASK 0x00000800
|
|
#define GPIO70_OE_OFFSET 10
|
|
#define GPIO70_OE_MASK 0x00000400
|
|
#define GPIO70_IE_OFFSET 9
|
|
#define GPIO70_IE_MASK 0x00000200
|
|
#define GPIO70_IN_OFFSET 8
|
|
#define GPIO70_IN_MASK 0x00000100
|
|
#define GPIO70_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO70_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO70_INT_TYPE_OFFSET 4
|
|
#define GPIO70_INT_TYPE_MASK 0x00000070
|
|
#define GPIO70_INT_RAW_OFFSET 3
|
|
#define GPIO70_INT_RAW_MASK 0x00000008
|
|
#define GPIO70_INT_STS_OFFSET 2
|
|
#define GPIO70_INT_STS_MASK 0x00000004
|
|
#define GPIO70_INT_ENA_OFFSET 1
|
|
#define GPIO70_INT_ENA_MASK 0x00000002
|
|
#define GPIO70_INT_CLR_OFFSET 0
|
|
#define GPIO70_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO71_CFG_ADDR 0x15c
|
|
#define GPIO71_OD_MODE_OFFSET 12
|
|
#define GPIO71_OD_MODE_MASK 0x00003000
|
|
#define GPIO71_OUT_OFFSET 11
|
|
#define GPIO71_OUT_MASK 0x00000800
|
|
#define GPIO71_OE_OFFSET 10
|
|
#define GPIO71_OE_MASK 0x00000400
|
|
#define GPIO71_IE_OFFSET 9
|
|
#define GPIO71_IE_MASK 0x00000200
|
|
#define GPIO71_IN_OFFSET 8
|
|
#define GPIO71_IN_MASK 0x00000100
|
|
#define GPIO71_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO71_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO71_INT_TYPE_OFFSET 4
|
|
#define GPIO71_INT_TYPE_MASK 0x00000070
|
|
#define GPIO71_INT_RAW_OFFSET 3
|
|
#define GPIO71_INT_RAW_MASK 0x00000008
|
|
#define GPIO71_INT_STS_OFFSET 2
|
|
#define GPIO71_INT_STS_MASK 0x00000004
|
|
#define GPIO71_INT_ENA_OFFSET 1
|
|
#define GPIO71_INT_ENA_MASK 0x00000002
|
|
#define GPIO71_INT_CLR_OFFSET 0
|
|
#define GPIO71_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO72_CFG_ADDR 0x160
|
|
#define GPIO72_OD_MODE_OFFSET 12
|
|
#define GPIO72_OD_MODE_MASK 0x00003000
|
|
#define GPIO72_OUT_OFFSET 11
|
|
#define GPIO72_OUT_MASK 0x00000800
|
|
#define GPIO72_OE_OFFSET 10
|
|
#define GPIO72_OE_MASK 0x00000400
|
|
#define GPIO72_IE_OFFSET 9
|
|
#define GPIO72_IE_MASK 0x00000200
|
|
#define GPIO72_IN_OFFSET 8
|
|
#define GPIO72_IN_MASK 0x00000100
|
|
#define GPIO72_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO72_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO72_INT_TYPE_OFFSET 4
|
|
#define GPIO72_INT_TYPE_MASK 0x00000070
|
|
#define GPIO72_INT_RAW_OFFSET 3
|
|
#define GPIO72_INT_RAW_MASK 0x00000008
|
|
#define GPIO72_INT_STS_OFFSET 2
|
|
#define GPIO72_INT_STS_MASK 0x00000004
|
|
#define GPIO72_INT_ENA_OFFSET 1
|
|
#define GPIO72_INT_ENA_MASK 0x00000002
|
|
#define GPIO72_INT_CLR_OFFSET 0
|
|
#define GPIO72_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIO73_CFG_ADDR 0x164
|
|
#define GPIO73_OD_MODE_OFFSET 12
|
|
#define GPIO73_OD_MODE_MASK 0x00003000
|
|
#define GPIO73_OUT_OFFSET 11
|
|
#define GPIO73_OUT_MASK 0x00000800
|
|
#define GPIO73_OE_OFFSET 10
|
|
#define GPIO73_OE_MASK 0x00000400
|
|
#define GPIO73_IE_OFFSET 9
|
|
#define GPIO73_IE_MASK 0x00000200
|
|
#define GPIO73_IN_OFFSET 8
|
|
#define GPIO73_IN_MASK 0x00000100
|
|
#define GPIO73_WAKEUP_ENA_OFFSET 7
|
|
#define GPIO73_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIO73_INT_TYPE_OFFSET 4
|
|
#define GPIO73_INT_TYPE_MASK 0x00000070
|
|
#define GPIO73_INT_RAW_OFFSET 3
|
|
#define GPIO73_INT_RAW_MASK 0x00000008
|
|
#define GPIO73_INT_STS_OFFSET 2
|
|
#define GPIO73_INT_STS_MASK 0x00000004
|
|
#define GPIO73_INT_ENA_OFFSET 1
|
|
#define GPIO73_INT_ENA_MASK 0x00000002
|
|
#define GPIO73_INT_CLR_OFFSET 0
|
|
#define GPIO73_INT_CLR_MASK 0x00000001
|
|
|
|
//HW module read/write macro
|
|
#define GPIO_READ_REG(addr) SOC_READ_REG(GPIO_BASEADDR + addr)
|
|
#define GPIO_WRITE_REG(addr,value) SOC_WRITE_REG(GPIO_BASEADDR + addr,value)
|