420 lines
14 KiB
C
420 lines
14 KiB
C
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT0_ENA0_ADDR 0x0
|
|
#define GPIOA_INT0_ENA0_OFFSET 0
|
|
#define GPIOA_INT0_ENA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT0_ENA1_ADDR 0x4
|
|
#define GPIOA_INT0_ENA1_OFFSET 0
|
|
#define GPIOA_INT0_ENA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT1_ENA0_ADDR 0x8
|
|
#define GPIOA_INT1_ENA0_OFFSET 0
|
|
#define GPIOA_INT1_ENA0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT1_ENA1_ADDR 0xc
|
|
#define GPIOA_INT1_ENA1_OFFSET 0
|
|
#define GPIOA_INT1_ENA1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT0_STS0_ADDR 0x10
|
|
#define GPIOA_INT0_STS0_OFFSET 0
|
|
#define GPIOA_INT0_STS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT0_STS1_ADDR 0x14
|
|
#define GPIOA_INT0_STS1_OFFSET 0
|
|
#define GPIOA_INT0_STS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT1_STS0_ADDR 0x18
|
|
#define GPIOA_INT1_STS0_OFFSET 0
|
|
#define GPIOA_INT1_STS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA_INT1_STS1_ADDR 0x1c
|
|
#define GPIOA_INT1_STS1_OFFSET 0
|
|
#define GPIOA_INT1_STS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA0_CFG_ADDR 0x20
|
|
#define GPIOA0_OD_MODE_OFFSET 12
|
|
#define GPIOA0_OD_MODE_MASK 0x00003000
|
|
#define GPIOA0_OUT_OFFSET 11
|
|
#define GPIOA0_OUT_MASK 0x00000800
|
|
#define GPIOA0_OE_OFFSET 10
|
|
#define GPIOA0_OE_MASK 0x00000400
|
|
#define GPIOA0_IE_OFFSET 9
|
|
#define GPIOA0_IE_MASK 0x00000200
|
|
#define GPIOA0_IN_OFFSET 8
|
|
#define GPIOA0_IN_MASK 0x00000100
|
|
#define GPIOA0_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA0_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA0_INT_TYPE_OFFSET 4
|
|
#define GPIOA0_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA0_INT_RAW_OFFSET 3
|
|
#define GPIOA0_INT_RAW_MASK 0x00000008
|
|
#define GPIOA0_INT_STS_OFFSET 2
|
|
#define GPIOA0_INT_STS_MASK 0x00000004
|
|
#define GPIOA0_INT_ENA_OFFSET 1
|
|
#define GPIOA0_INT_ENA_MASK 0x00000002
|
|
#define GPIOA0_INT_CLR_OFFSET 0
|
|
#define GPIOA0_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA1_CFG_ADDR 0x24
|
|
#define GPIOA1_OD_MODE_OFFSET 12
|
|
#define GPIOA1_OD_MODE_MASK 0x00003000
|
|
#define GPIOA1_OUT_OFFSET 11
|
|
#define GPIOA1_OUT_MASK 0x00000800
|
|
#define GPIOA1_OE_OFFSET 10
|
|
#define GPIOA1_OE_MASK 0x00000400
|
|
#define GPIOA1_IE_OFFSET 9
|
|
#define GPIOA1_IE_MASK 0x00000200
|
|
#define GPIOA1_IN_OFFSET 8
|
|
#define GPIOA1_IN_MASK 0x00000100
|
|
#define GPIOA1_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA1_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA1_INT_TYPE_OFFSET 4
|
|
#define GPIOA1_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA1_INT_RAW_OFFSET 3
|
|
#define GPIOA1_INT_RAW_MASK 0x00000008
|
|
#define GPIOA1_INT_STS_OFFSET 2
|
|
#define GPIOA1_INT_STS_MASK 0x00000004
|
|
#define GPIOA1_INT_ENA_OFFSET 1
|
|
#define GPIOA1_INT_ENA_MASK 0x00000002
|
|
#define GPIOA1_INT_CLR_OFFSET 0
|
|
#define GPIOA1_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA2_CFG_ADDR 0x28
|
|
#define GPIOA2_OD_MODE_OFFSET 12
|
|
#define GPIOA2_OD_MODE_MASK 0x00003000
|
|
#define GPIOA2_OUT_OFFSET 11
|
|
#define GPIOA2_OUT_MASK 0x00000800
|
|
#define GPIOA2_OE_OFFSET 10
|
|
#define GPIOA2_OE_MASK 0x00000400
|
|
#define GPIOA2_IE_OFFSET 9
|
|
#define GPIOA2_IE_MASK 0x00000200
|
|
#define GPIOA2_IN_OFFSET 8
|
|
#define GPIOA2_IN_MASK 0x00000100
|
|
#define GPIOA2_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA2_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA2_INT_TYPE_OFFSET 4
|
|
#define GPIOA2_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA2_INT_RAW_OFFSET 3
|
|
#define GPIOA2_INT_RAW_MASK 0x00000008
|
|
#define GPIOA2_INT_STS_OFFSET 2
|
|
#define GPIOA2_INT_STS_MASK 0x00000004
|
|
#define GPIOA2_INT_ENA_OFFSET 1
|
|
#define GPIOA2_INT_ENA_MASK 0x00000002
|
|
#define GPIOA2_INT_CLR_OFFSET 0
|
|
#define GPIOA2_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA3_CFG_ADDR 0x2c
|
|
#define GPIOA3_OD_MODE_OFFSET 12
|
|
#define GPIOA3_OD_MODE_MASK 0x00003000
|
|
#define GPIOA3_OUT_OFFSET 11
|
|
#define GPIOA3_OUT_MASK 0x00000800
|
|
#define GPIOA3_OE_OFFSET 10
|
|
#define GPIOA3_OE_MASK 0x00000400
|
|
#define GPIOA3_IE_OFFSET 9
|
|
#define GPIOA3_IE_MASK 0x00000200
|
|
#define GPIOA3_IN_OFFSET 8
|
|
#define GPIOA3_IN_MASK 0x00000100
|
|
#define GPIOA3_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA3_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA3_INT_TYPE_OFFSET 4
|
|
#define GPIOA3_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA3_INT_RAW_OFFSET 3
|
|
#define GPIOA3_INT_RAW_MASK 0x00000008
|
|
#define GPIOA3_INT_STS_OFFSET 2
|
|
#define GPIOA3_INT_STS_MASK 0x00000004
|
|
#define GPIOA3_INT_ENA_OFFSET 1
|
|
#define GPIOA3_INT_ENA_MASK 0x00000002
|
|
#define GPIOA3_INT_CLR_OFFSET 0
|
|
#define GPIOA3_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA4_CFG_ADDR 0x30
|
|
#define GPIOA4_OD_MODE_OFFSET 12
|
|
#define GPIOA4_OD_MODE_MASK 0x00003000
|
|
#define GPIOA4_OUT_OFFSET 11
|
|
#define GPIOA4_OUT_MASK 0x00000800
|
|
#define GPIOA4_OE_OFFSET 10
|
|
#define GPIOA4_OE_MASK 0x00000400
|
|
#define GPIOA4_IE_OFFSET 9
|
|
#define GPIOA4_IE_MASK 0x00000200
|
|
#define GPIOA4_IN_OFFSET 8
|
|
#define GPIOA4_IN_MASK 0x00000100
|
|
#define GPIOA4_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA4_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA4_INT_TYPE_OFFSET 4
|
|
#define GPIOA4_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA4_INT_RAW_OFFSET 3
|
|
#define GPIOA4_INT_RAW_MASK 0x00000008
|
|
#define GPIOA4_INT_STS_OFFSET 2
|
|
#define GPIOA4_INT_STS_MASK 0x00000004
|
|
#define GPIOA4_INT_ENA_OFFSET 1
|
|
#define GPIOA4_INT_ENA_MASK 0x00000002
|
|
#define GPIOA4_INT_CLR_OFFSET 0
|
|
#define GPIOA4_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA5_CFG_ADDR 0x34
|
|
#define GPIOA5_OD_MODE_OFFSET 12
|
|
#define GPIOA5_OD_MODE_MASK 0x00003000
|
|
#define GPIOA5_OUT_OFFSET 11
|
|
#define GPIOA5_OUT_MASK 0x00000800
|
|
#define GPIOA5_OE_OFFSET 10
|
|
#define GPIOA5_OE_MASK 0x00000400
|
|
#define GPIOA5_IE_OFFSET 9
|
|
#define GPIOA5_IE_MASK 0x00000200
|
|
#define GPIOA5_IN_OFFSET 8
|
|
#define GPIOA5_IN_MASK 0x00000100
|
|
#define GPIOA5_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA5_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA5_INT_TYPE_OFFSET 4
|
|
#define GPIOA5_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA5_INT_RAW_OFFSET 3
|
|
#define GPIOA5_INT_RAW_MASK 0x00000008
|
|
#define GPIOA5_INT_STS_OFFSET 2
|
|
#define GPIOA5_INT_STS_MASK 0x00000004
|
|
#define GPIOA5_INT_ENA_OFFSET 1
|
|
#define GPIOA5_INT_ENA_MASK 0x00000002
|
|
#define GPIOA5_INT_CLR_OFFSET 0
|
|
#define GPIOA5_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA6_CFG_ADDR 0x38
|
|
#define GPIOA6_OD_MODE_OFFSET 12
|
|
#define GPIOA6_OD_MODE_MASK 0x00003000
|
|
#define GPIOA6_OUT_OFFSET 11
|
|
#define GPIOA6_OUT_MASK 0x00000800
|
|
#define GPIOA6_OE_OFFSET 10
|
|
#define GPIOA6_OE_MASK 0x00000400
|
|
#define GPIOA6_IE_OFFSET 9
|
|
#define GPIOA6_IE_MASK 0x00000200
|
|
#define GPIOA6_IN_OFFSET 8
|
|
#define GPIOA6_IN_MASK 0x00000100
|
|
#define GPIOA6_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA6_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA6_INT_TYPE_OFFSET 4
|
|
#define GPIOA6_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA6_INT_RAW_OFFSET 3
|
|
#define GPIOA6_INT_RAW_MASK 0x00000008
|
|
#define GPIOA6_INT_STS_OFFSET 2
|
|
#define GPIOA6_INT_STS_MASK 0x00000004
|
|
#define GPIOA6_INT_ENA_OFFSET 1
|
|
#define GPIOA6_INT_ENA_MASK 0x00000002
|
|
#define GPIOA6_INT_CLR_OFFSET 0
|
|
#define GPIOA6_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA7_CFG_ADDR 0x3c
|
|
#define GPIOA7_OD_MODE_OFFSET 12
|
|
#define GPIOA7_OD_MODE_MASK 0x00003000
|
|
#define GPIOA7_OUT_OFFSET 11
|
|
#define GPIOA7_OUT_MASK 0x00000800
|
|
#define GPIOA7_OE_OFFSET 10
|
|
#define GPIOA7_OE_MASK 0x00000400
|
|
#define GPIOA7_IE_OFFSET 9
|
|
#define GPIOA7_IE_MASK 0x00000200
|
|
#define GPIOA7_IN_OFFSET 8
|
|
#define GPIOA7_IN_MASK 0x00000100
|
|
#define GPIOA7_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA7_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA7_INT_TYPE_OFFSET 4
|
|
#define GPIOA7_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA7_INT_RAW_OFFSET 3
|
|
#define GPIOA7_INT_RAW_MASK 0x00000008
|
|
#define GPIOA7_INT_STS_OFFSET 2
|
|
#define GPIOA7_INT_STS_MASK 0x00000004
|
|
#define GPIOA7_INT_ENA_OFFSET 1
|
|
#define GPIOA7_INT_ENA_MASK 0x00000002
|
|
#define GPIOA7_INT_CLR_OFFSET 0
|
|
#define GPIOA7_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA8_CFG_ADDR 0x40
|
|
#define GPIOA8_OD_MODE_OFFSET 12
|
|
#define GPIOA8_OD_MODE_MASK 0x00003000
|
|
#define GPIOA8_OUT_OFFSET 11
|
|
#define GPIOA8_OUT_MASK 0x00000800
|
|
#define GPIOA8_OE_OFFSET 10
|
|
#define GPIOA8_OE_MASK 0x00000400
|
|
#define GPIOA8_IE_OFFSET 9
|
|
#define GPIOA8_IE_MASK 0x00000200
|
|
#define GPIOA8_IN_OFFSET 8
|
|
#define GPIOA8_IN_MASK 0x00000100
|
|
#define GPIOA8_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA8_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA8_INT_TYPE_OFFSET 4
|
|
#define GPIOA8_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA8_INT_RAW_OFFSET 3
|
|
#define GPIOA8_INT_RAW_MASK 0x00000008
|
|
#define GPIOA8_INT_STS_OFFSET 2
|
|
#define GPIOA8_INT_STS_MASK 0x00000004
|
|
#define GPIOA8_INT_ENA_OFFSET 1
|
|
#define GPIOA8_INT_ENA_MASK 0x00000002
|
|
#define GPIOA8_INT_CLR_OFFSET 0
|
|
#define GPIOA8_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA9_CFG_ADDR 0x44
|
|
#define GPIOA9_OD_MODE_OFFSET 12
|
|
#define GPIOA9_OD_MODE_MASK 0x00003000
|
|
#define GPIOA9_OUT_OFFSET 11
|
|
#define GPIOA9_OUT_MASK 0x00000800
|
|
#define GPIOA9_OE_OFFSET 10
|
|
#define GPIOA9_OE_MASK 0x00000400
|
|
#define GPIOA9_IE_OFFSET 9
|
|
#define GPIOA9_IE_MASK 0x00000200
|
|
#define GPIOA9_IN_OFFSET 8
|
|
#define GPIOA9_IN_MASK 0x00000100
|
|
#define GPIOA9_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA9_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA9_INT_TYPE_OFFSET 4
|
|
#define GPIOA9_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA9_INT_RAW_OFFSET 3
|
|
#define GPIOA9_INT_RAW_MASK 0x00000008
|
|
#define GPIOA9_INT_STS_OFFSET 2
|
|
#define GPIOA9_INT_STS_MASK 0x00000004
|
|
#define GPIOA9_INT_ENA_OFFSET 1
|
|
#define GPIOA9_INT_ENA_MASK 0x00000002
|
|
#define GPIOA9_INT_CLR_OFFSET 0
|
|
#define GPIOA9_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA10_CFG_ADDR 0x48
|
|
#define GPIOA10_OD_MODE_OFFSET 12
|
|
#define GPIOA10_OD_MODE_MASK 0x00003000
|
|
#define GPIOA10_OUT_OFFSET 11
|
|
#define GPIOA10_OUT_MASK 0x00000800
|
|
#define GPIOA10_OE_OFFSET 10
|
|
#define GPIOA10_OE_MASK 0x00000400
|
|
#define GPIOA10_IE_OFFSET 9
|
|
#define GPIOA10_IE_MASK 0x00000200
|
|
#define GPIOA10_IN_OFFSET 8
|
|
#define GPIOA10_IN_MASK 0x00000100
|
|
#define GPIOA10_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA10_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA10_INT_TYPE_OFFSET 4
|
|
#define GPIOA10_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA10_INT_RAW_OFFSET 3
|
|
#define GPIOA10_INT_RAW_MASK 0x00000008
|
|
#define GPIOA10_INT_STS_OFFSET 2
|
|
#define GPIOA10_INT_STS_MASK 0x00000004
|
|
#define GPIOA10_INT_ENA_OFFSET 1
|
|
#define GPIOA10_INT_ENA_MASK 0x00000002
|
|
#define GPIOA10_INT_CLR_OFFSET 0
|
|
#define GPIOA10_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA11_CFG_ADDR 0x4c
|
|
#define GPIOA11_OD_MODE_OFFSET 12
|
|
#define GPIOA11_OD_MODE_MASK 0x00003000
|
|
#define GPIOA11_OUT_OFFSET 11
|
|
#define GPIOA11_OUT_MASK 0x00000800
|
|
#define GPIOA11_OE_OFFSET 10
|
|
#define GPIOA11_OE_MASK 0x00000400
|
|
#define GPIOA11_IE_OFFSET 9
|
|
#define GPIOA11_IE_MASK 0x00000200
|
|
#define GPIOA11_IN_OFFSET 8
|
|
#define GPIOA11_IN_MASK 0x00000100
|
|
#define GPIOA11_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA11_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA11_INT_TYPE_OFFSET 4
|
|
#define GPIOA11_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA11_INT_RAW_OFFSET 3
|
|
#define GPIOA11_INT_RAW_MASK 0x00000008
|
|
#define GPIOA11_INT_STS_OFFSET 2
|
|
#define GPIOA11_INT_STS_MASK 0x00000004
|
|
#define GPIOA11_INT_ENA_OFFSET 1
|
|
#define GPIOA11_INT_ENA_MASK 0x00000002
|
|
#define GPIOA11_INT_CLR_OFFSET 0
|
|
#define GPIOA11_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA12_CFG_ADDR 0x50
|
|
#define GPIOA12_OD_MODE_OFFSET 12
|
|
#define GPIOA12_OD_MODE_MASK 0x00003000
|
|
#define GPIOA12_OUT_OFFSET 11
|
|
#define GPIOA12_OUT_MASK 0x00000800
|
|
#define GPIOA12_OE_OFFSET 10
|
|
#define GPIOA12_OE_MASK 0x00000400
|
|
#define GPIOA12_IE_OFFSET 9
|
|
#define GPIOA12_IE_MASK 0x00000200
|
|
#define GPIOA12_IN_OFFSET 8
|
|
#define GPIOA12_IN_MASK 0x00000100
|
|
#define GPIOA12_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA12_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA12_INT_TYPE_OFFSET 4
|
|
#define GPIOA12_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA12_INT_RAW_OFFSET 3
|
|
#define GPIOA12_INT_RAW_MASK 0x00000008
|
|
#define GPIOA12_INT_STS_OFFSET 2
|
|
#define GPIOA12_INT_STS_MASK 0x00000004
|
|
#define GPIOA12_INT_ENA_OFFSET 1
|
|
#define GPIOA12_INT_ENA_MASK 0x00000002
|
|
#define GPIOA12_INT_CLR_OFFSET 0
|
|
#define GPIOA12_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA13_CFG_ADDR 0x54
|
|
#define GPIOA13_OD_MODE_OFFSET 12
|
|
#define GPIOA13_OD_MODE_MASK 0x00003000
|
|
#define GPIOA13_OUT_OFFSET 11
|
|
#define GPIOA13_OUT_MASK 0x00000800
|
|
#define GPIOA13_OE_OFFSET 10
|
|
#define GPIOA13_OE_MASK 0x00000400
|
|
#define GPIOA13_IE_OFFSET 9
|
|
#define GPIOA13_IE_MASK 0x00000200
|
|
#define GPIOA13_IN_OFFSET 8
|
|
#define GPIOA13_IN_MASK 0x00000100
|
|
#define GPIOA13_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA13_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA13_INT_TYPE_OFFSET 4
|
|
#define GPIOA13_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA13_INT_RAW_OFFSET 3
|
|
#define GPIOA13_INT_RAW_MASK 0x00000008
|
|
#define GPIOA13_INT_STS_OFFSET 2
|
|
#define GPIOA13_INT_STS_MASK 0x00000004
|
|
#define GPIOA13_INT_ENA_OFFSET 1
|
|
#define GPIOA13_INT_ENA_MASK 0x00000002
|
|
#define GPIOA13_INT_CLR_OFFSET 0
|
|
#define GPIOA13_INT_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_GPIOA14_CFG_ADDR 0x58
|
|
#define GPIOA14_OD_MODE_OFFSET 12
|
|
#define GPIOA14_OD_MODE_MASK 0x00003000
|
|
#define GPIOA14_OUT_OFFSET 11
|
|
#define GPIOA14_OUT_MASK 0x00000800
|
|
#define GPIOA14_OE_OFFSET 10
|
|
#define GPIOA14_OE_MASK 0x00000400
|
|
#define GPIOA14_IE_OFFSET 9
|
|
#define GPIOA14_IE_MASK 0x00000200
|
|
#define GPIOA14_IN_OFFSET 8
|
|
#define GPIOA14_IN_MASK 0x00000100
|
|
#define GPIOA14_WAKEUP_ENA_OFFSET 7
|
|
#define GPIOA14_WAKEUP_ENA_MASK 0x00000080
|
|
#define GPIOA14_INT_TYPE_OFFSET 4
|
|
#define GPIOA14_INT_TYPE_MASK 0x00000070
|
|
#define GPIOA14_INT_RAW_OFFSET 3
|
|
#define GPIOA14_INT_RAW_MASK 0x00000008
|
|
#define GPIOA14_INT_STS_OFFSET 2
|
|
#define GPIOA14_INT_STS_MASK 0x00000004
|
|
#define GPIOA14_INT_ENA_OFFSET 1
|
|
#define GPIOA14_INT_ENA_MASK 0x00000002
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#define GPIOA14_INT_CLR_OFFSET 0
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#define GPIOA14_INT_CLR_MASK 0x00000001
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//HW module read/write macro
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#define GPIOA_READ_REG(addr) SOC_READ_REG(GPIOA_BASEADDR + addr)
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#define GPIOA_WRITE_REG(addr,value) SOC_WRITE_REG(GPIOA_BASEADDR + addr,value)
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