3345 lines
120 KiB
C
Executable File
3345 lines
120 KiB
C
Executable File
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//-----------------------------------
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#define CFG_BB_CLOCK_CTRL_ADDR 0x0000
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#define SW_SYMB_DET_ICG_EN_OFFSET 19
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#define SW_SYMB_DET_ICG_EN_MASK 0x00080000
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#define SW_CH_EST_ICG_EN_OFFSET 18
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#define SW_CH_EST_ICG_EN_MASK 0x00040000
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#define SW_CH_EQU_ICG_EN_OFFSET 17
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#define SW_CH_EQU_ICG_EN_MASK 0x00020000
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#define SW_DCFB_ICG_EN_OFFSET 16
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#define SW_DCFB_ICG_EN_MASK 0x00010000
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#define SW_CLK_EN_ANF2_OFFSET 15
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#define SW_CLK_EN_ANF2_MASK 0x00008000
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#define SW_CLK_EN_ANF1_OFFSET 14
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#define SW_CLK_EN_ANF1_MASK 0x00004000
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#define SW_CLK_EN_FNF2_OFFSET 13
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#define SW_CLK_EN_FNF2_MASK 0x00002000
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#define SW_CLK_EN_FNF1_OFFSET 12
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#define SW_CLK_EN_FNF1_MASK 0x00001000
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#define SW_CLK_EN_PHY_REG_WRAP_OFFSET 11
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#define SW_CLK_EN_PHY_REG_WRAP_MASK 0x00000800
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#define SW_CLK_EN_FC_PARSE_OFFSET 10
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#define SW_CLK_EN_FC_PARSE_MASK 0x00000400
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#define SW_CLK_EN_DFE_RX_OFFSET 9
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#define SW_CLK_EN_DFE_RX_MASK 0x00000200
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#define SW_CLK_EN_DFE_TX_OFFSET 8
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#define SW_CLK_EN_DFE_TX_MASK 0x00000100
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#define SW_MEM_FORCE_ON_OFFSET 7
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#define SW_MEM_FORCE_ON_MASK 0x00000080
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#define SW_CLK_EN_TD_RX_OFFSET 6
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#define SW_CLK_EN_TD_RX_MASK 0x00000040
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#define SW_CLK_EN_TD_TX_OFFSET 5
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#define SW_CLK_EN_TD_TX_MASK 0x00000020
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#define SW_CLK_EN_FFT_OFFSET 4
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#define SW_CLK_EN_FFT_MASK 0x00000010
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#define SW_CLK_EN_RX_FEC_OFFSET 3
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#define SW_CLK_EN_RX_FEC_MASK 0x00000008
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#define SW_CLK_EN_TX_FEC_OFFSET 2
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#define SW_CLK_EN_TX_FEC_MASK 0x00000004
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#define SW_CLK_EN_TURBO_DEC_OFFSET 1
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#define SW_CLK_EN_TURBO_DEC_MASK 0x00000002
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#define SW_CLK_EN_TURBO_ENC_OFFSET 0
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#define SW_CLK_EN_TURBO_ENC_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RESET_CTRL_ADDR 0x0004
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#define SW_ARST_TD_RX_OFFSET 6
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#define SW_ARST_TD_RX_MASK 0x00000040
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#define SW_ARST_TD_TX_OFFSET 5
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#define SW_ARST_TD_TX_MASK 0x00000020
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#define SW_ARST_FFT_OFFSET 4
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#define SW_ARST_FFT_MASK 0x00000010
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#define SW_ARST_RX_FEC_OFFSET 3
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#define SW_ARST_RX_FEC_MASK 0x00000008
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#define SW_ARST_TX_FEC_OFFSET 2
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#define SW_ARST_TX_FEC_MASK 0x00000004
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#define SW_ARST_TURBO_DEC_OFFSET 1
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#define SW_ARST_TURBO_DEC_MASK 0x00000002
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#define SW_ARST_TURBO_ENC_OFFSET 0
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#define SW_ARST_TURBO_ENC_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RTL_VERSION_ADDR 0x0008
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#define BB_RTL_VERSION_OFFSET 0
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#define BB_RTL_VERSION_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_FD_CLK_SEL_ADDR 0x000c
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#define SW_FD_FREQ_SEL_OFFSET 0
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#define SW_FD_FREQ_SEL_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_VERSION_ADDR 0x0010
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#define BOND_G3_ENA_OFFSET 6
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#define BOND_G3_ENA_MASK 0x00000040
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#define BOND_GD_SG_ENA_OFFSET 5
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#define BOND_GD_SG_ENA_MASK 0x00000020
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#define BOND_NEW_SG_ENA_OFFSET 4
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#define BOND_NEW_SG_ENA_MASK 0x00000010
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#define BOND_GREEN_PHY_ENA_OFFSET 3
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#define BOND_GREEN_PHY_ENA_MASK 0x00000008
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#define SW_BB_VERSION_OFFSET 0
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#define SW_BB_VERSION_MASK 0x00000007
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//-----------------------------------
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#define CFG_BB_PRE_CFG_ADDR 0x0014
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#define SW_TX_PRS_PRE_NUM_OFFSET 24
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#define SW_TX_PRS_PRE_NUM_MASK 0xFF000000
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#define SW_TX_PRE_NUM_OFFSET 16
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#define SW_TX_PRE_NUM_MASK 0x00FF0000
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#define SW_TX_PRE_AMP_OFFSET 5
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#define SW_TX_PRE_AMP_MASK 0x000001E0
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#define SW_PRE_REF_PHASE_OFFSET 2
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#define SW_PRE_REF_PHASE_MASK 0x0000001C
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#define SW_TX_PRE_MODE_OFFSET 0
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#define SW_TX_PRE_MODE_MASK 0x00000003
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//-----------------------------------
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#define CFG_BB_PLD_CFG_ADDR 0x0018
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#define SW_RX_TONE_MAP_PB_NUM_MAX_EN_OFFSET 21
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#define SW_RX_TONE_MAP_PB_NUM_MAX_EN_MASK 0x00200000
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#define SW_AV_HIGH_SPEED_CODE_RATE_USE_OFFSET 20
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#define SW_AV_HIGH_SPEED_CODE_RATE_USE_MASK 0x00100000
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#define SW_RX_TURBO_SOFT_BIT_WIDTH_OFFSET 18
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#define SW_RX_TURBO_SOFT_BIT_WIDTH_MASK 0x000C0000
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#define SW_RX_TURBO_DEC_LOOP_OFFSET 16
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#define SW_RX_TURBO_DEC_LOOP_MASK 0x00030000
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#define SW_AV_HIGH_SPEED_GI_X_OFFSET 14
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#define SW_AV_HIGH_SPEED_GI_X_MASK 0x0000C000
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#define SW_AV_HIGH_SPEED_CODE_RATE_OFFSET 12
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#define SW_AV_HIGH_SPEED_CODE_RATE_MASK 0x00003000
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#define SW_CI_HBS_DIR_OFFSET 8
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#define SW_CI_HBS_DIR_MASK 0x00000100
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#define SW_DIVERSITY_MODE_OFFSET 6
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#define SW_DIVERSITY_MODE_MASK 0x00000040
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#define SW_PLD_REF_PHASE_OFFSET 3
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#define SW_PLD_REF_PHASE_MASK 0x00000038
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#define SW_TX_PLD_MODE_OFFSET 1
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#define SW_TX_PLD_MODE_MASK 0x00000006
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#define SW_PLD_COPY_MODE_OFFSET 0
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#define SW_PLD_COPY_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_HYBRID_CTRL_ADDR 0x001c
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#define SW_TX_HYBRID_PRE_NUM_OFFSET 0
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#define SW_TX_HYBRID_PRE_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_SW_ACCESS_BUF_ADDR 0x0020
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#define SW_MASK_SNR_WR_EN_OFFSET 4
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#define SW_MASK_SNR_WR_EN_MASK 0x00000010
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#define SW_ACCESS_FDBUF_EN_OFFSET 3
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#define SW_ACCESS_FDBUF_EN_MASK 0x00000008
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#define SW_ACCESS_CSI_BUF_EN_OFFSET 2
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#define SW_ACCESS_CSI_BUF_EN_MASK 0x00000004
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#define SW_ACCESS_AGC_GAIN_BUF_EN_OFFSET 1
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#define SW_ACCESS_AGC_GAIN_BUF_EN_MASK 0x00000002
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#define SW_ACCESS_TMI_BUF_EN_OFFSET 0
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#define SW_ACCESS_TMI_BUF_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RX_PAUSE_CLR_ADDR 0x0024
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#define SW_SOUND_PAUSE_EN_OFFSET 31
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#define SW_SOUND_PAUSE_EN_MASK 0x80000000
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#define SW_RX_PAUSE_CLR_OFFSET 0
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#define SW_RX_PAUSE_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_NEG_PREAM_CTRL_ADDR 0x0028
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#define SW_NEG_LONG_PREAM_SYMB_NUM_OFFSET 8
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#define SW_NEG_LONG_PREAM_SYMB_NUM_MASK 0x0000FF00
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#define SW_NEG_PREAM_SYMB_NUM_OFFSET 0
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#define SW_NEG_PREAM_SYMB_NUM_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_TONE_MAP_GIX_LONG_ADDR 0x002c
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#define SW_AV_HIGH_SPEED_GI_3534_OFFSET 0
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#define SW_AV_HIGH_SPEED_GI_3534_MASK 0x00001FFF
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//-----------------------------------
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#define CFG_BB_TONE_MAP_GIX_NUM_ADDR 0x0030
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#define SW_GIX_3534_CLK25M_POINT_ALIGN_OFFSET 20
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#define SW_GIX_3534_CLK25M_POINT_ALIGN_MASK 0x3FF00000
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#define SW_GIX_567_CLK25M_POINT_ALIGN_OFFSET 10
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#define SW_GIX_567_CLK25M_POINT_ALIGN_MASK 0x000FFC00
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#define SW_GIX_417_CLK25M_POINT_ALIGN_OFFSET 0
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#define SW_GIX_417_CLK25M_POINT_ALIGN_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_TONE_MAP_GIX_POINT_ADDR 0x0034
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#define SW_AV_HIGH_SPEED_GI_567_OFFSET 10
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#define SW_AV_HIGH_SPEED_GI_567_MASK 0x000FFC00
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#define SW_AV_HIGH_SPEED_GI_417_OFFSET 0
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#define SW_AV_HIGH_SPEED_GI_417_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_FCPLD_FFT_NUM_CTRT_ADDR 0x0038
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#define SW_PLD_FFT_HALF_NUM_OFFSET 16
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#define SW_PLD_FFT_HALF_NUM_MASK 0x0FFF0000
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#define SW_FC_FFT_HALF_NUM_OFFSET 0
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#define SW_FC_FFT_HALF_NUM_MASK 0x00000FFF
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//-----------------------------------
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#define CFG_BB_FC101_BANDWIDTH_ADDR 0x0040
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#define SW_FC101_END_TONE_OFFSET 16
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#define SW_FC101_END_TONE_MASK 0x07FF0000
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#define SW_FC101_START_TONE_OFFSET 0
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#define SW_FC101_START_TONE_MASK 0x000007FF
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//-----------------------------------
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#define CFG_BB_TX_FCC_CTRL_ADDR 0x0050
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#define SW_TX_RI_DISABLE_CHOS_OFFSET 1
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#define SW_TX_RI_DISABLE_CHOS_MASK 0x00000002
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#define SW_TX_RI_DISABLE_OFFSET 0
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#define SW_TX_RI_DISABLE_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_DPSK_CTRL_ADDR 0x0054
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#define SW_DPSK_IS_FORBIDDEN_OFFSET 1
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#define SW_DPSK_IS_FORBIDDEN_MASK 0x00000002
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#define SW_IS_DPSK_OFFSET 0
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#define SW_IS_DPSK_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RAW_DATA_MODE_CTRL_ADDR 0x005c
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#define SW_IS_RX_RAW_DATA_MODE_OFFSET 1
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#define SW_IS_RX_RAW_DATA_MODE_MASK 0x00000002
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#define SW_IS_TX_RAW_DATA_MODE_OFFSET 0
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#define SW_IS_TX_RAW_DATA_MODE_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RX_FC_RAW_0_ADDR 0x0060
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#define SW_RX_FC_RAW_RD_WORD0_OFFSET 0
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#define SW_RX_FC_RAW_RD_WORD0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_FC_RAW_1_ADDR 0x0064
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#define SW_RX_FC_RAW_RD_WORD1_OFFSET 0
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#define SW_RX_FC_RAW_RD_WORD1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_FC_RAW_2_ADDR 0x0068
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#define SW_RX_FC_RAW_RD_WORD2_OFFSET 0
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#define SW_RX_FC_RAW_RD_WORD2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_FC_RAW_3_ADDR 0x006C
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#define SW_RX_FC_RAW_RD_WORD3_OFFSET 0
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#define SW_RX_FC_RAW_RD_WORD3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_FC_CFG_0_ADDR 0x0070
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#define SW_RX_FC_NOW_CFG_WORD0_OFFSET 0
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#define SW_RX_FC_NOW_CFG_WORD0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_FC_CFG_1_ADDR 0x0074
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#define SW_RX_FC_NOW_CFG_WORD1_OFFSET 0
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#define SW_RX_FC_NOW_CFG_WORD1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_FC_CFG_2_ADDR 0x0078
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#define SW_RX_FC_NOW_CFG_WORD2_OFFSET 0
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#define SW_RX_FC_NOW_CFG_WORD2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_RX_FC_CFG_3_ADDR 0x007c
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#define SW_RX_FC_NOW_CFG_VLD_OFFSET 16
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#define SW_RX_FC_NOW_CFG_VLD_MASK 0x00010000
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#define SW_RX_FC_NOW_CFG_WORD3_OFFSET 0
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#define SW_RX_FC_NOW_CFG_WORD3_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_INT_EN_0_ADDR 0x0080
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#define BB_INT_EN_0_OFFSET 0
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#define BB_INT_EN_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_CLR_0_ADDR 0x0084
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#define BB_INT_CLR_0_OFFSET 0
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#define BB_INT_CLR_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_MASK_0_ADDR 0x0088
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#define BB_INT_MASK_0_OFFSET 0
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#define BB_INT_MASK_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_RAW_0_ADDR 0x008c
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#define BB_INT_RAW_0_OFFSET 0
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#define BB_INT_RAW_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_EN_1_ADDR 0x0090
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#define BB_INT_EN_1_OFFSET 0
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#define BB_INT_EN_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_CLR_1_ADDR 0x0094
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#define BB_INT_CLR_1_OFFSET 0
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#define BB_INT_CLR_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_MASK_1_ADDR 0x0098
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#define BB_INT_MASK_1_OFFSET 0
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#define BB_INT_MASK_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_RAW_1_ADDR 0x009c
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#define BB_INT_RAW_1_OFFSET 0
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#define BB_INT_RAW_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_EN_2_ADDR 0x00a0
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#define BB_INT_EN_2_OFFSET 0
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#define BB_INT_EN_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_CLR_2_ADDR 0x00a4
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#define BB_INT_CLR_2_OFFSET 0
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#define BB_INT_CLR_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_MASK_2_ADDR 0x00a8
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#define BB_INT_MASK_2_OFFSET 0
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#define BB_INT_MASK_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_RAW_2_ADDR 0x00ac
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#define BB_INT_RAW_2_OFFSET 0
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#define BB_INT_RAW_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_EN_3_ADDR 0x00b0
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#define BB_INT_EN_3_OFFSET 0
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#define BB_INT_EN_3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_CLR_3_ADDR 0x00b4
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#define BB_INT_CLR_3_OFFSET 0
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#define BB_INT_CLR_3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_MASK_3_ADDR 0x00b8
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#define BB_INT_MASK_3_OFFSET 0
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#define BB_INT_MASK_3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_INT_RAW_3_ADDR 0x00bc
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#define BB_INT_RAW_3_OFFSET 0
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#define BB_INT_RAW_3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PB_ROBO_ADDR 0x00c0
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#define SW_MN_INVERT_OFFSET 1
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#define SW_MN_INVERT_MASK 0x00000002
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#define SW_IS_NSG_PB_ROBO_OFFSET 0
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#define SW_IS_NSG_PB_ROBO_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_PB_RIFS_0_ADDR 0x00c4
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#define SW_GP_1_NUMSYM_RIFS_OFFSET 16
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#define SW_GP_1_NUMSYM_RIFS_MASK 0xFFFF0000
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#define SW_GP_0_NUMSYM_RIFS_OFFSET 0
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#define SW_GP_0_NUMSYM_RIFS_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_PB_RIFS_1_ADDR 0x00c8
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#define SW_FIRST_TWO_PLD_SYMB_CLK25M_POINT_OFFSET 16
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#define SW_FIRST_TWO_PLD_SYMB_CLK25M_POINT_MASK 0xFFFF0000
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#define SW_GP_2_NUMSYM_RIFS_OFFSET 0
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#define SW_GP_2_NUMSYM_RIFS_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_GP_SYMB_CAL_PRECISION_ADDR 0x00cc
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#define SW_GP_FLAV_SYMB_CAL_PRECISION_OFFSET 0
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#define SW_GP_FLAV_SYMB_CAL_PRECISION_MASK 0x0000001F
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//-----------------------------------
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#define CFG_BB_PB_IFS_ADDR 0x00f0
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#define SW_RIFS_OFFSET 16
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#define SW_RIFS_MASK 0xFFFF0000
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#define SW_BIFS_OFFSET 0
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#define SW_BIFS_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_TX_END_FRM_CNT_ADDR 0x00f4
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#define PHY_TX_ABORT_CNT_CLR_OFFSET 31
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#define PHY_TX_ABORT_CNT_CLR_MASK 0x80000000
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#define PHY_TX_ABORT_CNT_OFFSET 16
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#define PHY_TX_ABORT_CNT_MASK 0x7FFF0000
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#define PHY_TX_DONE_CNT_CLR_OFFSET 15
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#define PHY_TX_DONE_CNT_CLR_MASK 0x00008000
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#define PHY_TX_DONE_CNT_OFFSET 0
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#define PHY_TX_DONE_CNT_MASK 0x00007FFF
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//-----------------------------------
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#define CFG_BB_TX_ST_FRM_CNT_ADDR 0x00f8
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#define PHY_TX_PRS_CNT_CLR_OFFSET 31
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#define PHY_TX_PRS_CNT_CLR_MASK 0x80000000
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#define PHY_TX_PRS_CNT_OFFSET 16
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#define PHY_TX_PRS_CNT_MASK 0x7FFF0000
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#define PHY_TX_START_CNT_CLR_OFFSET 15
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#define PHY_TX_START_CNT_CLR_MASK 0x00008000
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#define PHY_TX_START_CNT_OFFSET 0
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#define PHY_TX_START_CNT_MASK 0x00007FFF
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//-----------------------------------
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#define CFG_BB_FC_OFFSET0_ADDR 0x0100
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#define SW_FC_SYMB5_OFFSET_OFFSET 24
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#define SW_FC_SYMB5_OFFSET_MASK 0xFF000000
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#define SW_FC_SYMB4_OFFSET_OFFSET 16
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#define SW_FC_SYMB4_OFFSET_MASK 0x00FF0000
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#define SW_FC_SYMB3_OFFSET_OFFSET 8
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#define SW_FC_SYMB3_OFFSET_MASK 0x0000FF00
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#define SW_FC_SYMB2_OFFSET_OFFSET 0
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#define SW_FC_SYMB2_OFFSET_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_FC_OFFSET1_ADDR 0x0104
|
|
#define SW_FC_SYMB9_OFFSET_OFFSET 24
|
|
#define SW_FC_SYMB9_OFFSET_MASK 0xFF000000
|
|
#define SW_FC_SYMB8_OFFSET_OFFSET 16
|
|
#define SW_FC_SYMB8_OFFSET_MASK 0x00FF0000
|
|
#define SW_FC_SYMB7_OFFSET_OFFSET 8
|
|
#define SW_FC_SYMB7_OFFSET_MASK 0x0000FF00
|
|
#define SW_FC_SYMB6_OFFSET_OFFSET 0
|
|
#define SW_FC_SYMB6_OFFSET_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_OFFSET2_ADDR 0x0108
|
|
#define SW_FC_SYMB12_OFFSET_OFFSET 16
|
|
#define SW_FC_SYMB12_OFFSET_MASK 0x00FF0000
|
|
#define SW_FC_SYMB11_OFFSET_OFFSET 8
|
|
#define SW_FC_SYMB11_OFFSET_MASK 0x0000FF00
|
|
#define SW_FC_SYMB10_OFFSET_OFFSET 0
|
|
#define SW_FC_SYMB10_OFFSET_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_GI_ADDR 0x010C
|
|
#define SW_FC_GI1_OFFSET 16
|
|
#define SW_FC_GI1_MASK 0x07FF0000
|
|
#define SW_FC_GI0_RANGE_OFFSET 11
|
|
#define SW_FC_GI0_RANGE_MASK 0x00007800
|
|
#define SW_FC_GI0_OFFSET 0
|
|
#define SW_FC_GI0_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_GI0_ADDR 0x0110
|
|
#define SW_PLD_GI1_RANGE_OFFSET 28
|
|
#define SW_PLD_GI1_RANGE_MASK 0xF0000000
|
|
#define SW_PLD_GI1_OFFSET 16
|
|
#define SW_PLD_GI1_MASK 0x0FFF0000
|
|
#define SW_PLD_GI0_RANGE_OFFSET 12
|
|
#define SW_PLD_GI0_RANGE_MASK 0x0000F000
|
|
#define SW_PLD_GI0_OFFSET 0
|
|
#define SW_PLD_GI0_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_GI1_ADDR 0x0114
|
|
#define SW_GI3534_USE_OFFSET 12
|
|
#define SW_GI3534_USE_MASK 0x00001000
|
|
#define SW_PLD_GI2_OFFSET 0
|
|
#define SW_PLD_GI2_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CRC_CFG_ADDR 0x0118
|
|
#define SW_PLD_CRC_BY_SW_OFFSET 7
|
|
#define SW_PLD_CRC_BY_SW_MASK 0x00000080
|
|
#define SW_FC_CRC_BY_SW_OFFSET 6
|
|
#define SW_FC_CRC_BY_SW_MASK 0x00000040
|
|
#define SW_PLD_CRC_INV_OFFSET 5
|
|
#define SW_PLD_CRC_INV_MASK 0x00000020
|
|
#define SW_FC_CRC_INV_OFFSET 4
|
|
#define SW_FC_CRC_INV_MASK 0x00000010
|
|
#define SW_PLD_CRC_INITIAL_OFFSET 3
|
|
#define SW_PLD_CRC_INITIAL_MASK 0x00000008
|
|
#define SW_FC_CRC_INITIAL_OFFSET 2
|
|
#define SW_FC_CRC_INITIAL_MASK 0x00000004
|
|
#define SW_PLD_CRC_MODE_OFFSET 1
|
|
#define SW_PLD_CRC_MODE_MASK 0x00000002
|
|
#define SW_FC_CRC_MODE_OFFSET 0
|
|
#define SW_FC_CRC_MODE_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_CRC_REM_ADDR 0x011C
|
|
#define SW_FC_CRC_REMAIN_OFFSET 0
|
|
#define SW_FC_CRC_REMAIN_MASK 0x00FFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_CRC_REM_ADDR 0x0120
|
|
#define SW_PLD_CRC_REMAIN_OFFSET 0
|
|
#define SW_PLD_CRC_REMAIN_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SOF_FC_FIELD_ADDR 0x0124
|
|
#define SW_SOF_SYMB_NUM_START_OFFSET 24
|
|
#define SW_SOF_SYMB_NUM_START_MASK 0x7F000000
|
|
#define SW_SOF_PB_NUM_START_OFFSET 16
|
|
#define SW_SOF_PB_NUM_START_MASK 0x007F0000
|
|
#define SW_SOF_DCEM_START_OFFSET 8
|
|
#define SW_SOF_DCEM_START_MASK 0x00007F00
|
|
#define SW_SOF_DCBM_START_OFFSET 0
|
|
#define SW_SOF_DCBM_START_MASK 0x0000007F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_BEA_FC_FIELD_ADDR 0x0128
|
|
#define SW_BEA_SYMB_NUM_START_OFFSET 24
|
|
#define SW_BEA_SYMB_NUM_START_MASK 0x7F000000
|
|
#define SW_BEA_PB_NUM_START_OFFSET 16
|
|
#define SW_BEA_PB_NUM_START_MASK 0x007F0000
|
|
#define SW_BEA_DCEM_START_OFFSET 8
|
|
#define SW_BEA_DCEM_START_MASK 0x00007F00
|
|
#define SW_BEA_DCBM_START_OFFSET 0
|
|
#define SW_BEA_DCBM_START_MASK 0x0000007F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_0_ADDR 0x0130
|
|
#define SW_CONFIG_PB_SYMB_NUM_OFFSET 22
|
|
#define SW_CONFIG_PB_SYMB_NUM_MASK 0x7FC00000
|
|
#define SW_CONFIG_PB_SYMB_NUM_EN_OFFSET 21
|
|
#define SW_CONFIG_PB_SYMB_NUM_EN_MASK 0x00200000
|
|
#define SW_CONFIG_PLD_SYMB_NUM_OFFSET 12
|
|
#define SW_CONFIG_PLD_SYMB_NUM_MASK 0x001FF000
|
|
#define SW_CONFIG_PLD_SYMB_NUM_EN_OFFSET 11
|
|
#define SW_CONFIG_PLD_SYMB_NUM_EN_MASK 0x00000800
|
|
#define SW_CONFIG_PB_NUM_OFFSET 1
|
|
#define SW_CONFIG_PB_NUM_MASK 0x000007FE
|
|
#define SW_CONFIG_PB_NUM_EN_OFFSET 0
|
|
#define SW_CONFIG_PB_NUM_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_1_ADDR 0x0134
|
|
#define SW_CONFIG_TURBO_RATE_OFFSET 13
|
|
#define SW_CONFIG_TURBO_RATE_MASK 0x00006000
|
|
#define SW_CONFIG_TURBO_RATE_EN_OFFSET 12
|
|
#define SW_CONFIG_TURBO_RATE_EN_MASK 0x00001000
|
|
#define SW_CONFIG_MODU_MODE_OFFSET 9
|
|
#define SW_CONFIG_MODU_MODE_MASK 0x00000E00
|
|
#define SW_CONFIG_MODU_MODE_EN_OFFSET 8
|
|
#define SW_CONFIG_MODU_MODE_EN_MASK 0x00000100
|
|
#define SW_CONFIG_COPY_NUM_OFFSET 5
|
|
#define SW_CONFIG_COPY_NUM_MASK 0x000000E0
|
|
#define SW_CONFIG_COPY_NUM_EN_OFFSET 4
|
|
#define SW_CONFIG_COPY_NUM_EN_MASK 0x00000010
|
|
#define SW_CONFIG_PB_SIZE_OFFSET 1
|
|
#define SW_CONFIG_PB_SIZE_MASK 0x0000000E
|
|
#define SW_CONFIG_PB_SIZE_EN_OFFSET 0
|
|
#define SW_CONFIG_PB_SIZE_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RTL_PARSE_DBG_4_ADDR 0x013c
|
|
#define RTL_FC_PARSE_PB_NUM_OFFSET 0
|
|
#define RTL_FC_PARSE_PB_NUM_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RTL_PARSE_DBG_3_ADDR 0x0140
|
|
#define RTL_FC_PARSE_INTER_PER_COPY_OFFSET 11
|
|
#define RTL_FC_PARSE_INTER_PER_COPY_MASK 0x01FFF800
|
|
#define RTL_FC_PARSE_INTER_SIZE_OFFSET 0
|
|
#define RTL_FC_PARSE_INTER_SIZE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RTL_PARSE_DBG_2_ADDR 0x0144
|
|
#define RTL_FC_PARSE_INTER_SHIFT_STEP_OFFSET 21
|
|
#define RTL_FC_PARSE_INTER_SHIFT_STEP_MASK 0x01E00000
|
|
#define RTL_FC_PARSE_INTER_NUM_OFFSET 17
|
|
#define RTL_FC_PARSE_INTER_NUM_MASK 0x001E0000
|
|
#define RTL_FC_PARSE_LAST_BIT_SEG_OFFSET 13
|
|
#define RTL_FC_PARSE_LAST_BIT_SEG_MASK 0x0001E000
|
|
#define RTL_FC_PARSE_SEG_BIT_NUM_OFFSET 0
|
|
#define RTL_FC_PARSE_SEG_BIT_NUM_MASK 0x00001FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RTL_PARSE_DBG_1_ADDR 0x0148
|
|
#define RTL_FC_PARSE_PAD_BIT_NUM_OFFSET 13
|
|
#define RTL_FC_PARSE_PAD_BIT_NUM_MASK 0x03FFE000
|
|
#define RTL_FC_PARSE_USED_TONE_NUM_OFFSET 2
|
|
#define RTL_FC_PARSE_USED_TONE_NUM_MASK 0x00001FFC
|
|
#define RTL_FC_PARSE_TURBO_RATE_OFFSET 0
|
|
#define RTL_FC_PARSE_TURBO_RATE_MASK 0x00000003
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RTL_PARSE_DBG_0_ADDR 0x014c
|
|
#define RTL_FC_PARSE_MODU_MODE_OFFSET 28
|
|
#define RTL_FC_PARSE_MODU_MODE_MASK 0x70000000
|
|
#define RTL_FC_PARSE_COPY_NUM_OFFSET 25
|
|
#define RTL_FC_PARSE_COPY_NUM_MASK 0x0E000000
|
|
#define RTL_FC_PARSE_PB_SIZE_OFFSET 22
|
|
#define RTL_FC_PARSE_PB_SIZE_MASK 0x01C00000
|
|
#define RTL_FC_PARSE_PB_SYMB_NUM_OFFSET 13
|
|
#define RTL_FC_PARSE_PB_SYMB_NUM_MASK 0x003FE000
|
|
#define RTL_FC_PARSE_PLD_SYMB_NUM_OFFSET 4
|
|
#define RTL_FC_PARSE_PLD_SYMB_NUM_MASK 0x00001FF0
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TXRX_TURBO_CTRL_ADDR 0x0150
|
|
#define SW_16_21_PUNCTURE_CTRL_OFFSET 8
|
|
#define SW_16_21_PUNCTURE_CTRL_MASK 0x00000100
|
|
#define SW_OUT_INFO_SCALE_SEL_OFFSET 3
|
|
#define SW_OUT_INFO_SCALE_SEL_MASK 0x00000038
|
|
#define SW_PUNCTURE_BIT_LOC_OFFSET 0
|
|
#define SW_PUNCTURE_BIT_LOC_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TR_GP_FC_PLD_GI_ADDR 0x0154
|
|
#define SW_GP_FC_GI_OFFSET 12
|
|
#define SW_GP_FC_GI_MASK 0x007FF000
|
|
#define SW_GP_PLD_GI_STD_OFFSET 0
|
|
#define SW_GP_PLD_GI_STD_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TR_GP_PLD_GI_ADDR 0x0158
|
|
#define SW_GP_PLD_GI_HS_OFFSET 12
|
|
#define SW_GP_PLD_GI_HS_MASK 0x00FFF000
|
|
#define SW_GP_PLD_GI_MIN_OFFSET 0
|
|
#define SW_GP_PLD_GI_MIN_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_EN_0_EXT_ADDR 0x0180
|
|
#define BB_INT_EN_0_EXT_OFFSET 0
|
|
#define BB_INT_EN_0_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_CLR_0_EXT_ADDR 0x0184
|
|
#define BB_INT_CLR_0_EXT_OFFSET 0
|
|
#define BB_INT_CLR_0_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_MASK_0_EXT_ADDR 0x0188
|
|
#define BB_INT_MASK_0_EXT_OFFSET 0
|
|
#define BB_INT_MASK_0_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_RAW_0_EXT_ADDR 0x018c
|
|
#define BB_INT_RAW_0_EXT_OFFSET 0
|
|
#define BB_INT_RAW_0_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_EN_1_EXT_ADDR 0x0190
|
|
#define BB_INT_EN_1_EXT_OFFSET 0
|
|
#define BB_INT_EN_1_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_CLR_1_EXT_ADDR 0x0194
|
|
#define BB_INT_CLR_1_EXT_OFFSET 0
|
|
#define BB_INT_CLR_1_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_MASK_1_EXT_ADDR 0x0198
|
|
#define BB_INT_MASK_1_EXT_OFFSET 0
|
|
#define BB_INT_MASK_1_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_RAW_1_EXT_ADDR 0x019c
|
|
#define BB_INT_RAW_1_EXT_OFFSET 0
|
|
#define BB_INT_RAW_1_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_EN_2_EXT_ADDR 0x01a0
|
|
#define BB_INT_EN_2_EXT_OFFSET 0
|
|
#define BB_INT_EN_2_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_CLR_2_EXT_ADDR 0x01a4
|
|
#define BB_INT_CLR_2_EXT_OFFSET 0
|
|
#define BB_INT_CLR_2_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_MASK_2_EXT_ADDR 0x01a8
|
|
#define BB_INT_MASK_2_EXT_OFFSET 0
|
|
#define BB_INT_MASK_2_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_RAW_2_EXT_ADDR 0x01ac
|
|
#define BB_INT_RAW_2_EXT_OFFSET 0
|
|
#define BB_INT_RAW_2_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_EN_3_EXT_ADDR 0x01b0
|
|
#define BB_INT_EN_3_EXT_OFFSET 0
|
|
#define BB_INT_EN_3_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_CLR_3_EXT_ADDR 0x01b4
|
|
#define BB_INT_CLR_3_EXT_OFFSET 0
|
|
#define BB_INT_CLR_3_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_MASK_3_EXT_ADDR 0x01b8
|
|
#define BB_INT_MASK_3_EXT_OFFSET 0
|
|
#define BB_INT_MASK_3_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_RAW_3_EXT_ADDR 0x01bc
|
|
#define BB_INT_RAW_3_EXT_OFFSET 0
|
|
#define BB_INT_RAW_3_EXT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R0_B0_TONE_ADDR 0x0200
|
|
#define SW_RATE0_BAND0_FC_NUM_OFFSET 27
|
|
#define SW_RATE0_BAND0_FC_NUM_MASK 0x78000000
|
|
#define SW_RATE0_BAND0_END_TONE_OFFSET 16
|
|
#define SW_RATE0_BAND0_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE0_BAND0_START_TONE_OFFSET 0
|
|
#define SW_RATE0_BAND0_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R0_B1_TONE_ADDR 0x0204
|
|
#define SW_RATE0_BAND1_FC_NUM_OFFSET 27
|
|
#define SW_RATE0_BAND1_FC_NUM_MASK 0x78000000
|
|
#define SW_RATE0_BAND1_END_TONE_OFFSET 16
|
|
#define SW_RATE0_BAND1_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE0_BAND1_START_TONE_OFFSET 0
|
|
#define SW_RATE0_BAND1_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R0_B2_TONE_ADDR 0x0208
|
|
#define SW_RATE0_BAND2_FC_NUM_OFFSET 27
|
|
#define SW_RATE0_BAND2_FC_NUM_MASK 0x78000000
|
|
#define SW_RATE0_BAND2_END_TONE_OFFSET 16
|
|
#define SW_RATE0_BAND2_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE0_BAND2_START_TONE_OFFSET 0
|
|
#define SW_RATE0_BAND2_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R0_B0_VLD_TONE_ADDR 0x020C
|
|
#define SW_RATE0_BAND0_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_RATE0_BAND0_VLD_TONE_NUM_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R0_B1_VLD_TONE_ADDR 0x0210
|
|
#define SW_RATE0_BAND1_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_RATE0_BAND1_VLD_TONE_NUM_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R0_B2_VLD_TONE_ADDR 0x0214
|
|
#define SW_RATE0_BAND2_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_RATE0_BAND2_VLD_TONE_NUM_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R1_B0_TONE_ADDR 0x0300
|
|
#define SW_RATE1_BAND0_FC_NUM_OFFSET 27
|
|
#define SW_RATE1_BAND0_FC_NUM_MASK 0x78000000
|
|
#define SW_RATE1_BAND0_END_TONE_OFFSET 16
|
|
#define SW_RATE1_BAND0_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE1_BAND0_START_TONE_OFFSET 0
|
|
#define SW_RATE1_BAND0_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R1_B1_TONE_ADDR 0x0304
|
|
#define SW_RATE1_BAND1_FC_NUM_OFFSET 27
|
|
#define SW_RATE1_BAND1_FC_NUM_MASK 0x78000000
|
|
#define SW_RATE1_BAND1_END_TONE_OFFSET 16
|
|
#define SW_RATE1_BAND1_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE1_BAND1_START_TONE_OFFSET 0
|
|
#define SW_RATE1_BAND1_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R1_B2_TONE_ADDR 0x0308
|
|
#define SW_RATE1_BAND2_FC_NUM_OFFSET 27
|
|
#define SW_RATE1_BAND2_FC_NUM_MASK 0x78000000
|
|
#define SW_RATE1_BAND2_END_TONE_OFFSET 16
|
|
#define SW_RATE1_BAND2_END_TONE_MASK 0x07FF0000
|
|
#define SW_RATE1_BAND2_START_TONE_OFFSET 0
|
|
#define SW_RATE1_BAND2_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R1_B0_VLD_TONE_ADDR 0x030C
|
|
#define SW_RATE1_BAND0_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_RATE1_BAND0_VLD_TONE_NUM_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R1_B1_VLD_TONE_ADDR 0x0310
|
|
#define SW_RATE1_BAND1_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_RATE1_BAND1_VLD_TONE_NUM_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_R1_B2_VLD_TONE_ADDR 0x0314
|
|
#define SW_RATE1_BAND2_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_RATE1_BAND2_VLD_TONE_NUM_MASK 0x00000FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SHORT_PREAM_TONE_ADDR 0x0320
|
|
#define SW_SHORT_PREAM_FC_NUM_OFFSET 27
|
|
#define SW_SHORT_PREAM_FC_NUM_MASK 0x78000000
|
|
#define SW_SHORT_PREAM_END_TONE_OFFSET 16
|
|
#define SW_SHORT_PREAM_END_TONE_MASK 0x07FF0000
|
|
#define SW_SHORT_PREAM_START_TONE_OFFSET 0
|
|
#define SW_SHORT_PREAM_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SHORT_PREAM_VLD_TONE_ADDR 0x0324
|
|
#define SW_SHORT_PREAM_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_SHORT_PREAM_VLD_TONE_NUM_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NSG_OVERWRITE_TONE_ADDR 0x0328
|
|
#define SW_NSG_OVERWRITE_FC_NUM_OFFSET 27
|
|
#define SW_NSG_OVERWRITE_FC_NUM_MASK 0x78000000
|
|
#define SW_NSG_OVERWRITE_END_TONE_OFFSET 16
|
|
#define SW_NSG_OVERWRITE_END_TONE_MASK 0x07FF0000
|
|
#define SW_NSG_OVERWRITE_START_TONE_OFFSET 0
|
|
#define SW_NSG_OVERWRITE_START_TONE_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NSG_OVERWRITE_VLD_TONE_ADDR 0x032c
|
|
#define SW_NSG_OVERWRITE_EN_OFFSET 16
|
|
#define SW_NSG_OVERWRITE_EN_MASK 0x00010000
|
|
#define SW_NSG_OVERWRITE_VLD_TONE_NUM_OFFSET 0
|
|
#define SW_NSG_OVERWRITE_VLD_TONE_NUM_MASK 0x000007FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_VITB_CTRL_ADDR 0x0400
|
|
#define SW_VITB_FAIL_OFFSET 22
|
|
#define SW_VITB_FAIL_MASK 0x00400000
|
|
#define SW_VITB_DONE_OFFSET 21
|
|
#define SW_VITB_DONE_MASK 0x00200000
|
|
#define SW_VITB_START_OFFSET 20
|
|
#define SW_VITB_START_MASK 0x00100000
|
|
#define SW_VITB_SIZE_OFFSET 4
|
|
#define SW_VITB_SIZE_MASK 0x0001FFF0
|
|
#define SW_VITB_MODE_OFFSET 2
|
|
#define SW_VITB_MODE_MASK 0x00000004
|
|
#define SW_VITB_SRST_OFFSET 1
|
|
#define SW_VITB_SRST_MASK 0x00000002
|
|
#define SW_VITB_EN_OFFSET 0
|
|
#define SW_VITB_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PRS_CTRL_ADDR 0x0404
|
|
#define SW_PRS1_SRST_EN_OFFSET 1
|
|
#define SW_PRS1_SRST_EN_MASK 0x00000002
|
|
#define SW_PRS0_SRST_EN_OFFSET 0
|
|
#define SW_PRS0_SRST_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_PLD_CNTR_CLR_ADDR 0x0500
|
|
#define TX_UNDERFLOW_CLR_OFFSET 7
|
|
#define TX_UNDERFLOW_CLR_MASK 0x00000080
|
|
#define TX_FC_UNDERFLOW_CLR_OFFSET 6
|
|
#define TX_FC_UNDERFLOW_CLR_MASK 0x00000040
|
|
#define TX_PLD_UNDERFLOW_CLR_OFFSET 5
|
|
#define TX_PLD_UNDERFLOW_CLR_MASK 0x00000020
|
|
#define SW_RX_ABORT_CLR_OFFSET 4
|
|
#define SW_RX_ABORT_CLR_MASK 0x00000010
|
|
#define PLD_CRC_ERROR_CNTR_CLR_OFFSET 3
|
|
#define PLD_CRC_ERROR_CNTR_CLR_MASK 0x00000008
|
|
#define PLD_CRC_OK_CNTR_CLR_OFFSET 2
|
|
#define PLD_CRC_OK_CNTR_CLR_MASK 0x00000004
|
|
#define FC_CRC_ERROR_CNTR_CLR_OFFSET 1
|
|
#define FC_CRC_ERROR_CNTR_CLR_MASK 0x00000002
|
|
#define FC_CRC_OK_CNTR_CLR_OFFSET 0
|
|
#define FC_CRC_OK_CNTR_CLR_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_CRC_OK_CNTR_ADDR 0x0504
|
|
#define FC_CRC_OK_CNTR_OFFSET 0
|
|
#define FC_CRC_OK_CNTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_CRC_ERROR_CNTR_ADDR 0x0508
|
|
#define FC_CRC_ERROR_CNTR_OFFSET 0
|
|
#define FC_CRC_ERROR_CNTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_CRC_OK_CNTR_ADDR 0x050C
|
|
#define PLD_CRC_OK_CNTR_OFFSET 0
|
|
#define PLD_CRC_OK_CNTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_CRC_ERROR_CNTR_ADDR 0x0510
|
|
#define PLD_CRC_ERROR_CNTR_OFFSET 0
|
|
#define PLD_CRC_ERROR_CNTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_ABORT_CNTR_ADDR 0x0514
|
|
#define RX_ABORT_CNTR_OFFSET 0
|
|
#define RX_ABORT_CNTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_UNDERFLOW_CNTR_ADDR 0x0518
|
|
#define PHY_TX_UNDERFLOW_CNT_OFFSET 0
|
|
#define PHY_TX_UNDERFLOW_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_FC_UNDERFLOW_CNTR_ADDR 0x051c
|
|
#define PHY_TX_FC_UNDERFLOW_CNT_OFFSET 0
|
|
#define PHY_TX_FC_UNDERFLOW_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_PLD_UNDERFLOW_CNTR_ADDR 0x0520
|
|
#define PHY_TX_PLD_UNDERFLOW_CNT_OFFSET 0
|
|
#define PHY_TX_PLD_UNDERFLOW_CNT_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DBG_BUS_SEL_ADDR 0x0600
|
|
#define BB_DBG_BUS_SEL_OFFSET 0
|
|
#define BB_DBG_BUS_SEL_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_TD_DBG_BUS0_ADDR 0x0604
|
|
#define RX_TD_DBG_BUS0_OFFSET 0
|
|
#define RX_TD_DBG_BUS0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_TD_DBG_BUS1_ADDR 0x0608
|
|
#define RX_TD_DBG_BUS1_OFFSET 0
|
|
#define RX_TD_DBG_BUS1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_TD_DBG_BUS2_ADDR 0x060C
|
|
#define RX_TD_DBG_BUS2_OFFSET 0
|
|
#define RX_TD_DBG_BUS2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_TD_DBG_BUS3_ADDR 0x0610
|
|
#define RX_TD_DBG_BUS3_OFFSET 0
|
|
#define RX_TD_DBG_BUS3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMI_WORD0_ADDR 0x0614
|
|
#define TMI_WORD0_OFFSET 0
|
|
#define TMI_WORD0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMI_WORD1_ADDR 0x0618
|
|
#define TMI_WORD1_OFFSET 0
|
|
#define TMI_WORD1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMI_WORD2_ADDR 0x061C
|
|
#define TMI_WORD2_OFFSET 0
|
|
#define TMI_WORD2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_TD_DBG_BUS_ADDR 0x0620
|
|
#define TX_TD_DBG_BUS_OFFSET 0
|
|
#define TX_TD_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_FD_FSM_DBG_BUS_ADDR 0x0624
|
|
#define TX_FD_FSM_DBG_BUS_OFFSET 0
|
|
#define TX_FD_FSM_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_FEC_DBG_BUS_ADDR 0x0628
|
|
#define PLD_FEC_DBG_BUS_OFFSET 0
|
|
#define PLD_FEC_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_FEC_DBG_BUS_ADDR 0x062C
|
|
#define FC_FEC_DBG_BUS_OFFSET 0
|
|
#define FC_FEC_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PRE_DBG_BUS_ADDR 0x0630
|
|
#define PRE_DBG_BUS_OFFSET 0
|
|
#define PRE_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_AGC_DBG_BUS_ADDR 0x0634
|
|
#define AGC_DBG_BUS_OFFSET 0
|
|
#define AGC_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CH_EST_DBG_BUS_ADDR 0x0638
|
|
#define CH_EST_DBG_BUS_OFFSET 0
|
|
#define CH_EST_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CH_EQU_DBG_BUS_ADDR 0x063C
|
|
#define CH_EQU_DBG_BUS_OFFSET 0
|
|
#define CH_EQU_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PLD_DE_FEC_DBG_BUS_ADDR 0x0640
|
|
#define PLD_DE_FEC_DBG_BUS_OFFSET 0
|
|
#define PLD_DE_FEC_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_CRC_DBG_BUS_ADDR 0x0644
|
|
#define FC_CRC_DBG_BUS_OFFSET 0
|
|
#define FC_CRC_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PB_CRC_DBG_BUS_ADDR 0x0648
|
|
#define PB_CRC_DBG_BUS_OFFSET 0
|
|
#define PB_CRC_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DFE_DBG_BUS_ADDR 0x064C
|
|
#define DFE_DBG_BUS_OFFSET 0
|
|
#define DFE_DBG_BUS_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ADA_DUMP_CFG_ADDR 0x0680
|
|
#define SW_BB_DUMP_DATA_SEL_OFFSET 8
|
|
#define SW_BB_DUMP_DATA_SEL_MASK 0x00000F00
|
|
#define SW_BB_ADC_DATA_SAT_SEL_OFFSET 4
|
|
#define SW_BB_ADC_DATA_SAT_SEL_MASK 0x00000030
|
|
#define SW_BB_DUMP_TRIG_SEL_OFFSET 0
|
|
#define SW_BB_DUMP_TRIG_SEL_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PHY_SPARE0_ADDR 0x0690
|
|
#define SW_PHY_SPARE0_OFFSET 0
|
|
#define SW_PHY_SPARE0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PHY_SPARE1_ADDR 0x0694
|
|
#define SW_PHY_SPARE1_OFFSET 0
|
|
#define SW_PHY_SPARE1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PHY_SPARE2_ADDR 0x0698
|
|
#define SW_PHY_SPARE2_OFFSET 0
|
|
#define SW_PHY_SPARE2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PHY_SPARE3_ADDR 0x069c
|
|
#define SW_PHY_SPARE3_OFFSET 0
|
|
#define SW_PHY_SPARE3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PHY_PARSE_CONST_ADDR 0x06a0
|
|
#define SW_TONE_MAP_PB136_MAX_PBNUM_OFFSET 16
|
|
#define SW_TONE_MAP_PB136_MAX_PBNUM_MASK 0x03FF0000
|
|
#define SW_TONE_MAP_PB520_MAX_PBNUM_OFFSET 0
|
|
#define SW_TONE_MAP_PB520_MAX_PBNUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_2_ADDR 0x06a4
|
|
#define SW_CONFIG_PAD_BITS_NUM_OFFSET 17
|
|
#define SW_CONFIG_PAD_BITS_NUM_MASK 0x3FFE0000
|
|
#define SW_CONFIG_PAD_BITS_NUM_EN_OFFSET 16
|
|
#define SW_CONFIG_PAD_BITS_NUM_EN_MASK 0x00010000
|
|
#define SW_CONFIG_USED_TONE_NUM_OFFSET 1
|
|
#define SW_CONFIG_USED_TONE_NUM_MASK 0x00001FFE
|
|
#define SW_CONFIG_USED_TONE_NUM_EN_OFFSET 0
|
|
#define SW_CONFIG_USED_TONE_NUM_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_3_ADDR 0x06a8
|
|
#define SW_CONFIG_GP_MPDUCNT_OFFSET 29
|
|
#define SW_CONFIG_GP_MPDUCNT_MASK 0x60000000
|
|
#define SW_CONFIG_GP_MPDUCNT_EN_OFFSET 28
|
|
#define SW_CONFIG_GP_MPDUCNT_EN_MASK 0x10000000
|
|
#define SW_CONFIG_INTER_NUM_OFFSET 22
|
|
#define SW_CONFIG_INTER_NUM_MASK 0x03C00000
|
|
#define SW_CONFIG_INTER_NUM_EN_OFFSET 21
|
|
#define SW_CONFIG_INTER_NUM_EN_MASK 0x00200000
|
|
#define SW_CONFIG_LAST_BITS_SEG_OFFSET 17
|
|
#define SW_CONFIG_LAST_BITS_SEG_MASK 0x001E0000
|
|
#define SW_CONFIG_LAST_BITS_SEG_EN_OFFSET 16
|
|
#define SW_CONFIG_LAST_BITS_SEG_EN_MASK 0x00010000
|
|
#define SW_CONFIG_IS_OSG_16_18_TURBO_OFFSET 15
|
|
#define SW_CONFIG_IS_OSG_16_18_TURBO_MASK 0x00008000
|
|
#define SW_CONFIG_IS_OSG_16_18_TURBO_EN_OFFSET 14
|
|
#define SW_CONFIG_IS_OSG_16_18_TURBO_EN_MASK 0x00004000
|
|
#define SW_CONFIG_SEG_BITS_NUM_OFFSET 1
|
|
#define SW_CONFIG_SEG_BITS_NUM_MASK 0x00003FFE
|
|
#define SW_CONFIG_SEG_BITS_NUM_EN_OFFSET 0
|
|
#define SW_CONFIG_SEG_BITS_NUM_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_4_ADDR 0x06ac
|
|
#define SW_CONFIG_INTER_PER_COPY_OFFSET 17
|
|
#define SW_CONFIG_INTER_PER_COPY_MASK 0x7FFE0000
|
|
#define SW_CONFIG_INTER_PER_COPY_EN_OFFSET 16
|
|
#define SW_CONFIG_INTER_PER_COPY_EN_MASK 0x00010000
|
|
#define SW_CONFIG_IS_NSG_16_18_TURBO_OFFSET 15
|
|
#define SW_CONFIG_IS_NSG_16_18_TURBO_MASK 0x00008000
|
|
#define SW_CONFIG_IS_NSG_16_18_TURBO_EN_OFFSET 14
|
|
#define SW_CONFIG_IS_NSG_16_18_TURBO_EN_MASK 0x00004000
|
|
#define SW_CONFIG_IS_GP_HIGH_SPEED_OFFSET 13
|
|
#define SW_CONFIG_IS_GP_HIGH_SPEED_MASK 0x00002000
|
|
#define SW_CONFIG_IS_GP_HIGH_SPEED_EN_OFFSET 12
|
|
#define SW_CONFIG_IS_GP_HIGH_SPEED_EN_MASK 0x00001000
|
|
#define SW_CONFIG_CARRIER_NUM_PER_INTER_OFFSET 1
|
|
#define SW_CONFIG_CARRIER_NUM_PER_INTER_MASK 0x00000FFE
|
|
#define SW_CONFIG_CARRIER_NUM_PER_INTER_EN_OFFSET 0
|
|
#define SW_CONFIG_CARRIER_NUM_PER_INTER_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_IN_PARSE_0_ADDR 0x06b0
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_0_OFFSET 0
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_IN_PARSE_1_ADDR 0x06b4
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_1_OFFSET 0
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_IN_PARSE_2_ADDR 0x06b8
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_2_OFFSET 0
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_IN_PARSE_3_ADDR 0x06bc
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_EN_OFFSET 8
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_EN_MASK 0x00000100
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_3_OFFSET 0
|
|
#define SW_CONFIG_FC_USED_IN_PARSE_3_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_5_ADDR 0x06c0
|
|
#define SW_CONFIG_GP_PB_SIZE_OFFSET 29
|
|
#define SW_CONFIG_GP_PB_SIZE_MASK 0xE0000000
|
|
#define SW_CONFIG_GP_PB_SIZE_EN_OFFSET 28
|
|
#define SW_CONFIG_GP_PB_SIZE_EN_MASK 0x10000000
|
|
#define SW_CONFIG_TMAP_STEI_EN_OFFSET 24
|
|
#define SW_CONFIG_TMAP_STEI_EN_MASK 0x01000000
|
|
#define SW_CONFIG_TMAP_STEI_OFFSET 16
|
|
#define SW_CONFIG_TMAP_STEI_MASK 0x00FF0000
|
|
#define SW_CONFIG_GP_TMIAV_OFFSET 9
|
|
#define SW_CONFIG_GP_TMIAV_MASK 0x00003E00
|
|
#define SW_CONFIG_GP_TMIAV_EN_OFFSET 8
|
|
#define SW_CONFIG_GP_TMIAV_EN_MASK 0x00000100
|
|
#define SW_CONFIG_INTER_SHIFT_STEP_OFFSET 1
|
|
#define SW_CONFIG_INTER_SHIFT_STEP_MASK 0x0000001E
|
|
#define SW_CONFIG_INTER_SHIFT_STEP_EN_OFFSET 0
|
|
#define SW_CONFIG_INTER_SHIFT_STEP_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_6_ADDR 0x06c4
|
|
#define SW_CONFIG_TMAP_DTEI_EN_OFFSET 8
|
|
#define SW_CONFIG_TMAP_DTEI_EN_MASK 0x00000100
|
|
#define SW_CONFIG_TMAP_DTEI_OFFSET 0
|
|
#define SW_CONFIG_TMAP_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_7_ADDR 0x06c8
|
|
#define SW_CONFIG_TX_MAC_PB_SIZE_OFFSET 29
|
|
#define SW_CONFIG_TX_MAC_PB_SIZE_MASK 0xE0000000
|
|
#define SW_CONFIG_TX_MAC_PB_SIZE_EN_OFFSET 28
|
|
#define SW_CONFIG_TX_MAC_PB_SIZE_EN_MASK 0x10000000
|
|
#define SW_CONFIG_TX_MAC_TURBO_RATE_OFFSET 25
|
|
#define SW_CONFIG_TX_MAC_TURBO_RATE_MASK 0x06000000
|
|
#define SW_CONFIG_TX_MAC_TURBO_RATE_EN_OFFSET 24
|
|
#define SW_CONFIG_TX_MAC_TURBO_RATE_EN_MASK 0x01000000
|
|
#define SW_CONFIG_GP_HIGH_SPEED_PLD_BITS_NUM_OFFSET 1
|
|
#define SW_CONFIG_GP_HIGH_SPEED_PLD_BITS_NUM_MASK 0x00FFFFFE
|
|
#define SW_CONFIG_GP_HIGH_SPEED_PLD_BITS_NUM_EN_OFFSET 0
|
|
#define SW_CONFIG_GP_HIGH_SPEED_PLD_BITS_NUM_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_CONFIG_FC_PARSE_8_ADDR 0x06cc
|
|
#define SW_CONFIG_VLD_TONE_NUM_OFFSET 1
|
|
#define SW_CONFIG_VLD_TONE_NUM_MASK 0x00001FFE
|
|
#define SW_CONFIG_VLD_TONE_NUM_EN_OFFSET 0
|
|
#define SW_CONFIG_VLD_TONE_NUM_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TD_ROBO_ADDR 0x06d0
|
|
#define SW_TD_ROBO_MODE_OFFSET 1
|
|
#define SW_TD_ROBO_MODE_MASK 0x0000000E
|
|
#define SW_TD_ROBO_EN_OFFSET 0
|
|
#define SW_TD_ROBO_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SAMPLING_RATE_ADDR 0x06d4
|
|
#define SW_G3_IFFT_SYMB_CNT_OFFSET 1
|
|
#define SW_G3_IFFT_SYMB_CNT_MASK 0x0000FFFE
|
|
#define SW_SAMPLING_RATE_SEL_OFFSET 0
|
|
#define SW_SAMPLING_RATE_SEL_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_SW_G3_CTRL_ADDR 0x06d8
|
|
#define SW_G3_TX_TD_START_OFFSET 31
|
|
#define SW_G3_TX_TD_START_MASK 0x80000000
|
|
#define SW_G3_IFFT_SYMB_CNT_SET_VALUE_OFFSET 16
|
|
#define SW_G3_IFFT_SYMB_CNT_SET_VALUE_MASK 0x7FFF0000
|
|
#define SW_FC_PARSE_DONE_OFFSET 12
|
|
#define SW_FC_PARSE_DONE_MASK 0x00001000
|
|
#define SW_G3_TX_FD_RESET_OFFSET 11
|
|
#define SW_G3_TX_FD_RESET_MASK 0x00000800
|
|
#define SW_G3_TX_BY_CCA_IDLE_OFFSET 10
|
|
#define SW_G3_TX_BY_CCA_IDLE_MASK 0x00000400
|
|
#define SW_G3_IFFT_SYMB_CNT_SET_PLS_OFFSET 9
|
|
#define SW_G3_IFFT_SYMB_CNT_SET_PLS_MASK 0x00000200
|
|
#define SW_G3_FFT_FLUSH_WORKING_BUFFER_OFFSET 8
|
|
#define SW_G3_FFT_FLUSH_WORKING_BUFFER_MASK 0x00000100
|
|
#define SW_G3_FFT_FLUSH_FREQ_BUFFER_OFFSET 7
|
|
#define SW_G3_FFT_FLUSH_FREQ_BUFFER_MASK 0x00000080
|
|
#define SW_G3_RX_STATE_OFFSET 6
|
|
#define SW_G3_RX_STATE_MASK 0x00000040
|
|
#define SW_G3_FFT_SYNC_RESET_OFFSET 5
|
|
#define SW_G3_FFT_SYNC_RESET_MASK 0x00000020
|
|
#define SW_G3_IFFT_INVERT_OFFSET 4
|
|
#define SW_G3_IFFT_INVERT_MASK 0x00000010
|
|
#define SW_G3_IFFT_SIZE_OFFSET 2
|
|
#define SW_G3_IFFT_SIZE_MASK 0x0000000C
|
|
#define SW_G3_IFFT_START_OFFSET 1
|
|
#define SW_G3_IFFT_START_MASK 0x00000002
|
|
#define SW_G3_EN_OFFSET 0
|
|
#define SW_G3_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PHY_CONST_CTRL_9_ADDR 0x06dc
|
|
#define SW_TMI_FCPL_PHAS_START_OFFSET 19
|
|
#define SW_TMI_FCPL_PHAS_START_MASK 0x1FF80000
|
|
#define SW_TMI_PREAM_PHAS_START_OFFSET 9
|
|
#define SW_TMI_PREAM_PHAS_START_MASK 0x0007FE00
|
|
#define SW_TMI_TONE_START_OFFSET 0
|
|
#define SW_TMI_TONE_START_MASK 0x000001FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FFT_CFG_ADDR 0x06e0
|
|
#define SW_FFT_SAT_FOR_PKT_OFFSET 24
|
|
#define SW_FFT_SAT_FOR_PKT_MASK 0x01000000
|
|
#define SW_FFT_SAT_CNTR_OFFSET 8
|
|
#define SW_FFT_SAT_CNTR_MASK 0x00FFFF00
|
|
#define SW_FFT_IS_SATURATE_OFFSET 7
|
|
#define SW_FFT_IS_SATURATE_MASK 0x00000080
|
|
#define SW_R8_3_RSHIFT_OFFSET 5
|
|
#define SW_R8_3_RSHIFT_MASK 0x00000060
|
|
#define SW_R8_2_RSHIFT_OFFSET 3
|
|
#define SW_R8_2_RSHIFT_MASK 0x00000018
|
|
#define SW_R8_1_RSHIFT_OFFSET 1
|
|
#define SW_R8_1_RSHIFT_MASK 0x00000006
|
|
#define SW_FFT_SHIFT_EN_OFFSET 0
|
|
#define SW_FFT_SHIFT_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_EN_4_ADDR 0x06f0
|
|
#define BB_INT_EN_4_OFFSET 0
|
|
#define BB_INT_EN_4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_CLR_4_ADDR 0x06f4
|
|
#define BB_INT_CLR_4_OFFSET 0
|
|
#define BB_INT_CLR_4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_MASK_4_ADDR 0x06f8
|
|
#define BB_INT_MASK_4_OFFSET 0
|
|
#define BB_INT_MASK_4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_INT_RAW_4_ADDR 0x06fc
|
|
#define BB_INT_RAW_4_OFFSET 0
|
|
#define BB_INT_RAW_4_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_VLD_PTR_EN_ADDR 0x0700
|
|
#define SW_RO_TMAP_PTR_VLD_OFFSET 0
|
|
#define SW_RO_TMAP_PTR_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_VLD_PTR_ADDR 0x0704
|
|
#define SW_RO_TMAP_PTR_OFFSET 0
|
|
#define SW_RO_TMAP_PTR_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DBG_BUS_LOCK_PATTERN_ADDR 0x708
|
|
#define SW_PHY_DBG_LOCK_PATTERN_OFFSET 0
|
|
#define SW_PHY_DBG_LOCK_PATTERN_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DBG_BUS_LOCK_PATTERN_MASK_ADDR 0x70c
|
|
#define SW_PHY_DBG_LOCK_PATTERN_MASK_OFFSET 0
|
|
#define SW_PHY_DBG_LOCK_PATTERN_MASK_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_WORD0_ADDR 0x0800
|
|
#define SW_RO_FC_WORD0_OFFSET 0
|
|
#define SW_RO_FC_WORD0_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_WORD1_ADDR 0x0804
|
|
#define SW_RO_FC_WORD1_OFFSET 0
|
|
#define SW_RO_FC_WORD1_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_WORD2_ADDR 0x0808
|
|
#define SW_RO_FC_WORD2_OFFSET 0
|
|
#define SW_RO_FC_WORD2_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FC_WORD3_ADDR 0x080C
|
|
#define SW_RO_FC_WORD3_OFFSET 0
|
|
#define SW_RO_FC_WORD3_MASK 0xFFFFFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_VLD_CTRL_0_ADDR 0x1000
|
|
#define SW_TMAP_TX_000_VLD_OFFSET 31
|
|
#define SW_TMAP_TX_000_VLD_MASK 0x80000000
|
|
#define SW_TMAP_TX_001_VLD_OFFSET 30
|
|
#define SW_TMAP_TX_001_VLD_MASK 0x40000000
|
|
#define SW_TMAP_TX_002_VLD_OFFSET 29
|
|
#define SW_TMAP_TX_002_VLD_MASK 0x20000000
|
|
#define SW_TMAP_TX_003_VLD_OFFSET 28
|
|
#define SW_TMAP_TX_003_VLD_MASK 0x10000000
|
|
#define SW_TMAP_TX_004_VLD_OFFSET 27
|
|
#define SW_TMAP_TX_004_VLD_MASK 0x08000000
|
|
#define SW_TMAP_TX_005_VLD_OFFSET 26
|
|
#define SW_TMAP_TX_005_VLD_MASK 0x04000000
|
|
#define SW_TMAP_TX_006_VLD_OFFSET 25
|
|
#define SW_TMAP_TX_006_VLD_MASK 0x02000000
|
|
#define SW_TMAP_TX_007_VLD_OFFSET 24
|
|
#define SW_TMAP_TX_007_VLD_MASK 0x01000000
|
|
#define SW_TMAP_TX_008_VLD_OFFSET 23
|
|
#define SW_TMAP_TX_008_VLD_MASK 0x00800000
|
|
#define SW_TMAP_TX_009_VLD_OFFSET 22
|
|
#define SW_TMAP_TX_009_VLD_MASK 0x00400000
|
|
#define SW_TMAP_TX_010_VLD_OFFSET 21
|
|
#define SW_TMAP_TX_010_VLD_MASK 0x00200000
|
|
#define SW_TMAP_TX_011_VLD_OFFSET 20
|
|
#define SW_TMAP_TX_011_VLD_MASK 0x00100000
|
|
#define SW_TMAP_TX_012_VLD_OFFSET 19
|
|
#define SW_TMAP_TX_012_VLD_MASK 0x00080000
|
|
#define SW_TMAP_TX_013_VLD_OFFSET 18
|
|
#define SW_TMAP_TX_013_VLD_MASK 0x00040000
|
|
#define SW_TMAP_TX_014_VLD_OFFSET 17
|
|
#define SW_TMAP_TX_014_VLD_MASK 0x00020000
|
|
#define SW_TMAP_TX_015_VLD_OFFSET 16
|
|
#define SW_TMAP_TX_015_VLD_MASK 0x00010000
|
|
#define SW_TMAP_TX_016_VLD_OFFSET 15
|
|
#define SW_TMAP_TX_016_VLD_MASK 0x00008000
|
|
#define SW_TMAP_TX_017_VLD_OFFSET 14
|
|
#define SW_TMAP_TX_017_VLD_MASK 0x00004000
|
|
#define SW_TMAP_TX_018_VLD_OFFSET 13
|
|
#define SW_TMAP_TX_018_VLD_MASK 0x00002000
|
|
#define SW_TMAP_TX_019_VLD_OFFSET 12
|
|
#define SW_TMAP_TX_019_VLD_MASK 0x00001000
|
|
#define SW_TMAP_TX_020_VLD_OFFSET 11
|
|
#define SW_TMAP_TX_020_VLD_MASK 0x00000800
|
|
#define SW_TMAP_TX_021_VLD_OFFSET 10
|
|
#define SW_TMAP_TX_021_VLD_MASK 0x00000400
|
|
#define SW_TMAP_TX_022_VLD_OFFSET 9
|
|
#define SW_TMAP_TX_022_VLD_MASK 0x00000200
|
|
#define SW_TMAP_TX_023_VLD_OFFSET 8
|
|
#define SW_TMAP_TX_023_VLD_MASK 0x00000100
|
|
#define SW_TMAP_TX_024_VLD_OFFSET 7
|
|
#define SW_TMAP_TX_024_VLD_MASK 0x00000080
|
|
#define SW_TMAP_TX_025_VLD_OFFSET 6
|
|
#define SW_TMAP_TX_025_VLD_MASK 0x00000040
|
|
#define SW_TMAP_TX_026_VLD_OFFSET 5
|
|
#define SW_TMAP_TX_026_VLD_MASK 0x00000020
|
|
#define SW_TMAP_TX_027_VLD_OFFSET 4
|
|
#define SW_TMAP_TX_027_VLD_MASK 0x00000010
|
|
#define SW_TMAP_TX_028_VLD_OFFSET 3
|
|
#define SW_TMAP_TX_028_VLD_MASK 0x00000008
|
|
#define SW_TMAP_TX_029_VLD_OFFSET 2
|
|
#define SW_TMAP_TX_029_VLD_MASK 0x00000004
|
|
#define SW_TMAP_TX_030_VLD_OFFSET 1
|
|
#define SW_TMAP_TX_030_VLD_MASK 0x00000002
|
|
#define SW_TMAP_TX_031_VLD_OFFSET 0
|
|
#define SW_TMAP_TX_031_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_VLD_CTRL_1_ADDR 0x1004
|
|
#define SW_TMAP_TX_032_VLD_OFFSET 31
|
|
#define SW_TMAP_TX_032_VLD_MASK 0x80000000
|
|
#define SW_TMAP_TX_033_VLD_OFFSET 30
|
|
#define SW_TMAP_TX_033_VLD_MASK 0x40000000
|
|
#define SW_TMAP_TX_034_VLD_OFFSET 29
|
|
#define SW_TMAP_TX_034_VLD_MASK 0x20000000
|
|
#define SW_TMAP_TX_035_VLD_OFFSET 28
|
|
#define SW_TMAP_TX_035_VLD_MASK 0x10000000
|
|
#define SW_TMAP_TX_036_VLD_OFFSET 27
|
|
#define SW_TMAP_TX_036_VLD_MASK 0x08000000
|
|
#define SW_TMAP_TX_037_VLD_OFFSET 26
|
|
#define SW_TMAP_TX_037_VLD_MASK 0x04000000
|
|
#define SW_TMAP_TX_038_VLD_OFFSET 25
|
|
#define SW_TMAP_TX_038_VLD_MASK 0x02000000
|
|
#define SW_TMAP_TX_039_VLD_OFFSET 24
|
|
#define SW_TMAP_TX_039_VLD_MASK 0x01000000
|
|
#define SW_TMAP_TX_040_VLD_OFFSET 23
|
|
#define SW_TMAP_TX_040_VLD_MASK 0x00800000
|
|
#define SW_TMAP_TX_041_VLD_OFFSET 22
|
|
#define SW_TMAP_TX_041_VLD_MASK 0x00400000
|
|
#define SW_TMAP_TX_042_VLD_OFFSET 21
|
|
#define SW_TMAP_TX_042_VLD_MASK 0x00200000
|
|
#define SW_TMAP_TX_043_VLD_OFFSET 20
|
|
#define SW_TMAP_TX_043_VLD_MASK 0x00100000
|
|
#define SW_TMAP_TX_044_VLD_OFFSET 19
|
|
#define SW_TMAP_TX_044_VLD_MASK 0x00080000
|
|
#define SW_TMAP_TX_045_VLD_OFFSET 18
|
|
#define SW_TMAP_TX_045_VLD_MASK 0x00040000
|
|
#define SW_TMAP_TX_046_VLD_OFFSET 17
|
|
#define SW_TMAP_TX_046_VLD_MASK 0x00020000
|
|
#define SW_TMAP_TX_047_VLD_OFFSET 16
|
|
#define SW_TMAP_TX_047_VLD_MASK 0x00010000
|
|
#define SW_TMAP_TX_048_VLD_OFFSET 15
|
|
#define SW_TMAP_TX_048_VLD_MASK 0x00008000
|
|
#define SW_TMAP_TX_049_VLD_OFFSET 14
|
|
#define SW_TMAP_TX_049_VLD_MASK 0x00004000
|
|
#define SW_TMAP_TX_050_VLD_OFFSET 13
|
|
#define SW_TMAP_TX_050_VLD_MASK 0x00002000
|
|
#define SW_TMAP_TX_051_VLD_OFFSET 12
|
|
#define SW_TMAP_TX_051_VLD_MASK 0x00001000
|
|
#define SW_TMAP_TX_052_VLD_OFFSET 11
|
|
#define SW_TMAP_TX_052_VLD_MASK 0x00000800
|
|
#define SW_TMAP_TX_053_VLD_OFFSET 10
|
|
#define SW_TMAP_TX_053_VLD_MASK 0x00000400
|
|
#define SW_TMAP_TX_054_VLD_OFFSET 9
|
|
#define SW_TMAP_TX_054_VLD_MASK 0x00000200
|
|
#define SW_TMAP_TX_055_VLD_OFFSET 8
|
|
#define SW_TMAP_TX_055_VLD_MASK 0x00000100
|
|
#define SW_TMAP_TX_056_VLD_OFFSET 7
|
|
#define SW_TMAP_TX_056_VLD_MASK 0x00000080
|
|
#define SW_TMAP_TX_057_VLD_OFFSET 6
|
|
#define SW_TMAP_TX_057_VLD_MASK 0x00000040
|
|
#define SW_TMAP_TX_058_VLD_OFFSET 5
|
|
#define SW_TMAP_TX_058_VLD_MASK 0x00000020
|
|
#define SW_TMAP_TX_059_VLD_OFFSET 4
|
|
#define SW_TMAP_TX_059_VLD_MASK 0x00000010
|
|
#define SW_TMAP_TX_060_VLD_OFFSET 3
|
|
#define SW_TMAP_TX_060_VLD_MASK 0x00000008
|
|
#define SW_TMAP_TX_061_VLD_OFFSET 2
|
|
#define SW_TMAP_TX_061_VLD_MASK 0x00000004
|
|
#define SW_TMAP_TX_062_VLD_OFFSET 1
|
|
#define SW_TMAP_TX_062_VLD_MASK 0x00000002
|
|
#define SW_TMAP_TX_063_VLD_OFFSET 0
|
|
#define SW_TMAP_TX_063_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_VLD_CTRL_2_ADDR 0x1008
|
|
#define SW_TMAP_TX_064_VLD_OFFSET 31
|
|
#define SW_TMAP_TX_064_VLD_MASK 0x80000000
|
|
#define SW_TMAP_TX_065_VLD_OFFSET 30
|
|
#define SW_TMAP_TX_065_VLD_MASK 0x40000000
|
|
#define SW_TMAP_TX_066_VLD_OFFSET 29
|
|
#define SW_TMAP_TX_066_VLD_MASK 0x20000000
|
|
#define SW_TMAP_TX_067_VLD_OFFSET 28
|
|
#define SW_TMAP_TX_067_VLD_MASK 0x10000000
|
|
#define SW_TMAP_TX_068_VLD_OFFSET 27
|
|
#define SW_TMAP_TX_068_VLD_MASK 0x08000000
|
|
#define SW_TMAP_TX_069_VLD_OFFSET 26
|
|
#define SW_TMAP_TX_069_VLD_MASK 0x04000000
|
|
#define SW_TMAP_TX_070_VLD_OFFSET 25
|
|
#define SW_TMAP_TX_070_VLD_MASK 0x02000000
|
|
#define SW_TMAP_TX_071_VLD_OFFSET 24
|
|
#define SW_TMAP_TX_071_VLD_MASK 0x01000000
|
|
#define SW_TMAP_TX_072_VLD_OFFSET 23
|
|
#define SW_TMAP_TX_072_VLD_MASK 0x00800000
|
|
#define SW_TMAP_TX_073_VLD_OFFSET 22
|
|
#define SW_TMAP_TX_073_VLD_MASK 0x00400000
|
|
#define SW_TMAP_TX_074_VLD_OFFSET 21
|
|
#define SW_TMAP_TX_074_VLD_MASK 0x00200000
|
|
#define SW_TMAP_TX_075_VLD_OFFSET 20
|
|
#define SW_TMAP_TX_075_VLD_MASK 0x00100000
|
|
#define SW_TMAP_TX_076_VLD_OFFSET 19
|
|
#define SW_TMAP_TX_076_VLD_MASK 0x00080000
|
|
#define SW_TMAP_TX_077_VLD_OFFSET 18
|
|
#define SW_TMAP_TX_077_VLD_MASK 0x00040000
|
|
#define SW_TMAP_TX_078_VLD_OFFSET 17
|
|
#define SW_TMAP_TX_078_VLD_MASK 0x00020000
|
|
#define SW_TMAP_TX_079_VLD_OFFSET 16
|
|
#define SW_TMAP_TX_079_VLD_MASK 0x00010000
|
|
#define SW_TMAP_TX_080_VLD_OFFSET 15
|
|
#define SW_TMAP_TX_080_VLD_MASK 0x00008000
|
|
#define SW_TMAP_TX_081_VLD_OFFSET 14
|
|
#define SW_TMAP_TX_081_VLD_MASK 0x00004000
|
|
#define SW_TMAP_TX_082_VLD_OFFSET 13
|
|
#define SW_TMAP_TX_082_VLD_MASK 0x00002000
|
|
#define SW_TMAP_TX_083_VLD_OFFSET 12
|
|
#define SW_TMAP_TX_083_VLD_MASK 0x00001000
|
|
#define SW_TMAP_TX_084_VLD_OFFSET 11
|
|
#define SW_TMAP_TX_084_VLD_MASK 0x00000800
|
|
#define SW_TMAP_TX_085_VLD_OFFSET 10
|
|
#define SW_TMAP_TX_085_VLD_MASK 0x00000400
|
|
#define SW_TMAP_TX_086_VLD_OFFSET 9
|
|
#define SW_TMAP_TX_086_VLD_MASK 0x00000200
|
|
#define SW_TMAP_TX_087_VLD_OFFSET 8
|
|
#define SW_TMAP_TX_087_VLD_MASK 0x00000100
|
|
#define SW_TMAP_TX_088_VLD_OFFSET 7
|
|
#define SW_TMAP_TX_088_VLD_MASK 0x00000080
|
|
#define SW_TMAP_TX_089_VLD_OFFSET 6
|
|
#define SW_TMAP_TX_089_VLD_MASK 0x00000040
|
|
#define SW_TMAP_TX_090_VLD_OFFSET 5
|
|
#define SW_TMAP_TX_090_VLD_MASK 0x00000020
|
|
#define SW_TMAP_TX_091_VLD_OFFSET 4
|
|
#define SW_TMAP_TX_091_VLD_MASK 0x00000010
|
|
#define SW_TMAP_TX_092_VLD_OFFSET 3
|
|
#define SW_TMAP_TX_092_VLD_MASK 0x00000008
|
|
#define SW_TMAP_TX_093_VLD_OFFSET 2
|
|
#define SW_TMAP_TX_093_VLD_MASK 0x00000004
|
|
#define SW_TMAP_TX_094_VLD_OFFSET 1
|
|
#define SW_TMAP_TX_094_VLD_MASK 0x00000002
|
|
#define SW_TMAP_TX_095_VLD_OFFSET 0
|
|
#define SW_TMAP_TX_095_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_VLD_CTRL_3_ADDR 0x100c
|
|
#define SW_TMAP_TX_096_VLD_OFFSET 31
|
|
#define SW_TMAP_TX_096_VLD_MASK 0x80000000
|
|
#define SW_TMAP_TX_097_VLD_OFFSET 30
|
|
#define SW_TMAP_TX_097_VLD_MASK 0x40000000
|
|
#define SW_TMAP_TX_098_VLD_OFFSET 29
|
|
#define SW_TMAP_TX_098_VLD_MASK 0x20000000
|
|
#define SW_TMAP_TX_099_VLD_OFFSET 28
|
|
#define SW_TMAP_TX_099_VLD_MASK 0x10000000
|
|
#define SW_TMAP_TX_100_VLD_OFFSET 27
|
|
#define SW_TMAP_TX_100_VLD_MASK 0x08000000
|
|
#define SW_TMAP_TX_101_VLD_OFFSET 26
|
|
#define SW_TMAP_TX_101_VLD_MASK 0x04000000
|
|
#define SW_TMAP_TX_102_VLD_OFFSET 25
|
|
#define SW_TMAP_TX_102_VLD_MASK 0x02000000
|
|
#define SW_TMAP_TX_103_VLD_OFFSET 24
|
|
#define SW_TMAP_TX_103_VLD_MASK 0x01000000
|
|
#define SW_TMAP_TX_104_VLD_OFFSET 23
|
|
#define SW_TMAP_TX_104_VLD_MASK 0x00800000
|
|
#define SW_TMAP_TX_105_VLD_OFFSET 22
|
|
#define SW_TMAP_TX_105_VLD_MASK 0x00400000
|
|
#define SW_TMAP_TX_106_VLD_OFFSET 21
|
|
#define SW_TMAP_TX_106_VLD_MASK 0x00200000
|
|
#define SW_TMAP_TX_107_VLD_OFFSET 20
|
|
#define SW_TMAP_TX_107_VLD_MASK 0x00100000
|
|
#define SW_TMAP_TX_108_VLD_OFFSET 19
|
|
#define SW_TMAP_TX_108_VLD_MASK 0x00080000
|
|
#define SW_TMAP_TX_109_VLD_OFFSET 18
|
|
#define SW_TMAP_TX_109_VLD_MASK 0x00040000
|
|
#define SW_TMAP_TX_110_VLD_OFFSET 17
|
|
#define SW_TMAP_TX_110_VLD_MASK 0x00020000
|
|
#define SW_TMAP_TX_111_VLD_OFFSET 16
|
|
#define SW_TMAP_TX_111_VLD_MASK 0x00010000
|
|
#define SW_TMAP_TX_112_VLD_OFFSET 15
|
|
#define SW_TMAP_TX_112_VLD_MASK 0x00008000
|
|
#define SW_TMAP_TX_113_VLD_OFFSET 14
|
|
#define SW_TMAP_TX_113_VLD_MASK 0x00004000
|
|
#define SW_TMAP_TX_114_VLD_OFFSET 13
|
|
#define SW_TMAP_TX_114_VLD_MASK 0x00002000
|
|
#define SW_TMAP_TX_115_VLD_OFFSET 12
|
|
#define SW_TMAP_TX_115_VLD_MASK 0x00001000
|
|
#define SW_TMAP_TX_116_VLD_OFFSET 11
|
|
#define SW_TMAP_TX_116_VLD_MASK 0x00000800
|
|
#define SW_TMAP_TX_117_VLD_OFFSET 10
|
|
#define SW_TMAP_TX_117_VLD_MASK 0x00000400
|
|
#define SW_TMAP_TX_118_VLD_OFFSET 9
|
|
#define SW_TMAP_TX_118_VLD_MASK 0x00000200
|
|
#define SW_TMAP_TX_119_VLD_OFFSET 8
|
|
#define SW_TMAP_TX_119_VLD_MASK 0x00000100
|
|
#define SW_TMAP_TX_120_VLD_OFFSET 7
|
|
#define SW_TMAP_TX_120_VLD_MASK 0x00000080
|
|
#define SW_TMAP_TX_121_VLD_OFFSET 6
|
|
#define SW_TMAP_TX_121_VLD_MASK 0x00000040
|
|
#define SW_TMAP_TX_122_VLD_OFFSET 5
|
|
#define SW_TMAP_TX_122_VLD_MASK 0x00000020
|
|
#define SW_TMAP_TX_123_VLD_OFFSET 4
|
|
#define SW_TMAP_TX_123_VLD_MASK 0x00000010
|
|
#define SW_TMAP_TX_124_VLD_OFFSET 3
|
|
#define SW_TMAP_TX_124_VLD_MASK 0x00000008
|
|
#define SW_TMAP_TX_125_VLD_OFFSET 2
|
|
#define SW_TMAP_TX_125_VLD_MASK 0x00000004
|
|
#define SW_TMAP_TX_126_VLD_OFFSET 1
|
|
#define SW_TMAP_TX_126_VLD_MASK 0x00000002
|
|
#define SW_TMAP_TX_127_VLD_OFFSET 0
|
|
#define SW_TMAP_TX_127_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_0_ADDR 0x1010
|
|
#define SW_TMAP_TX_000_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_000_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_001_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_001_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_002_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_002_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_003_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_003_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_1_ADDR 0x1014
|
|
#define SW_TMAP_TX_004_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_004_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_005_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_005_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_006_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_006_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_007_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_007_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_2_ADDR 0x1018
|
|
#define SW_TMAP_TX_008_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_008_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_009_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_009_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_010_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_010_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_011_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_011_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_3_ADDR 0x101c
|
|
#define SW_TMAP_TX_012_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_012_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_013_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_013_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_014_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_014_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_015_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_015_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_4_ADDR 0x1020
|
|
#define SW_TMAP_TX_016_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_016_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_017_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_017_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_018_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_018_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_019_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_019_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_5_ADDR 0x1024
|
|
#define SW_TMAP_TX_020_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_020_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_021_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_021_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_022_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_022_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_023_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_023_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_6_ADDR 0x1028
|
|
#define SW_TMAP_TX_024_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_024_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_025_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_025_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_026_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_026_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_027_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_027_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_7_ADDR 0x102c
|
|
#define SW_TMAP_TX_028_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_028_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_029_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_029_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_030_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_030_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_031_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_031_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_8_ADDR 0x1030
|
|
#define SW_TMAP_TX_032_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_032_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_033_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_033_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_034_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_034_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_035_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_035_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_9_ADDR 0x1034
|
|
#define SW_TMAP_TX_036_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_036_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_037_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_037_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_038_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_038_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_039_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_039_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_10_ADDR 0x1038
|
|
#define SW_TMAP_TX_040_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_040_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_041_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_041_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_042_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_042_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_043_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_043_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_11_ADDR 0x103c
|
|
#define SW_TMAP_TX_044_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_044_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_045_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_045_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_046_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_046_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_047_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_047_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_12_ADDR 0x1040
|
|
#define SW_TMAP_TX_048_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_048_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_049_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_049_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_050_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_050_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_051_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_051_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_13_ADDR 0x1044
|
|
#define SW_TMAP_TX_052_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_052_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_053_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_053_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_054_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_054_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_055_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_055_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_14_ADDR 0x1048
|
|
#define SW_TMAP_TX_056_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_056_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_057_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_057_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_058_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_058_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_059_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_059_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_15_ADDR 0x104c
|
|
#define SW_TMAP_TX_060_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_060_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_061_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_061_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_062_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_062_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_063_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_063_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_16_ADDR 0x1050
|
|
#define SW_TMAP_TX_064_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_064_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_065_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_065_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_066_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_066_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_067_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_067_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_17_ADDR 0x1054
|
|
#define SW_TMAP_TX_068_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_068_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_069_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_069_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_070_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_070_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_071_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_071_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_18_ADDR 0x1058
|
|
#define SW_TMAP_TX_072_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_072_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_073_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_073_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_074_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_074_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_075_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_075_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_19_ADDR 0x105c
|
|
#define SW_TMAP_TX_076_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_076_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_077_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_077_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_078_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_078_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_079_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_079_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_20_ADDR 0x1060
|
|
#define SW_TMAP_TX_080_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_080_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_081_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_081_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_082_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_082_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_083_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_083_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_21_ADDR 0x1064
|
|
#define SW_TMAP_TX_084_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_084_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_085_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_085_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_086_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_086_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_087_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_087_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_22_ADDR 0x1068
|
|
#define SW_TMAP_TX_088_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_088_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_089_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_089_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_090_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_090_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_091_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_091_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_23_ADDR 0x106c
|
|
#define SW_TMAP_TX_092_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_092_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_093_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_093_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_094_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_094_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_095_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_095_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_24_ADDR 0x1070
|
|
#define SW_TMAP_TX_096_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_096_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_097_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_097_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_098_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_098_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_099_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_099_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_25_ADDR 0x1074
|
|
#define SW_TMAP_TX_100_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_100_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_101_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_101_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_102_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_102_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_103_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_103_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_26_ADDR 0x1078
|
|
#define SW_TMAP_TX_104_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_104_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_105_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_105_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_106_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_106_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_107_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_107_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_27_ADDR 0x107c
|
|
#define SW_TMAP_TX_108_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_108_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_109_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_109_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_110_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_110_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_111_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_111_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_28_ADDR 0x1080
|
|
#define SW_TMAP_TX_112_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_112_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_113_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_113_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_114_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_114_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_115_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_115_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_29_ADDR 0x1084
|
|
#define SW_TMAP_TX_116_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_116_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_117_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_117_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_118_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_118_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_119_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_119_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_30_ADDR 0x1088
|
|
#define SW_TMAP_TX_120_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_120_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_121_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_121_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_122_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_122_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_123_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_123_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_DTEI_CTRL_31_ADDR 0x108c
|
|
#define SW_TMAP_TX_124_DTEI_OFFSET 24
|
|
#define SW_TMAP_TX_124_DTEI_MASK 0xFF000000
|
|
#define SW_TMAP_TX_125_DTEI_OFFSET 16
|
|
#define SW_TMAP_TX_125_DTEI_MASK 0x00FF0000
|
|
#define SW_TMAP_TX_126_DTEI_OFFSET 8
|
|
#define SW_TMAP_TX_126_DTEI_MASK 0x0000FF00
|
|
#define SW_TMAP_TX_127_DTEI_OFFSET 0
|
|
#define SW_TMAP_TX_127_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_0_ADDR 0x1090
|
|
#define SW_TMAP_TX_000_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_000_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_001_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_001_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_002_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_002_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_003_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_003_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_1_ADDR 0x1094
|
|
#define SW_TMAP_TX_004_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_004_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_005_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_005_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_006_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_006_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_007_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_007_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_2_ADDR 0x1098
|
|
#define SW_TMAP_TX_008_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_008_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_009_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_009_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_010_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_010_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_011_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_011_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_3_ADDR 0x109c
|
|
#define SW_TMAP_TX_012_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_012_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_013_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_013_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_014_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_014_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_015_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_015_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_4_ADDR 0x10a0
|
|
#define SW_TMAP_TX_016_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_016_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_017_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_017_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_018_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_018_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_019_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_019_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_5_ADDR 0x10a4
|
|
#define SW_TMAP_TX_020_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_020_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_021_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_021_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_022_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_022_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_023_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_023_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_6_ADDR 0x10a8
|
|
#define SW_TMAP_TX_024_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_024_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_025_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_025_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_026_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_026_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_027_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_027_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_7_ADDR 0x10ac
|
|
#define SW_TMAP_TX_028_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_028_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_029_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_029_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_030_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_030_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_031_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_031_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_8_ADDR 0x10b0
|
|
#define SW_TMAP_TX_032_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_032_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_033_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_033_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_034_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_034_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_035_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_035_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_9_ADDR 0x10b4
|
|
#define SW_TMAP_TX_036_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_036_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_037_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_037_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_038_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_038_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_039_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_039_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_10_ADDR 0x10b8
|
|
#define SW_TMAP_TX_040_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_040_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_041_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_041_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_042_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_042_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_043_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_043_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_11_ADDR 0x10bc
|
|
#define SW_TMAP_TX_044_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_044_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_045_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_045_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_046_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_046_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_047_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_047_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_12_ADDR 0x10c0
|
|
#define SW_TMAP_TX_048_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_048_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_049_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_049_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_050_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_050_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_051_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_051_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_13_ADDR 0x10c4
|
|
#define SW_TMAP_TX_052_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_052_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_053_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_053_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_054_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_054_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_055_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_055_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_14_ADDR 0x10c8
|
|
#define SW_TMAP_TX_056_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_056_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_057_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_057_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_058_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_058_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_059_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_059_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_15_ADDR 0x10cc
|
|
#define SW_TMAP_TX_060_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_060_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_061_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_061_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_062_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_062_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_063_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_063_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_16_ADDR 0x10d0
|
|
#define SW_TMAP_TX_064_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_064_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_065_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_065_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_066_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_066_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_067_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_067_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_17_ADDR 0x10d4
|
|
#define SW_TMAP_TX_068_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_068_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_069_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_069_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_070_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_070_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_071_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_071_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_18_ADDR 0x10d8
|
|
#define SW_TMAP_TX_072_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_072_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_073_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_073_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_074_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_074_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_075_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_075_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_19_ADDR 0x10dc
|
|
#define SW_TMAP_TX_076_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_076_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_077_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_077_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_078_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_078_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_079_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_079_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_20_ADDR 0x10e0
|
|
#define SW_TMAP_TX_080_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_080_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_081_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_081_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_082_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_082_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_083_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_083_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_21_ADDR 0x10e4
|
|
#define SW_TMAP_TX_084_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_084_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_085_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_085_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_086_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_086_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_087_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_087_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_22_ADDR 0x10e8
|
|
#define SW_TMAP_TX_088_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_088_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_089_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_089_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_090_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_090_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_091_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_091_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_23_ADDR 0x10ec
|
|
#define SW_TMAP_TX_092_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_092_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_093_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_093_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_094_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_094_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_095_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_095_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_24_ADDR 0x10f0
|
|
#define SW_TMAP_TX_096_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_096_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_097_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_097_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_098_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_098_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_099_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_099_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_25_ADDR 0x10f4
|
|
#define SW_TMAP_TX_100_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_100_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_101_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_101_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_102_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_102_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_103_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_103_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_26_ADDR 0x10f8
|
|
#define SW_TMAP_TX_104_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_104_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_105_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_105_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_106_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_106_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_107_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_107_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_27_ADDR 0x10fc
|
|
#define SW_TMAP_TX_108_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_108_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_109_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_109_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_110_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_110_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_111_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_111_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_28_ADDR 0x1100
|
|
#define SW_TMAP_TX_112_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_112_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_113_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_113_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_114_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_114_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_115_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_115_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_29_ADDR 0x1104
|
|
#define SW_TMAP_TX_116_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_116_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_117_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_117_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_118_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_118_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_119_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_119_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_30_ADDR 0x1108
|
|
#define SW_TMAP_TX_120_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_120_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_121_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_121_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_122_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_122_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_123_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_123_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_TX_TMI_CTRL_31_ADDR 0x110c
|
|
#define SW_TMAP_TX_124_TMI_OFFSET 24
|
|
#define SW_TMAP_TX_124_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_TX_125_TMI_OFFSET 16
|
|
#define SW_TMAP_TX_125_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_TX_126_TMI_OFFSET 8
|
|
#define SW_TMAP_TX_126_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_TX_127_TMI_OFFSET 0
|
|
#define SW_TMAP_TX_127_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_SELF_TEI_CTRL_ADDR 0x1110
|
|
#define SW_TMAP_TX_STEI_OFFSET 8
|
|
#define SW_TMAP_TX_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_DTEI_OFFSET 0
|
|
#define SW_TMAP_RX_DTEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_VLD_CTRL_0_ADDR 0x1200
|
|
#define SW_TMAP_RX_000_VLD_OFFSET 31
|
|
#define SW_TMAP_RX_000_VLD_MASK 0x80000000
|
|
#define SW_TMAP_RX_001_VLD_OFFSET 30
|
|
#define SW_TMAP_RX_001_VLD_MASK 0x40000000
|
|
#define SW_TMAP_RX_002_VLD_OFFSET 29
|
|
#define SW_TMAP_RX_002_VLD_MASK 0x20000000
|
|
#define SW_TMAP_RX_003_VLD_OFFSET 28
|
|
#define SW_TMAP_RX_003_VLD_MASK 0x10000000
|
|
#define SW_TMAP_RX_004_VLD_OFFSET 27
|
|
#define SW_TMAP_RX_004_VLD_MASK 0x08000000
|
|
#define SW_TMAP_RX_005_VLD_OFFSET 26
|
|
#define SW_TMAP_RX_005_VLD_MASK 0x04000000
|
|
#define SW_TMAP_RX_006_VLD_OFFSET 25
|
|
#define SW_TMAP_RX_006_VLD_MASK 0x02000000
|
|
#define SW_TMAP_RX_007_VLD_OFFSET 24
|
|
#define SW_TMAP_RX_007_VLD_MASK 0x01000000
|
|
#define SW_TMAP_RX_008_VLD_OFFSET 23
|
|
#define SW_TMAP_RX_008_VLD_MASK 0x00800000
|
|
#define SW_TMAP_RX_009_VLD_OFFSET 22
|
|
#define SW_TMAP_RX_009_VLD_MASK 0x00400000
|
|
#define SW_TMAP_RX_010_VLD_OFFSET 21
|
|
#define SW_TMAP_RX_010_VLD_MASK 0x00200000
|
|
#define SW_TMAP_RX_011_VLD_OFFSET 20
|
|
#define SW_TMAP_RX_011_VLD_MASK 0x00100000
|
|
#define SW_TMAP_RX_012_VLD_OFFSET 19
|
|
#define SW_TMAP_RX_012_VLD_MASK 0x00080000
|
|
#define SW_TMAP_RX_013_VLD_OFFSET 18
|
|
#define SW_TMAP_RX_013_VLD_MASK 0x00040000
|
|
#define SW_TMAP_RX_014_VLD_OFFSET 17
|
|
#define SW_TMAP_RX_014_VLD_MASK 0x00020000
|
|
#define SW_TMAP_RX_015_VLD_OFFSET 16
|
|
#define SW_TMAP_RX_015_VLD_MASK 0x00010000
|
|
#define SW_TMAP_RX_016_VLD_OFFSET 15
|
|
#define SW_TMAP_RX_016_VLD_MASK 0x00008000
|
|
#define SW_TMAP_RX_017_VLD_OFFSET 14
|
|
#define SW_TMAP_RX_017_VLD_MASK 0x00004000
|
|
#define SW_TMAP_RX_018_VLD_OFFSET 13
|
|
#define SW_TMAP_RX_018_VLD_MASK 0x00002000
|
|
#define SW_TMAP_RX_019_VLD_OFFSET 12
|
|
#define SW_TMAP_RX_019_VLD_MASK 0x00001000
|
|
#define SW_TMAP_RX_020_VLD_OFFSET 11
|
|
#define SW_TMAP_RX_020_VLD_MASK 0x00000800
|
|
#define SW_TMAP_RX_021_VLD_OFFSET 10
|
|
#define SW_TMAP_RX_021_VLD_MASK 0x00000400
|
|
#define SW_TMAP_RX_022_VLD_OFFSET 9
|
|
#define SW_TMAP_RX_022_VLD_MASK 0x00000200
|
|
#define SW_TMAP_RX_023_VLD_OFFSET 8
|
|
#define SW_TMAP_RX_023_VLD_MASK 0x00000100
|
|
#define SW_TMAP_RX_024_VLD_OFFSET 7
|
|
#define SW_TMAP_RX_024_VLD_MASK 0x00000080
|
|
#define SW_TMAP_RX_025_VLD_OFFSET 6
|
|
#define SW_TMAP_RX_025_VLD_MASK 0x00000040
|
|
#define SW_TMAP_RX_026_VLD_OFFSET 5
|
|
#define SW_TMAP_RX_026_VLD_MASK 0x00000020
|
|
#define SW_TMAP_RX_027_VLD_OFFSET 4
|
|
#define SW_TMAP_RX_027_VLD_MASK 0x00000010
|
|
#define SW_TMAP_RX_028_VLD_OFFSET 3
|
|
#define SW_TMAP_RX_028_VLD_MASK 0x00000008
|
|
#define SW_TMAP_RX_029_VLD_OFFSET 2
|
|
#define SW_TMAP_RX_029_VLD_MASK 0x00000004
|
|
#define SW_TMAP_RX_030_VLD_OFFSET 1
|
|
#define SW_TMAP_RX_030_VLD_MASK 0x00000002
|
|
#define SW_TMAP_RX_031_VLD_OFFSET 0
|
|
#define SW_TMAP_RX_031_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_VLD_CTRL_1_ADDR 0x1204
|
|
#define SW_TMAP_RX_032_VLD_OFFSET 31
|
|
#define SW_TMAP_RX_032_VLD_MASK 0x80000000
|
|
#define SW_TMAP_RX_033_VLD_OFFSET 30
|
|
#define SW_TMAP_RX_033_VLD_MASK 0x40000000
|
|
#define SW_TMAP_RX_034_VLD_OFFSET 29
|
|
#define SW_TMAP_RX_034_VLD_MASK 0x20000000
|
|
#define SW_TMAP_RX_035_VLD_OFFSET 28
|
|
#define SW_TMAP_RX_035_VLD_MASK 0x10000000
|
|
#define SW_TMAP_RX_036_VLD_OFFSET 27
|
|
#define SW_TMAP_RX_036_VLD_MASK 0x08000000
|
|
#define SW_TMAP_RX_037_VLD_OFFSET 26
|
|
#define SW_TMAP_RX_037_VLD_MASK 0x04000000
|
|
#define SW_TMAP_RX_038_VLD_OFFSET 25
|
|
#define SW_TMAP_RX_038_VLD_MASK 0x02000000
|
|
#define SW_TMAP_RX_039_VLD_OFFSET 24
|
|
#define SW_TMAP_RX_039_VLD_MASK 0x01000000
|
|
#define SW_TMAP_RX_040_VLD_OFFSET 23
|
|
#define SW_TMAP_RX_040_VLD_MASK 0x00800000
|
|
#define SW_TMAP_RX_041_VLD_OFFSET 22
|
|
#define SW_TMAP_RX_041_VLD_MASK 0x00400000
|
|
#define SW_TMAP_RX_042_VLD_OFFSET 21
|
|
#define SW_TMAP_RX_042_VLD_MASK 0x00200000
|
|
#define SW_TMAP_RX_043_VLD_OFFSET 20
|
|
#define SW_TMAP_RX_043_VLD_MASK 0x00100000
|
|
#define SW_TMAP_RX_044_VLD_OFFSET 19
|
|
#define SW_TMAP_RX_044_VLD_MASK 0x00080000
|
|
#define SW_TMAP_RX_045_VLD_OFFSET 18
|
|
#define SW_TMAP_RX_045_VLD_MASK 0x00040000
|
|
#define SW_TMAP_RX_046_VLD_OFFSET 17
|
|
#define SW_TMAP_RX_046_VLD_MASK 0x00020000
|
|
#define SW_TMAP_RX_047_VLD_OFFSET 16
|
|
#define SW_TMAP_RX_047_VLD_MASK 0x00010000
|
|
#define SW_TMAP_RX_048_VLD_OFFSET 15
|
|
#define SW_TMAP_RX_048_VLD_MASK 0x00008000
|
|
#define SW_TMAP_RX_049_VLD_OFFSET 14
|
|
#define SW_TMAP_RX_049_VLD_MASK 0x00004000
|
|
#define SW_TMAP_RX_050_VLD_OFFSET 13
|
|
#define SW_TMAP_RX_050_VLD_MASK 0x00002000
|
|
#define SW_TMAP_RX_051_VLD_OFFSET 12
|
|
#define SW_TMAP_RX_051_VLD_MASK 0x00001000
|
|
#define SW_TMAP_RX_052_VLD_OFFSET 11
|
|
#define SW_TMAP_RX_052_VLD_MASK 0x00000800
|
|
#define SW_TMAP_RX_053_VLD_OFFSET 10
|
|
#define SW_TMAP_RX_053_VLD_MASK 0x00000400
|
|
#define SW_TMAP_RX_054_VLD_OFFSET 9
|
|
#define SW_TMAP_RX_054_VLD_MASK 0x00000200
|
|
#define SW_TMAP_RX_055_VLD_OFFSET 8
|
|
#define SW_TMAP_RX_055_VLD_MASK 0x00000100
|
|
#define SW_TMAP_RX_056_VLD_OFFSET 7
|
|
#define SW_TMAP_RX_056_VLD_MASK 0x00000080
|
|
#define SW_TMAP_RX_057_VLD_OFFSET 6
|
|
#define SW_TMAP_RX_057_VLD_MASK 0x00000040
|
|
#define SW_TMAP_RX_058_VLD_OFFSET 5
|
|
#define SW_TMAP_RX_058_VLD_MASK 0x00000020
|
|
#define SW_TMAP_RX_059_VLD_OFFSET 4
|
|
#define SW_TMAP_RX_059_VLD_MASK 0x00000010
|
|
#define SW_TMAP_RX_060_VLD_OFFSET 3
|
|
#define SW_TMAP_RX_060_VLD_MASK 0x00000008
|
|
#define SW_TMAP_RX_061_VLD_OFFSET 2
|
|
#define SW_TMAP_RX_061_VLD_MASK 0x00000004
|
|
#define SW_TMAP_RX_062_VLD_OFFSET 1
|
|
#define SW_TMAP_RX_062_VLD_MASK 0x00000002
|
|
#define SW_TMAP_RX_063_VLD_OFFSET 0
|
|
#define SW_TMAP_RX_063_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_VLD_CTRL_2_ADDR 0x1208
|
|
#define SW_TMAP_RX_064_VLD_OFFSET 31
|
|
#define SW_TMAP_RX_064_VLD_MASK 0x80000000
|
|
#define SW_TMAP_RX_065_VLD_OFFSET 30
|
|
#define SW_TMAP_RX_065_VLD_MASK 0x40000000
|
|
#define SW_TMAP_RX_066_VLD_OFFSET 29
|
|
#define SW_TMAP_RX_066_VLD_MASK 0x20000000
|
|
#define SW_TMAP_RX_067_VLD_OFFSET 28
|
|
#define SW_TMAP_RX_067_VLD_MASK 0x10000000
|
|
#define SW_TMAP_RX_068_VLD_OFFSET 27
|
|
#define SW_TMAP_RX_068_VLD_MASK 0x08000000
|
|
#define SW_TMAP_RX_069_VLD_OFFSET 26
|
|
#define SW_TMAP_RX_069_VLD_MASK 0x04000000
|
|
#define SW_TMAP_RX_070_VLD_OFFSET 25
|
|
#define SW_TMAP_RX_070_VLD_MASK 0x02000000
|
|
#define SW_TMAP_RX_071_VLD_OFFSET 24
|
|
#define SW_TMAP_RX_071_VLD_MASK 0x01000000
|
|
#define SW_TMAP_RX_072_VLD_OFFSET 23
|
|
#define SW_TMAP_RX_072_VLD_MASK 0x00800000
|
|
#define SW_TMAP_RX_073_VLD_OFFSET 22
|
|
#define SW_TMAP_RX_073_VLD_MASK 0x00400000
|
|
#define SW_TMAP_RX_074_VLD_OFFSET 21
|
|
#define SW_TMAP_RX_074_VLD_MASK 0x00200000
|
|
#define SW_TMAP_RX_075_VLD_OFFSET 20
|
|
#define SW_TMAP_RX_075_VLD_MASK 0x00100000
|
|
#define SW_TMAP_RX_076_VLD_OFFSET 19
|
|
#define SW_TMAP_RX_076_VLD_MASK 0x00080000
|
|
#define SW_TMAP_RX_077_VLD_OFFSET 18
|
|
#define SW_TMAP_RX_077_VLD_MASK 0x00040000
|
|
#define SW_TMAP_RX_078_VLD_OFFSET 17
|
|
#define SW_TMAP_RX_078_VLD_MASK 0x00020000
|
|
#define SW_TMAP_RX_079_VLD_OFFSET 16
|
|
#define SW_TMAP_RX_079_VLD_MASK 0x00010000
|
|
#define SW_TMAP_RX_080_VLD_OFFSET 15
|
|
#define SW_TMAP_RX_080_VLD_MASK 0x00008000
|
|
#define SW_TMAP_RX_081_VLD_OFFSET 14
|
|
#define SW_TMAP_RX_081_VLD_MASK 0x00004000
|
|
#define SW_TMAP_RX_082_VLD_OFFSET 13
|
|
#define SW_TMAP_RX_082_VLD_MASK 0x00002000
|
|
#define SW_TMAP_RX_083_VLD_OFFSET 12
|
|
#define SW_TMAP_RX_083_VLD_MASK 0x00001000
|
|
#define SW_TMAP_RX_084_VLD_OFFSET 11
|
|
#define SW_TMAP_RX_084_VLD_MASK 0x00000800
|
|
#define SW_TMAP_RX_085_VLD_OFFSET 10
|
|
#define SW_TMAP_RX_085_VLD_MASK 0x00000400
|
|
#define SW_TMAP_RX_086_VLD_OFFSET 9
|
|
#define SW_TMAP_RX_086_VLD_MASK 0x00000200
|
|
#define SW_TMAP_RX_087_VLD_OFFSET 8
|
|
#define SW_TMAP_RX_087_VLD_MASK 0x00000100
|
|
#define SW_TMAP_RX_088_VLD_OFFSET 7
|
|
#define SW_TMAP_RX_088_VLD_MASK 0x00000080
|
|
#define SW_TMAP_RX_089_VLD_OFFSET 6
|
|
#define SW_TMAP_RX_089_VLD_MASK 0x00000040
|
|
#define SW_TMAP_RX_090_VLD_OFFSET 5
|
|
#define SW_TMAP_RX_090_VLD_MASK 0x00000020
|
|
#define SW_TMAP_RX_091_VLD_OFFSET 4
|
|
#define SW_TMAP_RX_091_VLD_MASK 0x00000010
|
|
#define SW_TMAP_RX_092_VLD_OFFSET 3
|
|
#define SW_TMAP_RX_092_VLD_MASK 0x00000008
|
|
#define SW_TMAP_RX_093_VLD_OFFSET 2
|
|
#define SW_TMAP_RX_093_VLD_MASK 0x00000004
|
|
#define SW_TMAP_RX_094_VLD_OFFSET 1
|
|
#define SW_TMAP_RX_094_VLD_MASK 0x00000002
|
|
#define SW_TMAP_RX_095_VLD_OFFSET 0
|
|
#define SW_TMAP_RX_095_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_VLD_CTRL_3_ADDR 0x120c
|
|
#define SW_TMAP_RX_096_VLD_OFFSET 31
|
|
#define SW_TMAP_RX_096_VLD_MASK 0x80000000
|
|
#define SW_TMAP_RX_097_VLD_OFFSET 30
|
|
#define SW_TMAP_RX_097_VLD_MASK 0x40000000
|
|
#define SW_TMAP_RX_098_VLD_OFFSET 29
|
|
#define SW_TMAP_RX_098_VLD_MASK 0x20000000
|
|
#define SW_TMAP_RX_099_VLD_OFFSET 28
|
|
#define SW_TMAP_RX_099_VLD_MASK 0x10000000
|
|
#define SW_TMAP_RX_100_VLD_OFFSET 27
|
|
#define SW_TMAP_RX_100_VLD_MASK 0x08000000
|
|
#define SW_TMAP_RX_101_VLD_OFFSET 26
|
|
#define SW_TMAP_RX_101_VLD_MASK 0x04000000
|
|
#define SW_TMAP_RX_102_VLD_OFFSET 25
|
|
#define SW_TMAP_RX_102_VLD_MASK 0x02000000
|
|
#define SW_TMAP_RX_103_VLD_OFFSET 24
|
|
#define SW_TMAP_RX_103_VLD_MASK 0x01000000
|
|
#define SW_TMAP_RX_104_VLD_OFFSET 23
|
|
#define SW_TMAP_RX_104_VLD_MASK 0x00800000
|
|
#define SW_TMAP_RX_105_VLD_OFFSET 22
|
|
#define SW_TMAP_RX_105_VLD_MASK 0x00400000
|
|
#define SW_TMAP_RX_106_VLD_OFFSET 21
|
|
#define SW_TMAP_RX_106_VLD_MASK 0x00200000
|
|
#define SW_TMAP_RX_107_VLD_OFFSET 20
|
|
#define SW_TMAP_RX_107_VLD_MASK 0x00100000
|
|
#define SW_TMAP_RX_108_VLD_OFFSET 19
|
|
#define SW_TMAP_RX_108_VLD_MASK 0x00080000
|
|
#define SW_TMAP_RX_109_VLD_OFFSET 18
|
|
#define SW_TMAP_RX_109_VLD_MASK 0x00040000
|
|
#define SW_TMAP_RX_110_VLD_OFFSET 17
|
|
#define SW_TMAP_RX_110_VLD_MASK 0x00020000
|
|
#define SW_TMAP_RX_111_VLD_OFFSET 16
|
|
#define SW_TMAP_RX_111_VLD_MASK 0x00010000
|
|
#define SW_TMAP_RX_112_VLD_OFFSET 15
|
|
#define SW_TMAP_RX_112_VLD_MASK 0x00008000
|
|
#define SW_TMAP_RX_113_VLD_OFFSET 14
|
|
#define SW_TMAP_RX_113_VLD_MASK 0x00004000
|
|
#define SW_TMAP_RX_114_VLD_OFFSET 13
|
|
#define SW_TMAP_RX_114_VLD_MASK 0x00002000
|
|
#define SW_TMAP_RX_115_VLD_OFFSET 12
|
|
#define SW_TMAP_RX_115_VLD_MASK 0x00001000
|
|
#define SW_TMAP_RX_116_VLD_OFFSET 11
|
|
#define SW_TMAP_RX_116_VLD_MASK 0x00000800
|
|
#define SW_TMAP_RX_117_VLD_OFFSET 10
|
|
#define SW_TMAP_RX_117_VLD_MASK 0x00000400
|
|
#define SW_TMAP_RX_118_VLD_OFFSET 9
|
|
#define SW_TMAP_RX_118_VLD_MASK 0x00000200
|
|
#define SW_TMAP_RX_119_VLD_OFFSET 8
|
|
#define SW_TMAP_RX_119_VLD_MASK 0x00000100
|
|
#define SW_TMAP_RX_120_VLD_OFFSET 7
|
|
#define SW_TMAP_RX_120_VLD_MASK 0x00000080
|
|
#define SW_TMAP_RX_121_VLD_OFFSET 6
|
|
#define SW_TMAP_RX_121_VLD_MASK 0x00000040
|
|
#define SW_TMAP_RX_122_VLD_OFFSET 5
|
|
#define SW_TMAP_RX_122_VLD_MASK 0x00000020
|
|
#define SW_TMAP_RX_123_VLD_OFFSET 4
|
|
#define SW_TMAP_RX_123_VLD_MASK 0x00000010
|
|
#define SW_TMAP_RX_124_VLD_OFFSET 3
|
|
#define SW_TMAP_RX_124_VLD_MASK 0x00000008
|
|
#define SW_TMAP_RX_125_VLD_OFFSET 2
|
|
#define SW_TMAP_RX_125_VLD_MASK 0x00000004
|
|
#define SW_TMAP_RX_126_VLD_OFFSET 1
|
|
#define SW_TMAP_RX_126_VLD_MASK 0x00000002
|
|
#define SW_TMAP_RX_127_VLD_OFFSET 0
|
|
#define SW_TMAP_RX_127_VLD_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_0_ADDR 0x1210
|
|
#define SW_TMAP_RX_000_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_000_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_001_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_001_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_002_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_002_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_003_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_003_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_1_ADDR 0x1214
|
|
#define SW_TMAP_RX_004_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_004_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_005_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_005_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_006_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_006_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_007_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_007_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_2_ADDR 0x1218
|
|
#define SW_TMAP_RX_008_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_008_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_009_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_009_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_010_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_010_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_011_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_011_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_3_ADDR 0x121c
|
|
#define SW_TMAP_RX_012_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_012_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_013_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_013_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_014_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_014_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_015_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_015_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_4_ADDR 0x1220
|
|
#define SW_TMAP_RX_016_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_016_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_017_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_017_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_018_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_018_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_019_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_019_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_5_ADDR 0x1224
|
|
#define SW_TMAP_RX_020_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_020_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_021_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_021_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_022_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_022_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_023_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_023_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_6_ADDR 0x1228
|
|
#define SW_TMAP_RX_024_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_024_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_025_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_025_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_026_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_026_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_027_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_027_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_7_ADDR 0x122c
|
|
#define SW_TMAP_RX_028_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_028_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_029_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_029_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_030_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_030_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_031_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_031_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_8_ADDR 0x1230
|
|
#define SW_TMAP_RX_032_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_032_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_033_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_033_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_034_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_034_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_035_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_035_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_9_ADDR 0x1234
|
|
#define SW_TMAP_RX_036_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_036_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_037_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_037_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_038_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_038_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_039_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_039_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_10_ADDR 0x1238
|
|
#define SW_TMAP_RX_040_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_040_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_041_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_041_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_042_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_042_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_043_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_043_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_11_ADDR 0x123c
|
|
#define SW_TMAP_RX_044_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_044_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_045_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_045_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_046_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_046_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_047_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_047_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_12_ADDR 0x1240
|
|
#define SW_TMAP_RX_048_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_048_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_049_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_049_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_050_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_050_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_051_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_051_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_13_ADDR 0x1244
|
|
#define SW_TMAP_RX_052_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_052_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_053_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_053_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_054_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_054_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_055_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_055_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_14_ADDR 0x1248
|
|
#define SW_TMAP_RX_056_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_056_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_057_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_057_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_058_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_058_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_059_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_059_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_15_ADDR 0x124c
|
|
#define SW_TMAP_RX_060_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_060_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_061_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_061_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_062_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_062_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_063_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_063_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_16_ADDR 0x1250
|
|
#define SW_TMAP_RX_064_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_064_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_065_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_065_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_066_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_066_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_067_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_067_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_17_ADDR 0x1254
|
|
#define SW_TMAP_RX_068_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_068_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_069_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_069_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_070_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_070_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_071_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_071_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_18_ADDR 0x1258
|
|
#define SW_TMAP_RX_072_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_072_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_073_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_073_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_074_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_074_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_075_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_075_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_19_ADDR 0x125c
|
|
#define SW_TMAP_RX_076_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_076_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_077_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_077_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_078_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_078_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_079_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_079_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_20_ADDR 0x1260
|
|
#define SW_TMAP_RX_080_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_080_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_081_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_081_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_082_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_082_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_083_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_083_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_21_ADDR 0x1264
|
|
#define SW_TMAP_RX_084_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_084_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_085_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_085_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_086_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_086_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_087_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_087_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_22_ADDR 0x1268
|
|
#define SW_TMAP_RX_088_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_088_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_089_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_089_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_090_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_090_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_091_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_091_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_23_ADDR 0x126c
|
|
#define SW_TMAP_RX_092_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_092_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_093_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_093_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_094_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_094_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_095_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_095_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_24_ADDR 0x1270
|
|
#define SW_TMAP_RX_096_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_096_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_097_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_097_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_098_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_098_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_099_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_099_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_25_ADDR 0x1274
|
|
#define SW_TMAP_RX_100_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_100_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_101_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_101_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_102_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_102_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_103_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_103_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_26_ADDR 0x1278
|
|
#define SW_TMAP_RX_104_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_104_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_105_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_105_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_106_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_106_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_107_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_107_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_27_ADDR 0x127c
|
|
#define SW_TMAP_RX_108_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_108_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_109_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_109_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_110_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_110_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_111_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_111_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_28_ADDR 0x1280
|
|
#define SW_TMAP_RX_112_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_112_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_113_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_113_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_114_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_114_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_115_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_115_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_29_ADDR 0x1284
|
|
#define SW_TMAP_RX_116_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_116_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_117_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_117_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_118_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_118_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_119_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_119_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_30_ADDR 0x1288
|
|
#define SW_TMAP_RX_120_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_120_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_121_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_121_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_122_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_122_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_123_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_123_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_STEI_CTRL_31_ADDR 0x128c
|
|
#define SW_TMAP_RX_124_STEI_OFFSET 24
|
|
#define SW_TMAP_RX_124_STEI_MASK 0xFF000000
|
|
#define SW_TMAP_RX_125_STEI_OFFSET 16
|
|
#define SW_TMAP_RX_125_STEI_MASK 0x00FF0000
|
|
#define SW_TMAP_RX_126_STEI_OFFSET 8
|
|
#define SW_TMAP_RX_126_STEI_MASK 0x0000FF00
|
|
#define SW_TMAP_RX_127_STEI_OFFSET 0
|
|
#define SW_TMAP_RX_127_STEI_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_0_ADDR 0x1290
|
|
#define SW_TMAP_RX_000_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_000_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_001_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_001_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_002_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_002_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_003_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_003_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_1_ADDR 0x1294
|
|
#define SW_TMAP_RX_004_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_004_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_005_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_005_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_006_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_006_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_007_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_007_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_2_ADDR 0x1298
|
|
#define SW_TMAP_RX_008_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_008_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_009_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_009_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_010_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_010_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_011_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_011_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_3_ADDR 0x129c
|
|
#define SW_TMAP_RX_012_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_012_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_013_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_013_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_014_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_014_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_015_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_015_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_4_ADDR 0x12a0
|
|
#define SW_TMAP_RX_016_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_016_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_017_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_017_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_018_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_018_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_019_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_019_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_5_ADDR 0x12a4
|
|
#define SW_TMAP_RX_020_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_020_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_021_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_021_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_022_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_022_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_023_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_023_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_6_ADDR 0x12a8
|
|
#define SW_TMAP_RX_024_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_024_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_025_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_025_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_026_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_026_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_027_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_027_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_7_ADDR 0x12ac
|
|
#define SW_TMAP_RX_028_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_028_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_029_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_029_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_030_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_030_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_031_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_031_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_8_ADDR 0x12b0
|
|
#define SW_TMAP_RX_032_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_032_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_033_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_033_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_034_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_034_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_035_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_035_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_9_ADDR 0x12b4
|
|
#define SW_TMAP_RX_036_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_036_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_037_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_037_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_038_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_038_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_039_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_039_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_10_ADDR 0x12b8
|
|
#define SW_TMAP_RX_040_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_040_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_041_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_041_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_042_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_042_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_043_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_043_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_11_ADDR 0x12bc
|
|
#define SW_TMAP_RX_044_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_044_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_045_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_045_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_046_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_046_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_047_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_047_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_12_ADDR 0x12c0
|
|
#define SW_TMAP_RX_048_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_048_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_049_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_049_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_050_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_050_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_051_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_051_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_13_ADDR 0x12c4
|
|
#define SW_TMAP_RX_052_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_052_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_053_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_053_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_054_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_054_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_055_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_055_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_14_ADDR 0x12c8
|
|
#define SW_TMAP_RX_056_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_056_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_057_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_057_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_058_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_058_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_059_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_059_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_15_ADDR 0x12cc
|
|
#define SW_TMAP_RX_060_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_060_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_061_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_061_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_062_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_062_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_063_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_063_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_16_ADDR 0x12d0
|
|
#define SW_TMAP_RX_064_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_064_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_065_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_065_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_066_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_066_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_067_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_067_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_17_ADDR 0x12d4
|
|
#define SW_TMAP_RX_068_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_068_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_069_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_069_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_070_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_070_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_071_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_071_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_18_ADDR 0x12d8
|
|
#define SW_TMAP_RX_072_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_072_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_073_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_073_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_074_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_074_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_075_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_075_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_19_ADDR 0x12dc
|
|
#define SW_TMAP_RX_076_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_076_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_077_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_077_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_078_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_078_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_079_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_079_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_20_ADDR 0x12e0
|
|
#define SW_TMAP_RX_080_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_080_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_081_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_081_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_082_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_082_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_083_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_083_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_21_ADDR 0x12e4
|
|
#define SW_TMAP_RX_084_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_084_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_085_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_085_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_086_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_086_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_087_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_087_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_22_ADDR 0x12e8
|
|
#define SW_TMAP_RX_088_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_088_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_089_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_089_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_090_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_090_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_091_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_091_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_23_ADDR 0x12ec
|
|
#define SW_TMAP_RX_092_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_092_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_093_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_093_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_094_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_094_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_095_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_095_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_24_ADDR 0x12f0
|
|
#define SW_TMAP_RX_096_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_096_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_097_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_097_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_098_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_098_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_099_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_099_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_25_ADDR 0x12f4
|
|
#define SW_TMAP_RX_100_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_100_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_101_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_101_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_102_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_102_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_103_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_103_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_26_ADDR 0x12f8
|
|
#define SW_TMAP_RX_104_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_104_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_105_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_105_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_106_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_106_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_107_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_107_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_27_ADDR 0x12fc
|
|
#define SW_TMAP_RX_108_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_108_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_109_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_109_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_110_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_110_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_111_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_111_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_28_ADDR 0x1300
|
|
#define SW_TMAP_RX_112_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_112_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_113_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_113_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_114_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_114_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_115_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_115_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_29_ADDR 0x1304
|
|
#define SW_TMAP_RX_116_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_116_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_117_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_117_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_118_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_118_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_119_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_119_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_30_ADDR 0x1308
|
|
#define SW_TMAP_RX_120_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_120_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_121_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_121_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_122_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_122_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_123_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_123_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TMAP_RX_TMI_CTRL_31_ADDR 0x130c
|
|
#define SW_TMAP_RX_124_TMI_OFFSET 24
|
|
#define SW_TMAP_RX_124_TMI_MASK 0x1F000000
|
|
#define SW_TMAP_RX_125_TMI_OFFSET 16
|
|
#define SW_TMAP_RX_125_TMI_MASK 0x001F0000
|
|
#define SW_TMAP_RX_126_TMI_OFFSET 8
|
|
#define SW_TMAP_RX_126_TMI_MASK 0x00001F00
|
|
#define SW_TMAP_RX_127_TMI_OFFSET 0
|
|
#define SW_TMAP_RX_127_TMI_MASK 0x0000001F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_FORCE_TONE_MAP_ADDR 0x1310
|
|
#define SW_TX_FORCE_RULE_127_MATCH_OFFSET 24
|
|
#define SW_TX_FORCE_RULE_127_MATCH_MASK 0x01000000
|
|
#define SW_TX_FORCE_TONE_MAP_EN_OFFSET 23
|
|
#define SW_TX_FORCE_TONE_MAP_EN_MASK 0x00800000
|
|
#define SW_TX_FORCE_TONE_MAP_MODU_OFFSET 20
|
|
#define SW_TX_FORCE_TONE_MAP_MODU_MASK 0x00700000
|
|
#define SW_TX_FORCE_TONE_MAP_GI_X_OFFSET 18
|
|
#define SW_TX_FORCE_TONE_MAP_GI_X_MASK 0x000C0000
|
|
#define SW_TX_FORCE_TONE_MAP_TURBO_RATE_OFFSET 16
|
|
#define SW_TX_FORCE_TONE_MAP_TURBO_RATE_MASK 0x00030000
|
|
#define SW_TX_FORCE_TONE_MAP_124_MODU_OFFSET 13
|
|
#define SW_TX_FORCE_TONE_MAP_124_MODU_MASK 0x0000E000
|
|
#define SW_TX_FORCE_TONE_MAP_124_EN_OFFSET 12
|
|
#define SW_TX_FORCE_TONE_MAP_124_EN_MASK 0x00001000
|
|
#define SW_TX_FORCE_TONE_MAP_125_MODU_OFFSET 9
|
|
#define SW_TX_FORCE_TONE_MAP_125_MODU_MASK 0x00000E00
|
|
#define SW_TX_FORCE_TONE_MAP_125_EN_OFFSET 8
|
|
#define SW_TX_FORCE_TONE_MAP_125_EN_MASK 0x00000100
|
|
#define SW_TX_FORCE_TONE_MAP_126_MODU_OFFSET 5
|
|
#define SW_TX_FORCE_TONE_MAP_126_MODU_MASK 0x000000E0
|
|
#define SW_TX_FORCE_TONE_MAP_126_EN_OFFSET 4
|
|
#define SW_TX_FORCE_TONE_MAP_126_EN_MASK 0x00000010
|
|
#define SW_TX_FORCE_TONE_MAP_127_MODU_OFFSET 1
|
|
#define SW_TX_FORCE_TONE_MAP_127_MODU_MASK 0x0000000E
|
|
#define SW_TX_FORCE_TONE_MAP_127_EN_OFFSET 0
|
|
#define SW_TX_FORCE_TONE_MAP_127_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_RX_FORCE_TONE_MAP_ADDR 0x1314
|
|
#define SW_RX_FORCE_RULE_127_MATCH_OFFSET 24
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#define SW_RX_FORCE_RULE_127_MATCH_MASK 0x01000000
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#define SW_RX_FORCE_TONE_MAP_EN_OFFSET 23
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#define SW_RX_FORCE_TONE_MAP_EN_MASK 0x00800000
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#define SW_RX_FORCE_TONE_MAP_MODU_OFFSET 20
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#define SW_RX_FORCE_TONE_MAP_MODU_MASK 0x00700000
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#define SW_RX_FORCE_TONE_MAP_GI_X_OFFSET 18
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#define SW_RX_FORCE_TONE_MAP_GI_X_MASK 0x000C0000
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#define SW_RX_FORCE_TONE_MAP_TURBO_RATE_OFFSET 16
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#define SW_RX_FORCE_TONE_MAP_TURBO_RATE_MASK 0x00030000
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#define SW_RX_FORCE_TONE_MAP_124_MODU_OFFSET 13
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#define SW_RX_FORCE_TONE_MAP_124_MODU_MASK 0x0000E000
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#define SW_RX_FORCE_TONE_MAP_124_EN_OFFSET 12
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#define SW_RX_FORCE_TONE_MAP_124_EN_MASK 0x00001000
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#define SW_RX_FORCE_TONE_MAP_125_MODU_OFFSET 9
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#define SW_RX_FORCE_TONE_MAP_125_MODU_MASK 0x00000E00
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#define SW_RX_FORCE_TONE_MAP_125_EN_OFFSET 8
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#define SW_RX_FORCE_TONE_MAP_125_EN_MASK 0x00000100
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#define SW_RX_FORCE_TONE_MAP_126_MODU_OFFSET 5
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#define SW_RX_FORCE_TONE_MAP_126_MODU_MASK 0x000000E0
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#define SW_RX_FORCE_TONE_MAP_126_EN_OFFSET 4
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#define SW_RX_FORCE_TONE_MAP_126_EN_MASK 0x00000010
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#define SW_RX_FORCE_TONE_MAP_127_MODU_OFFSET 1
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#define SW_RX_FORCE_TONE_MAP_127_MODU_MASK 0x0000000E
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#define SW_RX_FORCE_TONE_MAP_127_EN_OFFSET 0
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#define SW_RX_FORCE_TONE_MAP_127_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_PHY_DBG_BUS_LOCK_CTRL_ADDR 0x1318
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#define SW_PHY_DBG_LOCK_PATTERN_EN_OFFSET 19
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#define SW_PHY_DBG_LOCK_PATTERN_EN_MASK 0x00080000
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#define SW_FC_PARSE_DBG_BUS_SEL_OFFSET 16
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#define SW_FC_PARSE_DBG_BUS_SEL_MASK 0x00070000
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#define SW_PHY_DBG_BUS_LOCK_CHOS_OFFSET 8
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#define SW_PHY_DBG_BUS_LOCK_CHOS_MASK 0x0000FF00
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#define SW_PHY_DBG_BUS_LOCK_ENA_OFFSET 0
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#define SW_PHY_DBG_BUS_LOCK_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_PHY_DBG_BUS_LOCK_VALUE_ADDR 0x131c
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#define PHY_DBG_BUS_LOCK_OFFSET 0
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#define PHY_DBG_BUS_LOCK_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_PHY_NN_NID0_ADDR 0x1320
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#define SW_PHY_NN_NID0_OFFSET 0
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#define SW_PHY_NN_NID0_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_BB_PHY_NN_NID1_ADDR 0x1324
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#define SW_PHY_NN_NID1_OFFSET 0
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#define SW_PHY_NN_NID1_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_BB_PHY_NN_NID2_ADDR 0x1328
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#define SW_PHY_NN_NID2_OFFSET 0
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#define SW_PHY_NN_NID2_MASK 0x00FFFFFF
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//-----------------------------------
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#define CFG_BB_PHY_NN_NID3_ADDR 0x132c
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#define SW_PHY_NN_NID3_OFFSET 0
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#define SW_PHY_NN_NID3_MASK 0x00FFFFFF
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|
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//-----------------------------------
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#define CFG_BB_PHY_NN_NID4_ADDR 0x1330
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#define SW_PHY_NN_NID4_OFFSET 0
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#define SW_PHY_NN_NID4_MASK 0x00FFFFFF
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|
|
//-----------------------------------
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#define CFG_BB_PHY_NN_NID5_ADDR 0x1334
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#define SW_PHY_NN_NID5_OFFSET 0
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#define SW_PHY_NN_NID5_MASK 0x00FFFFFF
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|
|
|
//-----------------------------------
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#define CFG_BB_PHY_NN_NID6_ADDR 0x1338
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|
#define SW_PHY_NN_NID6_OFFSET 0
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#define SW_PHY_NN_NID6_MASK 0x00FFFFFF
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|
|
|
//-----------------------------------
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#define CFG_BB_PHY_NN_NID7_ADDR 0x133c
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#define SW_PHY_NN_NID7_OFFSET 0
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|
#define SW_PHY_NN_NID7_MASK 0x00FFFFFF
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|
|
|
//-----------------------------------
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#define CFG_BB_PHY_MPI_CTRL_ADDR 0x1340
|
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#define SW_MAC_BAND_RATE_SEL_OFFSET 3
|
|
#define SW_MAC_BAND_RATE_SEL_MASK 0x00000008
|
|
#define SW_PHY_TX_IS_PCS_BUSY_OFFSET 2
|
|
#define SW_PHY_TX_IS_PCS_BUSY_MASK 0x00000004
|
|
#define SW_TX_START_FILTER_EN_OFFSET 1
|
|
#define SW_TX_START_FILTER_EN_MASK 0x00000002
|
|
#define SW_TX_PRS_FILTER_EN_OFFSET 0
|
|
#define SW_TX_PRS_FILTER_EN_MASK 0x00000001
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|
|
|
//HW module read/write macro
|
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#define PHY_READ_REG(addr) SOC_READ_REG(PHY_BASEADDR + addr)
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#define PHY_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_BASEADDR + addr,value)
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