kunlun/inc/hw/reg/riscv2/15/phy_rxtd_reg.h

//-----------------------------------
#define CFG_BB_PKT_RATIO_ADDR 0x0000
#define SW_AC_STEP_1K_OFFSET 24
#define SW_AC_STEP_1K_MASK 0x07000000
#define SW_PKT_DET_RATIO_1K_OFFSET 16
#define SW_PKT_DET_RATIO_1K_MASK 0x00FF0000
#define SW_AC_STEP_384_OFFSET 8
#define SW_AC_STEP_384_MASK 0x00000700
#define SW_PKT_DET_RATIO_384_OFFSET 0
#define SW_PKT_DET_RATIO_384_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_PKT_RATIO_MINUS_ADDR 0x0004
#define SW_PKT_DET_RATIO_1K_MINUS_OFFSET 16
#define SW_PKT_DET_RATIO_1K_MINUS_MASK 0x00FF0000
#define SW_PKT_DET_RATIO_384_MINUS_OFFSET 0
#define SW_PKT_DET_RATIO_384_MINUS_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_THRESHOLD_ADDR 0x0008
#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_1K_OFFSET 16
#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_1K_MASK 0x0FFF0000
#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_384_OFFSET 0
#define SW_THRESHOLD_REVERT_BACK_FD_LAST_ACCUM_384_MASK 0x00000FFF

//-----------------------------------
#define CFG_BB_PKT_TIME_OUT_ADDR 0x000C
#define SW_PKT_DET_TIME_OUT_DISABLE_OFFSET 31
#define SW_PKT_DET_TIME_OUT_DISABLE_MASK 0x80000000
#define SW_PKT_DET_TIME_OUT_OFFSET 0
#define SW_PKT_DET_TIME_OUT_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_ADC_TIME_OUT_ADDR 0x0010
#define SW_PWR_FALL_TIMEOUT_DIS_OFFSET 31
#define SW_PWR_FALL_TIMEOUT_DIS_MASK 0x80000000
#define SW_ADC_PWR_FALL_TIME_OUT_OFFSET 0
#define SW_ADC_PWR_FALL_TIME_OUT_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_CORR_TIME_OUT_384_ADDR 0x0014
#define SW_SELF_CORR_LOWEST_TIME_OUT_384_OFFSET 0
#define SW_SELF_CORR_LOWEST_TIME_OUT_384_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_CORR_TIME_OUT_1K_ADDR 0x0018
#define SW_SELF_CORR_LOWEST_TIME_OUT_1K_OFFSET 0
#define SW_SELF_CORR_LOWEST_TIME_OUT_1K_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_OFFSET_FROM_CORR_ADDR 0x001C
#define SW_OFFSET_FROM_LOWEST_CORR_OFFSET 16
#define SW_OFFSET_FROM_LOWEST_CORR_MASK 0x000F0000
#define SW_PACKET_SYNC_MODE_OFFSET 9
#define SW_PACKET_SYNC_MODE_MASK 0x00000200
#define SW_TUNE_SKIP_FOR_FC_OFFSET 0
#define SW_TUNE_SKIP_FOR_FC_MASK 0x000001FF

//-----------------------------------
#define CFG_BB_STOP_FFT_ENGINE_ADDR 0x0020
#define SW_PKT_DET_1K_STEP_OFFSET 28
#define SW_PKT_DET_1K_STEP_MASK 0xF0000000
#define SW_THRESHOLD_STOP_FFT_3K_OFFSET 16
#define SW_THRESHOLD_STOP_FFT_3K_MASK 0x0FFF0000
#define SW_PKT_DET_384_STEP_OFFSET 12
#define SW_PKT_DET_384_STEP_MASK 0x0000F000
#define SW_THRESHOLD_STOP_FFT_384_OFFSET 0
#define SW_THRESHOLD_STOP_FFT_384_MASK 0x00000FFF

//-----------------------------------
#define CFG_BB_PKT_TIME_OUT_1_ADDR 0x0024
#define SW_AVE_THETA_TIME_OUT_OFFSET 0
#define SW_AVE_THETA_TIME_OUT_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_RX_TD_PKT_CNT_ADDR 0x0028
#define SW_RO_PACKET_NUM_OFFSET 0
#define SW_RO_PACKET_NUM_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_RX_TD_PKT_CNT_RST_ADDR 0x002C
#define SW_RESET_PACKET_NUM_OFFSET 0
#define SW_RESET_PACKET_NUM_MASK 0x00000001

//-----------------------------------
#define CFG_BB_SELF_CORR_CTRL_ADDR 0x0030
#define SW_ADJ_CORR_THETA_3K_OFFSET 20
#define SW_ADJ_CORR_THETA_3K_MASK 0xFFF00000
#define SW_ADJ_CORR_THETA_384_OFFSET 8
#define SW_ADJ_CORR_THETA_384_MASK 0x000FFF00
#define SW_SC_EN_3K_OFFSET 1
#define SW_SC_EN_3K_MASK 0x00000002
#define SW_SC_EN_384_OFFSET 0
#define SW_SC_EN_384_MASK 0x00000001

//-----------------------------------
#define CFG_BB_WAIT_AGC_ADDR 0x0034
#define SW_RD_FSM_TIMEOUT_OFFSET 0
#define SW_RD_FSM_TIMEOUT_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_MINUS_PRE_TIME_OUT_384_ADDR 0x0038
#define SW_FIND_MINUS_PREAM_TIME_OUT_384_OFFSET 0
#define SW_FIND_MINUS_PREAM_TIME_OUT_384_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_MINUS_PRE_TIME_OUT_3K_ADDR 0x003C
#define SW_FIND_MINUS_PREAM_TIME_OUT_3K_OFFSET 0
#define SW_FIND_MINUS_PREAM_TIME_OUT_3K_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_RX_TD_CTRL_DLY_ADDR 0x0040
#define SW_SKIP_FOR_FC101_OFFSET 12
#define SW_SKIP_FOR_FC101_MASK 0x01FFF000
#define SW_DLY_CNTR_BF_FFT_OFFSET 0
#define SW_DLY_CNTR_BF_FFT_MASK 0x00000FFF

//-----------------------------------
#define CFG_BB_MINU_SYMBO_CNTR_ADDR 0x0044
#define SW_MINU_SYMB_CNTR_GP_OFFSET 14
#define SW_MINU_SYMB_CNTR_GP_MASK 0x0FFFC000
#define SW_MINU_SYMB_CNTR_SG_OFFSET 0
#define SW_MINU_SYMB_CNTR_SG_MASK 0x00003FFF

//-----------------------------------
#define CFG_BB_PKT_TIME_OUT_384_ADDR 0x0048
#define SW_PKT_DET_TIME_OUT_384_OFFSET 0
#define SW_PKT_DET_TIME_OUT_384_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_MIX_FLAG_ADDR 0x004C
#define SW_MIX_FLAG_OFFSET 0
#define SW_MIX_FLAG_MASK 0x00000001

//-----------------------------------
#define CFG_BB_RX_TD_PKT_LS_CNT_ADDR 0x0050
#define SW_RO_PACKET_NUM_LS_OFFSET 0
#define SW_RO_PACKET_NUM_LS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_BST_PKT_TIME_OUT_384_ADDR 0x0054
#define SW_BST_PKT_DET_TIME_OUT_384_OFFSET 0
#define SW_BST_PKT_DET_TIME_OUT_384_MASK 0x001FFFFF

//-----------------------------------
#define CFG_BB_BIFS_TIME_ADDR 0x0058
#define SW_BIFS_TIME_OFFSET 0
#define SW_BIFS_TIME_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_SKIP_FOR_BST_ADDR 0x005C
#define SW_SKIP_FOR_BST_OFFSET 0
#define SW_SKIP_FOR_BST_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_SKIP_FOR_TD_ROBO_ADDR 0x0060
#define SW_EXT_SKIP_FOR_TD_TOBO_OFFSET 0
#define SW_EXT_SKIP_FOR_TD_TOBO_MASK 0x0001FFFF

//-----------------------------------
#define CFG_BB_TUNE_FOR_GI_ADDR 0x0064
#define SW_TUNE_FOR_PLD_GI2_EN_OFFSET 31
#define SW_TUNE_FOR_PLD_GI2_EN_MASK 0x80000000
#define SW_TUNE_FOR_PLD_GI2_OFFSET 24
#define SW_TUNE_FOR_PLD_GI2_MASK 0x7F000000
#define SW_TUNE_FOR_PLD_GI1_EN_OFFSET 23
#define SW_TUNE_FOR_PLD_GI1_EN_MASK 0x00800000
#define SW_TUNE_FOR_PLD_GI1_OFFSET 16
#define SW_TUNE_FOR_PLD_GI1_MASK 0x007F0000
#define SW_TUNE_FOR_PLD_GI0_EN_OFFSET 15
#define SW_TUNE_FOR_PLD_GI0_EN_MASK 0x00008000
#define SW_TUNE_FOR_PLD_GI0_OFFSET 8
#define SW_TUNE_FOR_PLD_GI0_MASK 0x00007F00
#define SW_TUNE_FOR_FC_GI1_EN_OFFSET 7
#define SW_TUNE_FOR_FC_GI1_EN_MASK 0x00000080
#define SW_TUNE_FOR_FC_GI1_OFFSET 0
#define SW_TUNE_FOR_FC_GI1_MASK 0x0000007F

//-----------------------------------
#define CFG_BB_RX_SRST_ADDR 0x0068
#define SW_RX_SRST_OFFSET 0
#define SW_RX_SRST_MASK 0x00000001

//-----------------------------------
#define CFG_BB_1SYNCM_ADDR 0x006C
#define SW_SKIP_FOR_1SYNCM_OFFSET 4
#define SW_SKIP_FOR_1SYNCM_MASK 0x000FFFF0
#define SW_1SYNCM_EN_OFFSET 0
#define SW_1SYNCM_EN_MASK 0x00000001

//-----------------------------------
#define CFG_BB_RX_GI_WIN_ADDR 0x0070
#define SW_RX_GI_WIN_PROTECT_OFFSET 0
#define SW_RX_GI_WIN_PROTECT_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_RXTD_SPARE0_ADDR 0x0100
#define SW_RXTD_SPARE0_OFFSET 0
#define SW_RXTD_SPARE0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_RXTD_SPARE1_ADDR 0x0104
#define SW_RXTD_SPARE1_OFFSET 0
#define SW_RXTD_SPARE1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_RXTD_SPARE2_ADDR 0x0108
#define SW_RXTD_SPARE2_OFFSET 0
#define SW_RXTD_SPARE2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_RXTD_SPARE3_ADDR 0x010C
#define SW_RXTD_SPARE3_OFFSET 0
#define SW_RXTD_SPARE3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_BB_AGC_WK_TO_ST_TH_ADDR 0x0400
#define SW_POWER_CCA_EN_OFFSET 31
#define SW_POWER_CCA_EN_MASK 0x80000000
#define SW_WK_TO_ST_TH_OFFSET 0
#define SW_WK_TO_ST_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_ST_RCV_LO_TH_ADDR 0x0404
#define SW_ST_RCV_LO_TH_OFFSET 0
#define SW_ST_RCV_LO_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_ST_RCV_HI_TH_ADDR 0x0408
#define SW_ST_RCV_HI_TH_OFFSET 0
#define SW_ST_RCV_HI_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_ST_RCV_TGT_ADDR 0x040C
#define SW_ST_RCV_TGT_OFFSET 0
#define SW_ST_RCV_TGT_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_WK_RCV_LO_TH_ADDR 0x0410
#define SW_WK_RCV_LO_TH_OFFSET 0
#define SW_WK_RCV_LO_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_WK_RCV_HI_TH_ADDR 0x0414
#define SW_WK_RCV_HI_TH_OFFSET 0
#define SW_WK_RCV_HI_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_WK_RCV_TGT_ADDR 0x0418
#define SW_WK_RCV_TGT_OFFSET 0
#define SW_WK_RCV_TGT_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_WK_DET_LO_TH_ADDR 0x041C
#define SW_WK_DET_LO_TH_OFFSET 0
#define SW_WK_DET_LO_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_WK_DET_HI_TH_ADDR 0x0420
#define SW_WK_DET_HI_TH_OFFSET 0
#define SW_WK_DET_HI_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_WK_DET_TGT_ADDR 0x0424
#define SW_WK_DET_TGT_OFFSET 0
#define SW_WK_DET_TGT_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_RAMUP_TH_ADDR 0x0428
#define SW_RAMPUP_RESTART_DIS_OFFSET 31
#define SW_RAMPUP_RESTART_DIS_MASK 0x80000000
#define SW_R1B2_RAMPUP_RESTART_DIS_OFFSET 21
#define SW_R1B2_RAMPUP_RESTART_DIS_MASK 0x00200000
#define SW_R1B1_RAMPUP_RESTART_DIS_OFFSET 20
#define SW_R1B1_RAMPUP_RESTART_DIS_MASK 0x00100000
#define SW_R1B0_RAMPUP_RESTART_DIS_OFFSET 19
#define SW_R1B0_RAMPUP_RESTART_DIS_MASK 0x00080000
#define SW_R0B2_RAMPUP_RESTART_DIS_OFFSET 18
#define SW_R0B2_RAMPUP_RESTART_DIS_MASK 0x00040000
#define SW_R0B1_RAMPUP_RESTART_DIS_OFFSET 17
#define SW_R0B1_RAMPUP_RESTART_DIS_MASK 0x00020000
#define SW_R0B0_RAMPUP_RESTART_DIS_OFFSET 16
#define SW_R0B0_RAMPUP_RESTART_DIS_MASK 0x00010000
#define SW_RAMPUP_DET_TH_OFFSET 8
#define SW_RAMPUP_DET_TH_MASK 0x0000FF00
#define SW_RAMPUP_RCV_TH_OFFSET 0
#define SW_RAMPUP_RCV_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_DROP_TH_ADDR 0x042C
#define SW_DROP_RESTART_DIS_OFFSET 31
#define SW_DROP_RESTART_DIS_MASK 0x80000000
#define SW_R1B2_DROP_RESTART_DIS_OFFSET 21
#define SW_R1B2_DROP_RESTART_DIS_MASK 0x00200000
#define SW_R1B1_DROP_RESTART_DIS_OFFSET 20
#define SW_R1B1_DROP_RESTART_DIS_MASK 0x00100000
#define SW_R1B0_DROP_RESTART_DIS_OFFSET 19
#define SW_R1B0_DROP_RESTART_DIS_MASK 0x00080000
#define SW_R0B2_DROP_RESTART_DIS_OFFSET 18
#define SW_R0B2_DROP_RESTART_DIS_MASK 0x00040000
#define SW_R0B1_DROP_RESTART_DIS_OFFSET 17
#define SW_R0B1_DROP_RESTART_DIS_MASK 0x00020000
#define SW_R0B0_DROP_RESTART_DIS_OFFSET 16
#define SW_R0B0_DROP_RESTART_DIS_MASK 0x00010000
#define SW_DROP_DET_TH_OFFSET 8
#define SW_DROP_DET_TH_MASK 0x0000FF00
#define SW_DROP_RCV_TH_OFFSET 0
#define SW_DROP_RCV_TH_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_GAIN_DLY_ADDR 0x0430
#define SW_GAIN_DLY_OFFSET 0
#define SW_GAIN_DLY_MASK 0x0000FFFF

//-----------------------------------
#define CFG_BB_AGC_GAIN_LOOP_ADDR 0x0434
#define SW_GAIN_LOOP_OFFSET 0
#define SW_GAIN_LOOP_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_GAIN_LEVEL_ADDR 0x0438
#define SW_FIX_GAIN_EN_OFFSET 31
#define SW_FIX_GAIN_EN_MASK 0x80000000
#define SW_ADJ_REQ_DIS_OFFSET 30
#define SW_ADJ_REQ_DIS_MASK 0x40000000
#define SW_SAT_DIS_OFFSET 29
#define SW_SAT_DIS_MASK 0x20000000
#define SW_FIRST_GAIN_SEL_OFFSET 28
#define SW_FIRST_GAIN_SEL_MASK 0x10000000
#define SW_COMPARE_AVE_DIS_OFFSET 27
#define SW_COMPARE_AVE_DIS_MASK 0x08000000
#define SW_MAX_GAIN_OFFSET 16
#define SW_MAX_GAIN_MASK 0x00FF0000
#define SW_MIN_GAIN_OFFSET 8
#define SW_MIN_GAIN_MASK 0x0000FF00
#define SW_INI_GAIN_OFFSET 0
#define SW_INI_GAIN_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_SAT_TH_ADDR 0x043C
#define SW_SAT_ATTEN_DB_OFFSET 24
#define SW_SAT_ATTEN_DB_MASK 0xFF000000
#define SW_SAT_RESTART_DIS_OFFSET 10
#define SW_SAT_RESTART_DIS_MASK 0x00000400
#define SW_PWR_SAT_TH_OFFSET 0
#define SW_PWR_SAT_TH_MASK 0x000003FF

//-----------------------------------
#define CFG_BB_AGC_ACC_STEP_ADDR 0x0440
#define SW_AGC_ACC_SET_VLD_OFFSET 31
#define SW_AGC_ACC_SET_VLD_MASK 0x80000000
#define SW_AGC_ACC_STEP_HS_OFFSET 6
#define SW_AGC_ACC_STEP_HS_MASK 0x000001C0
#define SW_AGC_ACC_STEP_LS_OFFSET 3
#define SW_AGC_ACC_STEP_LS_MASK 0x00000038
#define SW_AGC_ACC_STEP_OFFSET 0
#define SW_AGC_ACC_STEP_MASK 0x00000007

//-----------------------------------
#define CFG_BB_AGC_NOISE_CAL_ADDR 0x0444
#define SW_CAL_NOISE_DET_EN_OFFSET 22
#define SW_CAL_NOISE_DET_EN_MASK 0x00400000
#define SW_CAL_NOISE_DONE_OFFSET 21
#define SW_CAL_NOISE_DONE_MASK 0x00200000
#define SW_CAL_NOISE_START_OFFSET 20
#define SW_CAL_NOISE_START_MASK 0x00100000
#define SW_CAL_NOISE_DLY_EXP_OFFSET 16
#define SW_CAL_NOISE_DLY_EXP_MASK 0x000F0000
#define SW_CAL_NOISE_PWR_OFFSET 8
#define SW_CAL_NOISE_PWR_MASK 0x0000FF00
#define SW_FREE_NOISE_PWR_OFFSET 0
#define SW_FREE_NOISE_PWR_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_ACC_PWR_ADDR 0x448
#define SW_SEG_PWR_MASK_SEL_OFFSET 20
#define SW_SEG_PWR_MASK_SEL_MASK 0x00100000
#define SW_SEG_PWR_MASK_THR_OFFSET 16
#define SW_SEG_PWR_MASK_THR_MASK 0x000F0000
#define SW_SEG_PWR_MASK_EN_OFFSET 12
#define SW_SEG_PWR_MASK_EN_MASK 0x00001000
#define SW_NORMAL_COEFF_OFFSET 8
#define SW_NORMAL_COEFF_MASK 0x00000300
#define SW_SEG_PWR_EN_OFFSET 0
#define SW_SEG_PWR_EN_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_AGC_SAT_JUDGE_ADDR 0x044C
#define SW_SAT_SEG_EN_OFFSET 20
#define SW_SAT_SEG_EN_MASK 0x00100000
#define SW_PWR_SAT_JUG_CNT_OFFSET 4
#define SW_PWR_SAT_JUG_CNT_MASK 0x0003FFF0
#define SW_SAT_SEG_NUM_OFFSET 0
#define SW_SAT_SEG_NUM_MASK 0x0000000F

//-----------------------------------
#define CFG_BB_PACKET_INF_0_ADDR 0x500
#define FREE_RSSI_OFFSET 16
#define FREE_RSSI_MASK 0x00FF0000
#define GAIN_TABLE_ENTRY_OFFSET 8
#define GAIN_TABLE_ENTRY_MASK 0x0000FF00
#define PACKET_RSSI_OFFSET 0
#define PACKET_RSSI_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_PACKET_INF_1_ADDR 0x504
#define GAIN_TABLE_ENTRY_NF_OFFSET 8
#define GAIN_TABLE_ENTRY_NF_MASK 0x0000FF00
#define RSSI_NF_OFFSET 0
#define RSSI_NF_MASK 0x000000FF

//-----------------------------------
#define CFG_BB_PACKET_INF_2_ADDR 0x508
#define DC_EST_FREE_OFFSET 12
#define DC_EST_FREE_MASK 0x003FF000
#define PACKET_DC_OFFSET 0
#define PACKET_DC_MASK 0x000003FF

//-----------------------------------
#define CFG_BB_AUTO_NOISE_ADDR 0x50C
#define SW_AUTO_NOISE_INTERVAL_OFFSET 8
#define SW_AUTO_NOISE_INTERVAL_MASK 0x00001F00
#define SW_AUTO_NOISE_PWR_OFFSET 0
#define SW_AUTO_NOISE_PWR_MASK 0x000000FF

//-----------------------------------
#define CFG_AGC_DBG_BUS_ADDR 0x600
#define AGC_DBG_BUS_OFFSET 0
#define AGC_DBG_BUS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_TD_DBG_BUS0_ADDR 0x604
#define RX_TD_DBG_BUS0_OFFSET 0
#define RX_TD_DBG_BUS0_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_TD_DBG_BUS1_ADDR 0x608
#define RX_TD_DBG_BUS1_OFFSET 0
#define RX_TD_DBG_BUS1_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_TD_DBG_BUS2_ADDR 0x60C
#define RX_TD_DBG_BUS2_OFFSET 0
#define RX_TD_DBG_BUS2_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_TD_DBG_BUS3_ADDR 0x610
#define RX_TD_DBG_BUS3_OFFSET 0
#define RX_TD_DBG_BUS3_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_TD_FSM_DBG_BUS_ADDR 0x614
#define RX_TD_FSM_DBG_BUS_OFFSET 0
#define RX_TD_FSM_DBG_BUS_MASK 0xFFFFFFFF

//-----------------------------------
#define CFG_RX_FD_FSM_DBG_BUS_ADDR 0x618
#define RX_FD_FSM_DBG_BUS_OFFSET 0
#define RX_FD_FSM_DBG_BUS_MASK 0xFFFFFFFF

//HW module read/write macro
#define PHY_RXTD_READ_REG(addr) SOC_READ_REG(PHY_RXTD_BASEADDR + addr)
#define PHY_RXTD_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_RXTD_BASEADDR + addr,value)