433 lines
13 KiB
C
Executable File
433 lines
13 KiB
C
Executable File
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//-----------------------------------
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#define CFG_PTCON_ADDR 0x00
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#define PTEN_OFFSET 15
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#define PTEN_MASK 0x00008000
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#define PTOPS_OFFSET 4
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#define PTOPS_MASK 0x000000F0
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#define PTMOD_OFFSET 0
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#define PTMOD_MASK 0x00000003
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//-----------------------------------
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#define CFG_PTMR_ADDR 0x04
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#define PTDIR_OFFSET 15
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#define PTDIR_MASK 0x00008000
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#define PTMR_OFFSET 0
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#define PTMR_MASK 0x00007FFF
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//-----------------------------------
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#define CFG_PTPER_ADDR 0x08
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#define PTPER_OFFSET 0
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#define PTPER_MASK 0x00007FFF
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//-----------------------------------
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#define CFG_SEVTCMP_ADDR 0x0C
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#define SEVTDIR_OFFSET 15
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#define SEVTDIR_MASK 0x00008000
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#define SEVTCMP_OFFSET 0
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#define SEVTCMP_MASK 0x00007FFF
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//-----------------------------------
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#define CFG_PWMCON1_ADDR 0x10
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#define PMOD4_OFFSET 11
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#define PMOD4_MASK 0x00000800
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#define PMOD3_OFFSET 10
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#define PMOD3_MASK 0x00000400
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#define PMOD2_OFFSET 9
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#define PMOD2_MASK 0x00000200
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#define PMOD1_OFFSET 8
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#define PMOD1_MASK 0x00000100
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//-----------------------------------
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#define CFG_PWM_ICAP_ADDR 0x14
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#define SEVOPS_OFFSET 8
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#define SEVOPS_MASK 0x00000F00
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#define IUE_OFFSET 2
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#define IUE_MASK 0x00000004
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#define OSYNC_OFFSET 1
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#define OSYNC_MASK 0x00000002
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#define UDIS_OFFSET 0
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#define UDIS_MASK 0x00000001
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//-----------------------------------
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#define CFG_DTCON1_ADDR 0x18
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#define DTBPS_OFFSET 14
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#define DTBPS_MASK 0x0000C000
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#define DTB_OFFSET 8
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#define DTB_MASK 0x00003F00
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#define DTAPS_OFFSET 6
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#define DTAPS_MASK 0x000000C0
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#define DTA_OFFSET 0
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#define DTA_MASK 0x0000003F
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//-----------------------------------
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#define CFG_DTCON2_ADDR 0x1C
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#define DTS4A_OFFSET 7
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#define DTS4A_MASK 0x00000080
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#define DTS4I_OFFSET 6
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#define DTS4I_MASK 0x00000040
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#define DTS3A_OFFSET 5
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#define DTS3A_MASK 0x00000020
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#define DTS3I_OFFSET 4
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#define DTS3I_MASK 0x00000010
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#define DTS2A_OFFSET 3
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#define DTS2A_MASK 0x00000008
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#define DTS2I_OFFSET 2
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#define DTS2I_MASK 0x00000004
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#define DTS1A_OFFSET 1
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#define DTS1A_MASK 0x00000002
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#define DTS1I_OFFSET 0
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#define DTS1I_MASK 0x00000001
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//-----------------------------------
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#define CFG_FLTACON_ADDR 0x20
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#define FAOV4H_OFFSET 15
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#define FAOV4H_MASK 0x00008000
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#define FAOV4L_OFFSET 14
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#define FAOV4L_MASK 0x00004000
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#define FAOV3H_OFFSET 13
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#define FAOV3H_MASK 0x00002000
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#define FAOV3L_OFFSET 12
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#define FAOV3L_MASK 0x00001000
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#define FAOV2H_OFFSET 11
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#define FAOV2H_MASK 0x00000800
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#define FAOV2L_OFFSET 10
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#define FAOV2L_MASK 0x00000400
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#define FAOV1H_OFFSET 9
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#define FAOV1H_MASK 0x00000200
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#define FAOV1L_OFFSET 8
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#define FAOV1L_MASK 0x00000100
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#define FLTAM_OFFSET 7
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#define FLTAM_MASK 0x00000080
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#define FAEN4_OFFSET 3
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#define FAEN4_MASK 0x00000008
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#define FAEN3_OFFSET 2
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#define FAEN3_MASK 0x00000004
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#define FAEN2_OFFSET 1
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#define FAEN2_MASK 0x00000002
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#define FAEN1_OFFSET 0
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#define FAEN1_MASK 0x00000001
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//-----------------------------------
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#define CFG_FLTBCON_ADDR 0x24
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#define FBOV4H_OFFSET 15
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#define FBOV4H_MASK 0x00008000
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#define FBOV4L_OFFSET 14
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#define FBOV4L_MASK 0x00004000
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#define FBOV3H_OFFSET 13
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#define FBOV3H_MASK 0x00002000
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#define FBOV3L_OFFSET 12
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#define FBOV3L_MASK 0x00001000
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#define FBOV2H_OFFSET 11
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#define FBOV2H_MASK 0x00000800
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#define FBOV2L_OFFSET 10
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#define FBOV2L_MASK 0x00000400
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#define FBOV1H_OFFSET 9
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#define FBOV1H_MASK 0x00000200
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#define FBOV1L_OFFSET 8
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#define FBOV1L_MASK 0x00000100
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#define FLTBM_OFFSET 7
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#define FLTBM_MASK 0x00000080
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#define FBEN4_OFFSET 3
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#define FBEN4_MASK 0x00000008
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#define FBEN3_OFFSET 2
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#define FBEN3_MASK 0x00000004
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#define FBEN2_OFFSET 1
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#define FBEN2_MASK 0x00000002
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#define FBEN1_OFFSET 0
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#define FBEN1_MASK 0x00000001
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//-----------------------------------
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#define CFG_OVDCON_ADDR 0x28
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#define POVD4H_OFFSET 15
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#define POVD4H_MASK 0x00008000
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#define POVD4L_OFFSET 14
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#define POVD4L_MASK 0x00004000
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#define POVD3H_OFFSET 13
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#define POVD3H_MASK 0x00002000
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#define POVD3L_OFFSET 12
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#define POVD3L_MASK 0x00001000
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#define POVD2H_OFFSET 11
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#define POVD2H_MASK 0x00000800
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#define POVD2L_OFFSET 10
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#define POVD2L_MASK 0x00000400
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#define POVD1H_OFFSET 9
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#define POVD1H_MASK 0x00000200
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#define POVD1L_OFFSET 8
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#define POVD1L_MASK 0x00000100
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#define POUT4H_OFFSET 7
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#define POUT4H_MASK 0x00000080
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#define POUT4L_OFFSET 6
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#define POUT4L_MASK 0x00000040
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#define POUT3H_OFFSET 5
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#define POUT3H_MASK 0x00000020
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#define POUT3L_OFFSET 4
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#define POUT3L_MASK 0x00000010
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#define POUT2H_OFFSET 3
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#define POUT2H_MASK 0x00000008
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#define POUT2L_OFFSET 2
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#define POUT2L_MASK 0x00000004
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#define POUT1H_OFFSET 1
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#define POUT1H_MASK 0x00000002
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#define POUT1L_OFFSET 0
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#define POUT1L_MASK 0x00000001
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//-----------------------------------
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#define CFG_PDC1_ADDR 0x2C
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#define PDC1_OFFSET 0
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#define PDC1_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_PDC2_ADDR 0x30
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#define PDC2_OFFSET 0
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#define PDC2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_PDC3_ADDR 0x34
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#define PDC3_OFFSET 0
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#define PDC3_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_PDC4_ADDR 0x38
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#define PDC4_OFFSET 0
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#define PDC4_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_POLAR_ADDR 0x3C
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#define POLAR_OFFSET 0
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#define POLAR_MASK 0x000000FF
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//-----------------------------------
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#define CFG_PTDIV_ADDR 0x40
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#define PTDIV_OFFSET 0
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#define PTDIV_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_PWM_INT_ENA_ADDR 0x44
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#define PDC_MATCH_DOWN4_INT_ENA_OFFSET 16
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#define PDC_MATCH_DOWN4_INT_ENA_MASK 0x00010000
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#define PDC_MATCH_UP4_INT_ENA_OFFSET 15
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#define PDC_MATCH_UP4_INT_ENA_MASK 0x00008000
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#define PDC_MATCH_DOWN3_INT_ENA_OFFSET 14
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#define PDC_MATCH_DOWN3_INT_ENA_MASK 0x00004000
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#define PDC_MATCH_UP3_INT_ENA_OFFSET 13
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#define PDC_MATCH_UP3_INT_ENA_MASK 0x00002000
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#define PDC_MATCH_DOWN2_INT_ENA_OFFSET 12
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#define PDC_MATCH_DOWN2_INT_ENA_MASK 0x00001000
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#define PDC_MATCH_UP2_INT_ENA_OFFSET 11
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#define PDC_MATCH_UP2_INT_ENA_MASK 0x00000800
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#define PDC_MATCH_DOWN1_INT_ENA_OFFSET 10
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#define PDC_MATCH_DOWN1_INT_ENA_MASK 0x00000400
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#define PDC_MATCH_UP1_INT_ENA_OFFSET 9
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#define PDC_MATCH_UP1_INT_ENA_MASK 0x00000200
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#define ENC_UNF_ENA_OFFSET 8
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#define ENC_UNF_ENA_MASK 0x00000100
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#define ENC_OVF_ENA_OFFSET 7
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#define ENC_OVF_ENA_MASK 0x00000080
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#define CAP3_INT_ENA_OFFSET 6
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#define CAP3_INT_ENA_MASK 0x00000040
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#define CAP2_INT_ENA_OFFSET 5
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#define CAP2_INT_ENA_MASK 0x00000020
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#define CAP1_INT_ENA_OFFSET 4
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#define CAP1_INT_ENA_MASK 0x00000010
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#define FLTB_INT_ENA_OFFSET 3
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#define FLTB_INT_ENA_MASK 0x00000008
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#define FLTA_INT_ENA_OFFSET 2
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#define FLTA_INT_ENA_MASK 0x00000004
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#define PWM_EVENT_INT_ENA_OFFSET 1
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#define PWM_EVENT_INT_ENA_MASK 0x00000002
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#define PTIMER_INT_ENA_OFFSET 0
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#define PTIMER_INT_ENA_MASK 0x00000001
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//-----------------------------------
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#define CFG_PWM_INT_RAW_ADDR 0x48
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#define PDC_MATCH_DOWN4_INT_RAW_OFFSET 16
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#define PDC_MATCH_DOWN4_INT_RAW_MASK 0x00010000
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#define PDC_MATCH_UP4_INT_RAW_OFFSET 15
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#define PDC_MATCH_UP4_INT_RAW_MASK 0x00008000
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#define PDC_MATCH_DOWN3_INT_RAW_OFFSET 14
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#define PDC_MATCH_DOWN3_INT_RAW_MASK 0x00004000
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#define PDC_MATCH_UP3_INT_RAW_OFFSET 13
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#define PDC_MATCH_UP3_INT_RAW_MASK 0x00002000
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#define PDC_MATCH_DOWN2_INT_RAW_OFFSET 12
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#define PDC_MATCH_DOWN2_INT_RAW_MASK 0x00001000
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#define PDC_MATCH_UP2_INT_RAW_OFFSET 11
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#define PDC_MATCH_UP2_INT_RAW_MASK 0x00000800
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#define PDC_MATCH_DOWN1_INT_RAW_OFFSET 10
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#define PDC_MATCH_DOWN1_INT_RAW_MASK 0x00000400
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#define PDC_MATCH_UP1_INT_RAW_OFFSET 9
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#define PDC_MATCH_UP1_INT_RAW_MASK 0x00000200
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#define ENC_UNF_INT_RAW_OFFSET 8
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#define ENC_UNF_INT_RAW_MASK 0x00000100
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#define ENC_OVF_INT_RAW_OFFSET 7
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#define ENC_OVF_INT_RAW_MASK 0x00000080
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#define CAP3_INT_RAW_OFFSET 6
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#define CAP3_INT_RAW_MASK 0x00000040
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#define CAP2_INT_RAW_OFFSET 5
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#define CAP2_INT_RAW_MASK 0x00000020
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#define CAP1_INT_RAW_OFFSET 4
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#define CAP1_INT_RAW_MASK 0x00000010
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#define FLTB_INT_RAW_OFFSET 3
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#define FLTB_INT_RAW_MASK 0x00000008
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#define FLTA_INT_RAW_OFFSET 2
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#define FLTA_INT_RAW_MASK 0x00000004
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#define PWM_EVENTINT_RAW_OFFSET 1
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#define PWM_EVENTINT_RAW_MASK 0x00000002
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#define PTIMER_INT_RAW_OFFSET 0
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#define PTIMER_INT_RAW_MASK 0x00000001
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//-----------------------------------
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#define CFG_PWM_INT_ST_ADDR 0x4c
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#define PDC_MATCH_DOWN4_INT_ST_OFFSET 16
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#define PDC_MATCH_DOWN4_INT_ST_MASK 0x00010000
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#define PDC_MATCH_UP4_INT_ST_OFFSET 15
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#define PDC_MATCH_UP4_INT_ST_MASK 0x00008000
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#define PDC_MATCH_DOWN3_INT_ST_OFFSET 14
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#define PDC_MATCH_DOWN3_INT_ST_MASK 0x00004000
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#define PDC_MATCH_UP3_INT_ST_OFFSET 13
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#define PDC_MATCH_UP3_INT_ST_MASK 0x00002000
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#define PDC_MATCH_DOWN2_INT_ST_OFFSET 12
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#define PDC_MATCH_DOWN2_INT_ST_MASK 0x00001000
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#define PDC_MATCH_UP2_INT_ST_OFFSET 11
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#define PDC_MATCH_UP2_INT_ST_MASK 0x00000800
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#define PDC_MATCH_DOWN1_INT_ST_OFFSET 10
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#define PDC_MATCH_DOWN1_INT_ST_MASK 0x00000400
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#define PDC_MATCH_UP1_INT_ST_OFFSET 9
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#define PDC_MATCH_UP1_INT_ST_MASK 0x00000200
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#define ENC_UNF_INT_ST_OFFSET 8
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#define ENC_UNF_INT_ST_MASK 0x00000100
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#define ENC_OVF_INT_ST_OFFSET 7
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#define ENC_OVF_INT_ST_MASK 0x00000080
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#define CAP3_INT_ST_OFFSET 6
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#define CAP3_INT_ST_MASK 0x00000040
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#define CAP2_INT_ST_OFFSET 5
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#define CAP2_INT_ST_MASK 0x00000020
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#define CAP1_INT_ST_OFFSET 4
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#define CAP1_INT_ST_MASK 0x00000010
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#define FLTB_INT_ST_OFFSET 3
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#define FLTB_INT_ST_MASK 0x00000008
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#define FLTA_INT_ST_OFFSET 2
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#define FLTA_INT_ST_MASK 0x00000004
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#define PWM_EVENTINT_ST_OFFSET 1
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#define PWM_EVENTINT_ST_MASK 0x00000002
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#define PTIMER_INT_ST_OFFSET 0
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#define PTIMER_INT_ST_MASK 0x00000001
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//-----------------------------------
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#define CFG_PWM_INT_CLR_ADDR 0x50
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#define PDC_MATCH_DOWN4_INT_CLR_OFFSET 16
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#define PDC_MATCH_DOWN4_INT_CLR_MASK 0x00010000
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#define PDC_MATCH_UP4_INT_CLR_OFFSET 15
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#define PDC_MATCH_UP4_INT_CLR_MASK 0x00008000
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#define PDC_MATCH_DOWN3_INT_CLR_OFFSET 14
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#define PDC_MATCH_DOWN3_INT_CLR_MASK 0x00004000
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#define PDC_MATCH_UP3_INT_CLR_OFFSET 13
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#define PDC_MATCH_UP3_INT_CLR_MASK 0x00002000
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#define PDC_MATCH_DOWN2_INT_CLR_OFFSET 12
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#define PDC_MATCH_DOWN2_INT_CLR_MASK 0x00001000
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#define PDC_MATCH_UP2_INT_CLR_OFFSET 11
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#define PDC_MATCH_UP2_INT_CLR_MASK 0x00000800
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#define PDC_MATCH_DOWN1_INT_CLR_OFFSET 10
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#define PDC_MATCH_DOWN1_INT_CLR_MASK 0x00000400
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#define PDC_MATCH_UP1_INT_CLR_OFFSET 9
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#define PDC_MATCH_UP1_INT_CLR_MASK 0x00000200
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#define ENC_UNF_INT_CLR_OFFSET 8
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#define ENC_UNF_INT_CLR_MASK 0x00000100
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#define ENC_OVF_INT_SCLR_OFFSET 7
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#define ENC_OVF_INT_SCLR_MASK 0x00000080
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#define CAP3_INT_CLR_OFFSET 6
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#define CAP3_INT_CLR_MASK 0x00000040
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#define CAP2_INT_CLR_OFFSET 5
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#define CAP2_INT_CLR_MASK 0x00000020
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#define CAP1_INT_CLR_OFFSET 4
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#define CAP1_INT_CLR_MASK 0x00000010
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#define FLTB_INT_CLR_OFFSET 3
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#define FLTB_INT_CLR_MASK 0x00000008
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#define FLTA_INT_CLR_OFFSET 2
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#define FLTA_INT_CLR_MASK 0x00000004
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#define PWM_EVENTINT_CLR_OFFSET 1
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#define PWM_EVENTINT_CLR_MASK 0x00000002
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#define PTIMER_INT_CLR_OFFSET 0
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#define PTIMER_INT_CLR_MASK 0x00000001
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//-----------------------------------
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#define CFG_CAP_MOD_ADDR 0x54
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#define CAP_ENA_OFFSET 15
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#define CAP_ENA_MASK 0x00008000
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#define CAP_POLAR_OFFSET 8
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#define CAP_POLAR_MASK 0x00000700
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#define CAP3_MOD_OFFSET 4
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#define CAP3_MOD_MASK 0x00000030
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#define CAP2_MOD_OFFSET 2
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#define CAP2_MOD_MASK 0x0000000C
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#define CAP1_MOD_OFFSET 0
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#define CAP1_MOD_MASK 0x00000003
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//-----------------------------------
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#define CFG_CAP_ST_ADDR 0x58
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#define CAP3_ST_OFFSET 4
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#define CAP3_ST_MASK 0x00000030
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#define CAP2_ST_OFFSET 2
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#define CAP2_ST_MASK 0x0000000C
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#define CAP1_ST_OFFSET 0
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#define CAP1_ST_MASK 0x00000003
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//-----------------------------------
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#define CFG_CAP1_TIME_ADDR 0x5C
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#define CAP1_TIME_OFFSET 0
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#define CAP1_TIME_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CAP2_TIME_ADDR 0x60
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#define CAP2_TIME_OFFSET 0
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#define CAP2_TIME_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_CAP3_TIME_ADDR 0x64
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#define CAP3_TIME_OFFSET 0
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#define CAP3_TIME_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_PWM_ST_ADDR 0x68
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#define CAP3_IN_OFFSET 6
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#define CAP3_IN_MASK 0x00000040
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#define CAP2_IN_OFFSET 5
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#define CAP2_IN_MASK 0x00000020
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#define CAP1_IN_OFFSET 4
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#define CAP1_IN_MASK 0x00000010
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#define FLTB_OFFSET 3
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#define FLTB_MASK 0x00000008
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#define FLTA_OFFSET 2
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#define FLTA_MASK 0x00000004
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#define PWM_EVENT_OFFSET 1
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#define PWM_EVENT_MASK 0x00000002
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#define PTINT_OFFSET 0
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#define PTINT_MASK 0x00000001
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//-----------------------------------
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#define CFG_PWM_ENC_MOD_ADDR 0x6C
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#define ENC_ENA_OFFSET 15
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#define ENC_ENA_MASK 0x00008000
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#define ROT_DIR_OFFSET 2
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#define ROT_DIR_MASK 0x00000004
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#define ENC_POLAR_OFFSET 0
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#define ENC_POLAR_MASK 0x00000003
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//-----------------------------------
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#define CFG_PWM_ENC_CNT_ADDR 0x70
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#define PWM_ENC_CNT_OFFSET 0
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#define PWM_ENC_CNT_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_PWM_MISC_CTL_ADDR 0x80
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#define PWM_OE_OFFSET 8
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#define PWM_OE_MASK 0x0000FF00
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#define EVT1_SEL_OFFSET 4
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#define EVT1_SEL_MASK 0x000000F0
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#define EVT0_SEL_OFFSET 0
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#define EVT0_SEL_MASK 0x0000000F
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//HW module read/write macro
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#define PWM_READ_REG(addr) SOC_READ_REG(PWM_BASEADDR + addr)
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#define PWM_WRITE_REG(addr,value) SOC_WRITE_REG(PWM_BASEADDR + addr,value)
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