171 lines
5.0 KiB
C
171 lines
5.0 KiB
C
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//-----------------------------------
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#define CFG_SPINLOCK_EN_ADDR 0x0
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#define SPINLOCK_MAGIC_NUM_OFFSET 0
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#define SPINLOCK_MAGIC_NUM_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK0_ADDR 0x100
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#define SPINLOCK_LOCK0_OFFSET 0
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#define SPINLOCK_LOCK0_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK1_ADDR 0x104
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#define SPINLOCK_LOCK1_OFFSET 0
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#define SPINLOCK_LOCK1_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK2_ADDR 0x108
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#define SPINLOCK_LOCK2_OFFSET 0
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#define SPINLOCK_LOCK2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK3_ADDR 0x10C
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#define SPINLOCK_LOCK3_OFFSET 0
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#define SPINLOCK_LOCK3_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK4_ADDR 0x110
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#define SPINLOCK_LOCK4_OFFSET 0
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#define SPINLOCK_LOCK4_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK5_ADDR 0x114
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#define SPINLOCK_LOCK5_OFFSET 0
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#define SPINLOCK_LOCK5_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK6_ADDR 0x118
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#define SPINLOCK_LOCK6_OFFSET 0
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#define SPINLOCK_LOCK6_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK7_ADDR 0x11C
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#define SPINLOCK_LOCK7_OFFSET 0
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#define SPINLOCK_LOCK7_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK8_ADDR 0x120
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#define SPINLOCK_LOCK8_OFFSET 0
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#define SPINLOCK_LOCK8_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK9_ADDR 0x124
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#define SPINLOCK_LOCK9_OFFSET 0
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#define SPINLOCK_LOCK9_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK10_ADDR 0x128
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#define SPINLOCK_LOCK10_OFFSET 0
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#define SPINLOCK_LOCK10_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK11_ADDR 0x12C
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#define SPINLOCK_LOCK11_OFFSET 0
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#define SPINLOCK_LOCK11_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK12_ADDR 0x130
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#define SPINLOCK_LOCK12_OFFSET 0
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#define SPINLOCK_LOCK12_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK13_ADDR 0x134
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#define SPINLOCK_LOCK13_OFFSET 0
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#define SPINLOCK_LOCK13_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK14_ADDR 0x138
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#define SPINLOCK_LOCK14_OFFSET 0
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#define SPINLOCK_LOCK14_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK15_ADDR 0x13C
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#define SPINLOCK_LOCK15_OFFSET 0
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#define SPINLOCK_LOCK15_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK0_CLR_ADDR 0x200
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#define SPINLOCK0_LOCK_CLR_OFFSET 0
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#define SPINLOCK0_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK1_CLR_ADDR 0x204
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#define SPINLOCK1_LOCK_CLR_OFFSET 0
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#define SPINLOCK1_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK2_CLR_ADDR 0x208
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#define SPINLOCK2_LOCK_CLR_OFFSET 0
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#define SPINLOCK2_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK3_CLR_ADDR 0x20C
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#define SPINLOCK3_LOCK_CLR_OFFSET 0
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#define SPINLOCK3_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK4_CLR_ADDR 0x210
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#define SPINLOCK4_LOCK_CLR_OFFSET 0
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#define SPINLOCK4_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK5_CLR_ADDR 0x214
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#define SPINLOCK5_LOCK_CLR_OFFSET 0
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#define SPINLOCK5_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK6_CLR_ADDR 0x218
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#define SPINLOCK6_LOCK_CLR_OFFSET 0
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#define SPINLOCK6_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK7_CLR_ADDR 0x21C
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#define SPINLOCK7_LOCK_CLR_OFFSET 0
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#define SPINLOCK7_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK8_CLR_ADDR 0x220
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#define SPINLOCK8_LOCK_CLR_OFFSET 0
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#define SPINLOCK8_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK9_CLR_ADDR 0x224
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#define SPINLOCK9_LOCK_CLR_OFFSET 0
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#define SPINLOCK9_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK10_CLR_ADDR 0x228
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#define SPINLOCK10_LOCK_CLR_OFFSET 0
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#define SPINLOCK10_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK11_CLR_ADDR 0x22C
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#define SPINLOCK11_LOCK_CLR_OFFSET 0
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#define SPINLOCK11_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK12_CLR_ADDR 0x230
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#define SPINLOCK12_LOCK_CLR_OFFSET 0
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#define SPINLOCK12_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK13_CLR_ADDR 0x234
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#define SPINLOCK13_LOCK_CLR_OFFSET 0
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#define SPINLOCK13_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK14_CLR_ADDR 0x238
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#define SPINLOCK14_LOCK_CLR_OFFSET 0
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#define SPINLOCK14_LOCK_CLR_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SPINLOCK15_CLR_ADDR 0x23C
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#define SPINLOCK15_LOCK_CLR_OFFSET 0
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#define SPINLOCK15_LOCK_CLR_MASK 0x0000FFFF
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//HW module read/write macro
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#define SPINLOCK_TOP_READ_REG(addr) SOC_READ_REG(SPINLOCK_TOP_BASEADDR + addr)
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#define SPINLOCK_TOP_WRITE_REG(addr,value) SOC_WRITE_REG(SPINLOCK_TOP_BASEADDR + addr,value)
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