506 lines
22 KiB
C
506 lines
22 KiB
C
/* KL3 efuse mapping */
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#define CFG_EFUSE_MAPPING_ATE_SECTION_W0_ADDR 0x0000
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#define EFUSE_FUNC_ATE_LOT_ID0_OFFSET 0
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#define EFUSE_FUNC_ATE_LOT_ID0_MASK 0x000000ff
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#define EFUSE_FUNC_ATE_LOT_ID1_OFFSET 8
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#define EFUSE_FUNC_ATE_LOT_ID1_MASK 0x0000ff00
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#define EFUSE_FUNC_ATE_LOT_ID2_OFFSET 16
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#define EFUSE_FUNC_ATE_LOT_ID2_MASK 0x00ff0000
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#define EFUSE_FUNC_ATE_LOT_ID3_OFFSET 24
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#define EFUSE_FUNC_ATE_LOT_ID3_MASK 0xff000000
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#define CFG_EFUSE_MAPPING_ATE_SECTION_W1_ADDR 0x0004
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#define EFUSE_FUNC_ATE_LOT_ID4_OFFSET 0
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#define EFUSE_FUNC_ATE_LOT_ID4_MASK 0x000000ff
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#define EFUSE_FUNC_ATE_LOT_ID5_OFFSET 8
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#define EFUSE_FUNC_ATE_LOT_ID5_MASK 0x0000ff00
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#define EFUSE_FUNC_ATE_WAFER_ID_OFFSET 16
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#define EFUSE_FUNC_ATE_WAFER_ID_MASK 0x00ff0000
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#define EFUSE_FUNC_ATE_DIE_X_COORDINATE_OFFSET 24
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#define EFUSE_FUNC_ATE_DIE_X_COORDINATE_MASK 0xff000000
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#define CFG_EFUSE_MAPPING_ATE_SECTION_W2_ADDR 0x0008
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#define EFUSE_FUNC_ATE_DIE_Y_COORDINATE_OFFSET 0
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#define EFUSE_FUNC_ATE_DIE_Y_COORDINATE_MASK 0x000000ff
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#define EFUSE_FUNC_ATE_WAFER_REV_RECORD_OFFSET 8
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#define EFUSE_FUNC_ATE_WAFER_REV_RECORD_MASK 0x0000ff00
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#define EFUSE_FUNC_ATE_FT_PASS_FLAG_OFFSET 16
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#define EFUSE_FUNC_ATE_FT_PASS_FLAG_MASK 0x000f0000
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#define EFUSE_FUNC_ATE_ANALOG_BIN_VER_OFFSET 20
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#define EFUSE_FUNC_ATE_ANALOG_BIN_VER_MASK 0x00f00000
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#define EFUSE_FUNC_ATE_D_VREF_TUNE_DCDC_OFFSET 24
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#define EFUSE_FUNC_ATE_D_VREF_TUNE_DCDC_MASK 0x0f000000
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#define EFUSE_FUNC_ATE_FLASH_LDO_OUT_TRIM_18_OFFSET 28
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#define EFUSE_FUNC_ATE_FLASH_LDO_OUT_TRIM_18_MASK 0xf0000000
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#define CFG_EFUSE_MAPPING_ATE_SECTION_W3_ADDR 0x000C
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#define EFUSE_FUNC_ATE_D_MDLL_LDOVREF_TRIM_OFFSET 0
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#define EFUSE_FUNC_ATE_D_MDLL_LDOVERF_TRIM_MASK 0x0000000f
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#define EFUSE_FUNC_ATE_D_BG_VBG_CNTL_OFFSET 4
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#define EFUSE_FUNC_ATE_D_BG_VBG_CNTL_MASK 0x00000070
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#define EFUSE_FUNC_ATE_RESERVED0_OFFSET 7
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#define EFUSE_FUNC_ATE_RESERVED0_MASK 0x00000080
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#define EFUSE_FUNC_ATE_D_BG_ICCAL_OFFSET 8
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#define EFUSE_FUNC_ATE_D_BG_ICCAL_MASK 0x00001f00
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#define EFUSE_FUNC_ATE_RX_ADC_VCM_CTRL_OFFSET 13
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#define EFUSE_FUNC_ATE_RX_ADC_VCM_CTRL_MASK 0x0000e000
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#define EFUSE_FUNC_ATE_FLASH_LDO_OUT_TRIM_25_OFFSET 16
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#define EFUSE_FUNC_ATE_FLASH_LDO_OUT_TRIM_25_MASK 0x000f0000
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#define EFUSE_FUNC_ATE_RESERVED1_OFFSET 20
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#define EFUSE_FUNC_ATE_RESERVED1_MASK 0x00f00000
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#define EFUSE_FUNC_MARK_OFFSET 24
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#define EFUSE_FUNC_MARK_MASK 0x0f000000
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#define EFUSE_FUNC_WAFER_VER_OFFSET 28
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#define EFUSE_FUNC_WAFER_VER_MASK 0xf0000000
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#define CFG_EFUSE_MAPPING_ATE_SECTION_W4_ADDR 0x0010
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#define EFUSE_FUNC_SIP_OFFSET 0
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#define EFUSE_FUNC_SIP_MASK 0x0000000f
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#define EFUSE_FUNC_PROJECT_OFFSET 4
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#define EFUSE_FUNC_PROJECT_MASK 0x000000f0
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#define EFUSE_FUNC_ATE_RESERVED2_OFFSET 8
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#define EFUSE_FUNC_ATE_RESERVED2_MASK 0x0000ff00
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#define EFUSE_FUNC_ATE_MAC_ADDR0_OFFSET 16
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#define EFUSE_FUNC_ATE_MAC_ADDR0_MASK 0x00ff0000
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#define EFUSE_FUNC_ATE_MAC_ADDR1_OFFSET 24
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#define EFUSE_FUNC_ATE_MAC_ADDR1_MASK 0xff000000
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#define CFG_EFUSE_MAPPING_ATE_SECTION_W5_ADDR 0x0014
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#define EFUSE_FUNC_ATE_MAC_ADDR2_OFFSET 0
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#define EFUSE_FUNC_ATE_MAC_ADDR2_MASK 0x000000ff
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#define EFUSE_FUNC_ATE_MAC_ADDR3_OFFSET 8
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#define EFUSE_FUNC_ATE_MAC_ADDR3_MASK 0x0000ff00
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#define EFUSE_FUNC_ATE_MAC_ADDR4_OFFSET 16
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#define EFUSE_FUNC_ATE_MAC_ADDR4_MASK 0x00ff0000
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#define EFUSE_FUNC_ATE_MAC_ADDR5_OFFSET 24
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#define EFUSE_FUNC_ATE_MAC_ADDR5_MASK 0xff000000
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#define CFG_EFUSE_MAPPING_BOND_SECTION_W6_ADDR 0x0018
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#define EFUSE_FUNC_BOND_PHY_CFG0_GP_OFFSET 0
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#define EFUSE_FUNC_BOND_PHY_CFG0_GP_MASK 0x00000001
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#define EFUSE_FUNC_BOND_PHY_CFG1_SG_OFFSET 1
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#define EFUSE_FUNC_BOND_PHY_CFG1_SG_MASK 0x00000002
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#define EFUSE_FUNC_BOND_PHY_CFG2_GD_OFFSET 2
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#define EFUSE_FUNC_BOND_PHY_CFG2_GD_MASK 0x00000004
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#define EFUSE_FUNC_BOND_PHY_CFG3_G3_OFFSET 3
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#define EFUSE_FUNC_BOND_PHY_CFG3_G3_MASK 0x00000008
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#define EFUSE_FUNC_BOND_PHY_CFG4_AV_OFFSET 4
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#define EFUSE_FUNC_BOND_PHY_CFG4_AV_MASK 0x00000010
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#define EFUSE_FUNC_BOND_PHY_CFG5_1901_OFFSET 5
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#define EFUSE_FUNC_BOND_PHY_CFG5_1901_MASK 0x00000020
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#define EFUSE_FUNC_BOND_PHY_CFG6_RF_OFFSET 6
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#define EFUSE_FUNC_BOND_PHY_CFG6_RF_MASK 0x00000040
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#define EFUSE_FUNC_BOND_RESERVED0_OFFSET 7
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#define EFUSE_FUNC_BOND_RESERVED0_MASK 0x00000380
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#define EFUSE_FUNC_BOND_SEC_AES_SHA2_OFFSET 10
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#define EFUSE_FUNC_BOND_SEC_AES_SHA2_MASK 0x00000400
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#define EFUSE_FUNC_BOND_SEC_SM4_SM3_OFFSET 11
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#define EFUSE_FUNC_BOND_SEC_SM4_SM3_MASK 0x00000800
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#define EFUSE_FUNC_BOND_SEC_SM2_RSA_OFFSET 12
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#define EFUSE_FUNC_BOND_SEC_SM2_RSA_MASK 0x00001000
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#define EFUSE_FUNC_BOND_FFT_OFFSET 13
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#define EFUSE_FUNC_BOND_FFT_MASK 0x00002000
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#define EFUSE_FUNC_BOND_RF_BONDING_FIELD_OFFSET 14
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#define EFUSE_FUNC_BOND_RF_BONDING_FIELD_MASK 0x00004000
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#define EFUSE_FUNC_BOND_RESERVED1_OFFSET 15
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#define EFUSE_FUNC_BOND_RESERVED1_MASK 0x00008000
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#define EFUSE_FUNC_BOND_METER_SELP_OFFSET 16
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#define EFUSE_FUNC_BOND_METER_SELP_MASK 0x00010000
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#define EFUSE_FUNC_BOND_METER_SELN_OFFSET 17
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#define EFUSE_FUNC_BOND_METER_SELN_MASK 0x00020000
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#define EFUSE_FUNC_BOND_METER_ONE_PHASE_OFFSET 18
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#define EFUSE_FUNC_BOND_METER_ONE_PHASE_MASK 0x00040000
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#define EFUSE_FUNC_BOND_TPID_SELP_OFFSET 19
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#define EFUSE_FUNC_BOND_TPID_SELP_MASK 0x00080000
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#define EFUSE_FUNC_BOND_TPID_SELN_OFFSET 20
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#define EFUSE_FUNC_BOND_TPID_SELN_MASK 0x00100000
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#define EFUSE_FUNC_BOND_TPID_ONE_PHASE_OFFSET 21
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#define EFUSE_FUNC_BOND_TPID_ONE_PHASE_MASK 0x00200000
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#define EFUSE_FUNC_BOND_RESERVED2_OFFSET 22
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#define EFUSE_FUNC_BOND_RESERVED2_MASK 0xffc00000
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#define CFG_EFUSE_MAPPING_BOND_SECTION_W7_ADDR 0x001C
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#define EFUSE_FUNC_BOND_PHY_CFG0_GP_BAK_OFFSET 0
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#define EFUSE_FUNC_BOND_PHY_CFG0_GP_BAK_MASK 0x00000001
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#define EFUSE_FUNC_BOND_PHY_CFG1_SG_BAK_OFFSET 1
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#define EFUSE_FUNC_BOND_PHY_CFG1_SG_BAK_MASK 0x00000002
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#define EFUSE_FUNC_BOND_PHY_CFG2_GD_BAK_OFFSET 2
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#define EFUSE_FUNC_BOND_PHY_CFG2_GD_BAK_MASK 0x00000004
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#define EFUSE_FUNC_BOND_PHY_CFG3_G3_BAK_OFFSET 3
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#define EFUSE_FUNC_BOND_PHY_CFG3_G3_BAK_MASK 0x00000008
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#define EFUSE_FUNC_BOND_PHY_CFG4_AV_BAK_OFFSET 4
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#define EFUSE_FUNC_BOND_PHY_CFG4_AV_BAK_MASK 0x00000010
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#define EFUSE_FUNC_BOND_PHY_CFG5_1901_BAK_OFFSET 5
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#define EFUSE_FUNC_BOND_PHY_CFG5_1901_BAK_MASK 0x00000020
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#define EFUSE_FUNC_BOND_PHY_CFG6_RF_BAK_OFFSET 6
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#define EFUSE_FUNC_BOND_PHY_CFG6_RF_BAK_MASK 0x00000040
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#define EFUSE_FUNC_BOND_RESERVED0_BAK_OFFSET 7
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#define EFUSE_FUNC_BOND_RESERVED0_BAK_MASK 0x00000380
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#define EFUSE_FUNC_BOND_SEC_AES_SHA2_BAK_OFFSET 10
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#define EFUSE_FUNC_BOND_SEC_AES_SHA2_BAK_MASK 0x00000400
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#define EFUSE_FUNC_BOND_SEC_SM4_SM3_BAK_OFFSET 11
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#define EFUSE_FUNC_BOND_SEC_SM4_SM3_BAK_MASK 0x00000800
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#define EFUSE_FUNC_BOND_SEC_SM2_RSA_BAK_OFFSET 12
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#define EFUSE_FUNC_BOND_SEC_SM2_RSA_BAK_MASK 0x00001000
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#define EFUSE_FUNC_BOND_FFT_BAK_OFFSET 13
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#define EFUSE_FUNC_BOND_FFT_BAK_MASK 0x00002000
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#define EFUSE_FUNC_BOND_RF_BONDING_FIELD_BAK_OFFSET 14
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#define EFUSE_FUNC_BOND_RF_BONDING_FIELD_BAK_MASK 0x00004000
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#define EFUSE_FUNC_BOND_RESERVED1_BAK_OFFSET 15
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#define EFUSE_FUNC_BOND_RESERVED1_BAK_MASK 0x00008000
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#define EFUSE_FUNC_BOND_METER_SELP_BAK_OFFSET 16
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#define EFUSE_FUNC_BOND_METER_SELP_BAK_MASK 0x00010000
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#define EFUSE_FUNC_BOND_METER_SELN_BAK_OFFSET 17
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#define EFUSE_FUNC_BOND_METER_SELN_BAK_MASK 0x00020000
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#define EFUSE_FUNC_BOND_METER_ONE_PHASE_BAK_OFFSET 18
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#define EFUSE_FUNC_BOND_METER_ONE_PHASE_BAK_MASK 0x00040000
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#define EFUSE_FUNC_BOND_TPID_SELP_BAK_OFFSET 19
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#define EFUSE_FUNC_BOND_TPID_SELP_BAK_MASK 0x00080000
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#define EFUSE_FUNC_BOND_TPID_SELN_BAK_OFFSET 20
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#define EFUSE_FUNC_BOND_TPID_SELN_BAK_MASK 0x00100000
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#define EFUSE_FUNC_BOND_TPID_ONE_PHASE_BAK_OFFSET 21
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#define EFUSE_FUNC_BOND_TPID_ONE_PHASE_BAK_MASK 0x00200000
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#define EFUSE_FUNC_BOND_RESERVED2_BAK_OFFSET 22
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#define EFUSE_FUNC_BOND_RESERVED2_BAK_MASK 0xffc00000
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#define CFG_EFUSE_MAPPING_IOMAP_SECTION_W8_ADDR 0x0020
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#define EFUSE_FUNC_IOMAP_VALID_FLAG_OFFSET 0
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#define EFUSE_FUNC_IOMAP_VALID_FLAG_MASK 0x00000001
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#define EFUSE_FUNC_IOMAP_VALUE_OFFSET 1
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#define EFUSE_FUNC_IOMAP_VALUE_MASK 0xfffffffe
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#define CFG_EFUSE_MAPPING_IOMAP_SECTION_W9_ADDR 0x0024
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#define EFUSE_FUNC_IOMAP_VALID_FLAG_BAK_OFFSET 0
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#define EFUSE_FUNC_IOMAP_VALID_FLAG_BAK_MASK 0x00000001
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#define EFUSE_FUNC_IOMAP_VALUE_BAK_OFFSET 1
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#define EFUSE_FUNC_IOMAP_VALUE_BAK_MASK 0xfffffffe
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#define CFG_EFUSE_MAPPING_SYS_ANA_SECTION_W10_ADDR 0x0028
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_POWER_OFFSET 0
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_POWER_MASK 0x00000003
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_WDG_OFFSET 2
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_WDG_MASK 0x0000000c
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#define EFUSE_FUNC_SYSTEM_ROM_MSG_EB_OFFSET 4
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#define EFUSE_FUNC_SYSTEM_ROM_MSG_EB_MASK 0x00000010
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#define EFUSE_FUNC_SYSTEM_RESERVED0_OFFSET 5
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#define EFUSE_FUNC_SYSTEM_RESERVED0_MASK 0x000000e0
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_POWER_BAK_OFFSET 8
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_POWER_BAK_MASK 0x00000300
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_WDG_BAK_OFFSET 10
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#define EFUSE_FUNC_SYSTEM_SBL_CRC_EB_WDG_BAK_MASK 0x00000c00
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#define EFUSE_FUNC_SYSTEM_ROM_MSG_EB_BAK_OFFSET 12
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#define EFUSE_FUNC_SYSTEM_ROM_MSG_EB_BAK_MASK 0x00001000
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#define EFUSE_FUNC_SYSTEM_RESERVED1_OFFSET 13
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#define EFUSE_FUNC_SYSTEM_RESERVED1_MASK 0x0000e000
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#define EFUSE_FUNC_ANA_DATA0_OFFSET 16
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#define EFUSE_FUNC_ANA_DATA0_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_ANA_SECTION_W11_ADDR 0x002C
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#define EFUSE_FUNC_ANA_DATA1_OFFSET 0
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#define EFUSE_FUNC_ANA_DATA1_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_ANA_SECTION_W12_ADDR 0x0030
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#define EFUSE_FUNC_ANA_DATA2_OFFSET 0
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#define EFUSE_FUNC_ANA_DATA2_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_ANA_SECTION_W13_ADDR 0x0034
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#define EFUSE_FUNC_ANA_DATA3_OFFSET 0
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#define EFUSE_FUNC_ANA_DATA3_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_ANA_PATCH_SECTION_W14_ADDR 0x0038
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#define EFUSE_FUNC_ANA_DATA4_OFFSET 0
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#define EFUSE_FUNC_ANA_DATA4_MASK 0x0000ffff
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#define EFUSE_FUNC_PATCH_VALID_FLAG_OFFSET 16
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#define EFUSE_FUNC_PATCH_VALID_FLAG_MASK 0x00ff0000
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#define EFUSE_FUNC_PATCH_VALID_FLAG_BAK_OFFSET 24
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#define EFUSE_FUNC_PATCH_VALID_FLAG_BAK_MASK 0xff000000
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W15_ADDR 0x003c
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#define EFUSE_FUNC_PATCH_POSITION0_OFFSET 0
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#define EFUSE_FUNC_PATCH_POSITION0_MASK 0x0000000f
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#define EFUSE_FUNC_PATCH_POSITION1_OFFSET 4
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#define EFUSE_FUNC_PATCH_POSITION1_MASK 0x000000f0
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#define EFUSE_FUNC_PATCH_POSITION2_OFFSET 8
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#define EFUSE_FUNC_PATCH_POSITION2_MASK 0x00000f00
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#define EFUSE_FUNC_PATCH_POSITION3_OFFSET 12
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#define EFUSE_FUNC_PATCH_POSITION3_MASK 0x0000f000
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#define EFUSE_FUNC_PATCH_RESV_OFFSET 16
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#define EFUSE_FUNC_PATCH_RESV_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W16_ADDR 0x0040
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#define EFUSE_FUNC_PATCH_ADDR0_OFFSET 0
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#define EFUSE_FUNC_PATCH_ADDR0_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W17_ADDR 0x0044
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#define EFUSE_FUNC_PATCH_DATA0_OFFSET 0
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#define EFUSE_FUNC_PATCH_DATA0_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W18_ADDR 0x0048
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#define EFUSE_FUNC_PATCH_ADDR1_OFFSET 0
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#define EFUSE_FUNC_PATCH_ADDR1_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W19_ADDR 0x004c
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#define EFUSE_FUNC_PATCH_DATA1_OFFSET 0
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#define EFUSE_FUNC_PATCH_DATA1_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W20_ADDR 0x0050
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#define EFUSE_FUNC_PATCH_ADDR2_OFFSET 0
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#define EFUSE_FUNC_PATCH_ADDR2_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W21_ADDR 0x0054
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#define EFUSE_FUNC_PATCH_DATA2_OFFSET 0
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#define EFUSE_FUNC_PATCH_DATA2_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W22_ADDR 0x0058
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#define EFUSE_FUNC_PATCH_ADDR3_OFFSET 0
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#define EFUSE_FUNC_PATCH_ADDR3_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W23_ADDR 0x005c
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#define EFUSE_FUNC_PATCH_DATA3_OFFSET 0
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#define EFUSE_FUNC_PATCH_DATA3_MASK 0xffffffff
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#define CFG_EFUSE_MAPPING_SADC_2_SECTION_W24_ADDR 0x0060
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_N12DB_OFFSET 0
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_N12DB_MASK 0x0000ffff
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_N6DB_OFFSET 16
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_N6DB_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_SADC_2_SECTION_W25_ADDR 0x0064
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_12DB_OFFSET 0
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_12DB_MASK 0x0000ffff
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_24DB_OFFSET 16
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#define EFUSE_FUNC_SADC_2_TPID_DC_OFFSET_24DB_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_SADC_2_SECTION_W26_ADDR 0x0068
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_N12DB_OFFSET 0
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_N12DB_MASK 0x0000ffff
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_N6DB_OFFSET 16
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_N6DB_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_SADC_2_SECTION_W27_ADDR 0x006c
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_12DB_OFFSET 0
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_12DB_MASK 0x0000ffff
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_24DB_OFFSET 16
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#define EFUSE_FUNC_SADC_2_METER_DC_OFFSET_24DB_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_PATCH_SECTION_W28_ADDR 0x0070
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#define EFUSE_FUNC_PATCH_ADDR6_RESERVED0_OFFSET 0
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#define EFUSE_FUNC_PATCH_ADDR6_RESERVED0_MASK 0x0000ffff
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#define EFUSE_FUNC_PATCH_SUB_MARK_OFFSET 16
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#define EFUSE_FUNC_PATCH_SUB_MARK_MASK 0x000f0000
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#define EFUSE_FUNC_PATCH_SUB_WAFER_VER_OFFSET 20
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#define EFUSE_FUNC_PATCH_SUB_WAFER_VER_MASK 0x00f00000
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#define EFUSE_FUNC_PATCH_SUB_SIP_OFFSET 24
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#define EFUSE_FUNC_PATCH_SUB_SIP_MASK 0x0f000000
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#define EFUSE_FUNC_PATCH_SUB_PROJECT_OFFSET 28
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#define EFUSE_FUNC_PATCH_SUB_PROJECT_MASK 0xf0000000
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#define CFG_EFUSE_MAPPING_SADC_SECTION_W29_ADDR 0x0074
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#define EFUSE_FUNC_SADC_TPID_DC_OFFSET_OFFSET 0
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#define EFUSE_FUNC_SADC_TPID_DC_OFFSET_MASK 0x0000ffff
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#define EFUSE_FUNC_SADC_TPID_VREF_OFFSET 16
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#define EFUSE_FUNC_SADC_TPID_VREF_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_SADC_SECTION_W30_ADDR 0x0078
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#define EFUSE_FUNC_SADC_TPID_VCM_OFFSET 0
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#define EFUSE_FUNC_SADC_TPID_VCM_MASK 0x0000ffff
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#define EFUSE_FUNC_SADC_METER_DC_OFFSET_OFFSET 16
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#define EFUSE_FUNC_SADC_METER_DC_OFFSET_MASK 0xffff0000
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#define CFG_EFUSE_MAPPING_SADC_SECTION_W31_ADDR 0x007c
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#define EFUSE_FUNC_SADC_METER_VREF_OFFSET 0
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#define EFUSE_FUNC_SADC_METER_VREF_MASK 0x0000ffff
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#define EFUSE_FUNC_SADC_METER_VCM_OFFSET 16
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#define EFUSE_FUNC_SADC_METER_VCM_MASK 0xffff0000
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#pragma pack(push) /* save the pack status */
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#pragma pack(1) /* 1 byte align */
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typedef struct _efuse_section_ate_t {
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uint8_t lot_id[6]; //byte 0~5
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uint8_t wafer_id; //byte 6
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uint8_t x_coor; //byte 7
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uint8_t y_coor; //byte 8
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uint8_t wafer_rev; //byte 9
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uint8_t ft_pass_flag : 4,
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analog_bin_ver : 4;
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uint8_t dcdc_1p1 : 4,
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ldo_1p8 : 4;
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uint8_t mdll_ldo_1p1 : 4,
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vbg_cntl : 3,
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resv_1 : 1;
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uint8_t ic_cal : 5,
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rx_adc_vcm_ctrl : 3;
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uint8_t ldo_2p5 : 4,
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resv_2 : 4;
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uint8_t mark : 4,
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wafer_ver : 4;
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/* sip[3]:rf_in, sip[2]:pa_in, sip[1]:psram_in, sip[0]:flash_in */
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uint8_t sip : 4,
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project : 4;
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uint8_t resv_3;
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uint8_t mac[6];
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} efuse_section_ate_t;
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typedef struct _efuse_section_bond_t {
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uint8_t phy_cfg0_gp : 1,
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phy_cfg1_sg : 1,
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phy_cfg2_gd : 1,
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phy_cfg3_g3 : 1,
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phy_cfg4_av : 1,
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phy_cfg5_ieee1901 : 1,
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phy_cfg6_rfplc : 1,
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resv_1 : 1;
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uint8_t resv_2 : 2,
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sec_aes_sha2 : 1,
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sec_sm4_sm3 : 1,
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sec_sm2_rsa : 1,
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fft : 1,
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rfplc_bonding : 1,
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resfv_3 : 1;
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uint8_t meter_selp : 1,
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meter_seln : 1,
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meter_one_phase : 1,
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tpid_selp : 1,
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tpid_seln : 1,
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tpid_one_phase : 1,
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resv_4 : 2;
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uint8_t resv_5;
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uint8_t phy_cfg0_gp_bak : 1,
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phy_cfg1_sg_bak : 1,
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phy_cfg2_gd_bak : 1,
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phy_cfg3_g3_bak : 1,
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phy_cfg4_av_bak : 1,
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phy_cfg5_ieee1901_bak : 1,
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phy_cfg6_rfplc_bak : 1,
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resv_1_bak : 1;
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uint8_t resv_2_bak : 2,
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sec_aes_sha2_bak : 1,
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sec_sm4_sm3_bak : 1,
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sec_sm2_rsa_bak : 1,
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fft_bak : 1,
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rfplc_bonding_bak : 1,
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resfv_3_bak : 1;
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uint8_t meter_selp_bak : 1,
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meter_seln_bak : 1,
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meter_one_phase_bak : 1,
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tpid_selp_bak : 1,
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tpid_seln_bak : 1,
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tpid_one_phase_bak : 1,
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resv_4_bak : 2;
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uint8_t resv_5_bak;
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} efuse_section_bond_t;
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typedef struct _efuse_section_iomap_t {
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uint32_t iomap; //bit0 is flag, 1->valid, 0->invalid
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uint32_t iomap_bak; //bit0 is flag, 1->valid, 0->invalid
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} efuse_section_iomap_t;
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typedef struct _efuse_section_system_config_t {
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uint8_t sbl_crc_power_on : 2, //00->check crc while not fast boot, 01/10->check crc, 11->not check
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sbl_crc_wdg_rst : 2, //00->check crc while not fast boot, 01/10->check crc, 11->not check
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rom_err_msg_en : 1,
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resv : 3;
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uint8_t sbl_crc_power_on_bak : 2, //00->check crc while not fast boot, 01/10->check crc, 11->not check
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sbl_crc_wdg_rst_bak : 2, //00->check crc while not fast boot, 01/10->check crc, 11->not check
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rom_err_msg_en_bak : 1,
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resv_bak : 3;
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} efuse_section_system_config_t;
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/* define valid marks for different types calibration information in ana
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* section.
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*/
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#define EFULSE_SEC_ANA_VALID_MARK_RF_TX_IQM_DC_CALIB (1 << 0)
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/* rf tx iqm and dc calibration compensate info layout */
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typedef struct {
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/* tx I MAG balance compensate value, range: 0~15 */
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uint8_t i_mag : 4,
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/* tx Q MAG balance compensate value, range: 0~15 */
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q_mag : 4;
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/* tx I phase compensate value, range: 0~31 */
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uint8_t i_phase;
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/* tx Q phase compensate value, range: 0~31 */
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uint8_t q_phase;
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/* tx I dc compensate value, range: -127~127 */
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int8_t i_dc;
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/* tx Q dc compensate value, range: -127~127 */
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int8_t q_dc;
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} efuse_section_ana_rf_tx_iqm_dc_t;
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/* rf calibration compensation information layout */
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typedef struct _efuse_section_ana_t {
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/* compensate value valid mark flag bm
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* bit0: rf tx iqm and dc calibration compensate value valid mark
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* bit1~7: rsvd
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*/
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uint8_t valid_mark;
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/* rf tx iq mismatch and dc calibration info */
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efuse_section_ana_rf_tx_iqm_dc_t tx_iqm_dc;
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/* reserved for further use */
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uint8_t rsvd[10];
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} efuse_section_ana_t;
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typedef struct _efsue_section_rom_patch_t {
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uint8_t valid_flag; //patch0~6 valid flag
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uint8_t valid_flag_bak; //patch0~6 valid flag
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uint8_t patch_0_pos : 4,
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patch_1_pos : 4;
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uint8_t patch_2_pos : 4,
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patch_3_pos : 4;
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uint8_t resv[2];
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uint32_t patch_0_addr;
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uint32_t patch_0_data;
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uint32_t patch_1_addr;
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uint32_t patch_1_data;
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uint32_t patch_2_addr;
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uint32_t patch_2_data;
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uint32_t patch_3_addr;
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uint32_t patch_3_data;
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} efuse_section_rom_patch_t;
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typedef struct _efuse_section_sadc_2_t {
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uint16_t tpid_dc_offset_n12db;
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uint16_t tpid_dc_offset_n6db;
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uint16_t tpid_dc_offset_12db;
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uint16_t tpid_dc_offset_24db;
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uint16_t meter_dc_offset_n12db;
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uint16_t meter_dc_offset_n6db;
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uint16_t meter_dc_offset_12db;
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uint16_t meter_dc_offset_24db;
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} efuse_section_sadc_2_t;
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typedef struct _efsue_section_subid_t {
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uint8_t resv_2[2];
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uint8_t sub_mark : 4,
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sub_wafer_ver : 4;
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/* sip[3]:rf_in, sip[2]:pa_in, sip[1]:psram_in, sip[0]:flash_in */
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uint8_t sub_sip : 4,
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sub_project : 4;
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} efuse_section_subid_t;
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typedef struct _efuse_section_sadc_t {
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uint16_t tpid_dc_offset_code;
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uint16_t tpid_vref_code;
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uint16_t tpid_vcm_code;
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uint16_t meter_dc_offset_code;
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uint16_t meter_vref_code;
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uint16_t meter_vcm_code;
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} efuse_section_sadc_t;
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typedef struct _efuse_section_t {
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efuse_section_ate_t ate;
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efuse_section_bond_t bond;
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efuse_section_iomap_t iomap;
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efuse_section_system_config_t system;
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efuse_section_ana_t ana;
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efuse_section_rom_patch_t rom_patch;
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efuse_section_sadc_2_t sadc_2;
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efuse_section_subid_t subid;
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efuse_section_sadc_t sadc;
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} efuse_section_t;
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#pragma pack(pop) /* restore the pack status */
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