519 lines
15 KiB
C
Executable File
519 lines
15 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "os_types.h"
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/* mac module internal includes */
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#include "mac_vdev.h"
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#include "mac_pdev.h"
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#include "command_list.h"
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#include "hw_reg_api.h"
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#include "mac_sys_reg.h"
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#include "mac_hwq_reg.h"
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/* public api includes */
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#include "plc_fr.h"
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#include "tx_mpdu_start.h"
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#include "mac_txq_hw.h"
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#include "mac_status.h"
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#include "os_utils.h"
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#include "mac_reset.h"
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#include "os_task.h"
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#if MAC_SCHED_HW_DEBUG || ENA_WAR_911
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#include "iot_io.h"
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#endif
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#include "multi_nid_sync.h"
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#include "phy_reg.h"
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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#if ENA_WAR_440
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#include "phy_bb.h"
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#endif
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void mac_sched_enable_hw_ntb_sync(mac_vdev_t *vdev, uint8_t enable)
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{
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uint32_t value;
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/* disable irq */
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os_disable_irq();
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value = RGF_MAC_READ_REG(CFG_NTB_SYNC_0_ADDR);
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if (enable) {
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REG_FIELD_SET(CFG_HW_NTB_SYNC_EN, value, 1);
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REG_FIELD_SET(CFG_NTB_SW_SYNC_CLR, value, 1);
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} else {
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REG_FIELD_SET(CFG_HW_NTB_SYNC_EN, value, 0);
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REG_FIELD_SET(CFG_NTB_HW_SYNC_CLR, value, 1);
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}
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_0_ADDR, value);
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/* enable irq */
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os_enable_irq();
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}
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void mac_record_sync_ntb_overflow(uint64_t st_ntb, uint32_t result)
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{
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/* bitmap 0 1 3 4 */
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#define SYNC_OVERFLOW_NTB_WAY_1 0x1B
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/* bitmap 0 1 3 5 */
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#define SYNC_OVERFLOW_NTB_WAY_2 0x2B
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/* bitmap 0 2 3 4 */
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#define SYNC_OVERFLOW_NTB_WAY_3 0x1D
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/* bitmap 0 2 3 5 */
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#define SYNC_OVERFLOW_NTB_WAY_4 0x2D
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/* bitmap 6 */
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#define SYNC_OVERFLOW_NTB_WAY_5 0x40
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mac_pdev_t *pdev = get_pdev_ptr(PLC_PDEV_ID);
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mac_sync_ntb_record_t *sync_ntb_record = &pdev->mac_status.sync_ntb_record;
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uint64_t cur_ntb = mac_sched_get_ntb64(NULL);
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switch (result) {
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case SYNC_OVERFLOW_NTB_WAY_1 :
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sync_ntb_record->sync_ntb_ovf_way1_cnt++;
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if (iot_uint64_higher32(cur_ntb) - iot_uint64_higher32(st_ntb) == 1) {
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sync_ntb_record->way1_success_cnt++;
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}
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break;
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case SYNC_OVERFLOW_NTB_WAY_2 :
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sync_ntb_record->sync_ntb_ovf_way2_cnt++;
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if (iot_uint64_higher32(cur_ntb) - iot_uint64_higher32(st_ntb) == 1) {
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sync_ntb_record->way2_success_cnt++;
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}
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break;
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case SYNC_OVERFLOW_NTB_WAY_3 :
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sync_ntb_record->sync_ntb_ovf_way3_cnt++;
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if (iot_uint64_higher32(cur_ntb) - iot_uint64_higher32(st_ntb) == 1) {
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sync_ntb_record->way3_success_cnt++;
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}
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break;
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case SYNC_OVERFLOW_NTB_WAY_4 :
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sync_ntb_record->sync_ntb_ovf_way4_cnt++;
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if (iot_uint64_higher32(cur_ntb) - iot_uint64_higher32(st_ntb) == 1) {
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sync_ntb_record->way4_success_cnt++;
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}
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break;
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case SYNC_OVERFLOW_NTB_WAY_5 :
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sync_ntb_record->sync_ntb_ovf_way5_cnt++;
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break;
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default:
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sync_ntb_record->sync_ntb_ovf_way6_cnt++;
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break;
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}
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}
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void mac_sched_sync_ntb(mac_vdev_t *vdev, uint16_t golden_gap,
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int32_t ntb_delta)
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{
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uint32_t value;
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(void)vdev;
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/* disable irq */
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os_disable_irq();
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value = RGF_MAC_READ_REG(CFG_NTB_SYNC_0_ADDR);
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value |= CFG_NTB_DELTA_VAL_SIGN_MASK | CFG_MODIFY_NTB_EN_MASK;
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if (golden_gap) {
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/* set golden gap only when it's non-zero, this value shouldn't be
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* changed once set.
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*/
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value &= ~CFG_NTB_GOLDEN_GAP_MASK;
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value |= (((uint32_t)golden_gap) << CFG_NTB_GOLDEN_GAP_OFFSET)
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& CFG_NTB_GOLDEN_GAP_MASK;
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}
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if (!(value & CFG_HW_NTB_SYNC_EN_MASK)) {
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/* make sure HW don't sync NTB blindly */
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IOT_ASSERT(RGF_MAC_READ_REG(CFG_RO_NTB_HW_SYNC_VAL_ADDR) == 0);
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}
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uint32_t u_ntb_delta = 0;
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#if ENA_WAR_911
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uint32_t result = 0;
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/* war for hw bug, low bit overflow high bit not + 1 */
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uint32_t ntb_delta_a = 0;
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uint32_t ntb_delta_b = 0;
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uint64_t cur_ntb = mac_sched_get_ntb64(NULL);
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if (ntb_delta >= 0) {
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/* positive */
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uint64_t temp_ntb = (uint64_t)iot_uint64_lower32(cur_ntb) + ntb_delta;
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/* if overflow */
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if (iot_uint64_higher32(temp_ntb) >= 1) {
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result |= 1 << 0;
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/* set delta part a */
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ntb_delta_a = MAX_UINT32_NTB - iot_uint64_lower32(cur_ntb);
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if (ntb_delta_a > (RESERVE_NTB + (RESERVE_NTB >> 1))) {
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result |= 1 << 1;
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ntb_delta_a = ntb_delta_a - RESERVE_NTB;
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/* set part a to register */
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_1_ADDR, ntb_delta_a);
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_0_ADDR, value);
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} else {
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result |= 1 << 2;
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ntb_delta_a = 0;
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}
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IOT_ASSERT(ntb_delta >= ntb_delta_a);
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/* set delta part b */
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ntb_delta_b = ntb_delta - ntb_delta_a;
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/* delay to wait hight bit +1 */
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temp_ntb = mac_sched_get_ntb64(NULL);
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/* check ntb is normal */
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if (iot_uint64_higher32(temp_ntb) >= iot_uint64_higher32(cur_ntb)) {
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result |= 1 << 3;
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/* wait overflow happen */
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uint32_t time_span = 0;
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uint32_t cur_ntb_temp = 0;
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do {
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cur_ntb_temp = mac_sched_get_ntb(NULL);
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time_span = cur_ntb_temp - iot_uint64_lower32(temp_ntb);
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} while (cur_ntb_temp > (MAX_UINT32_NTB >> 1) &&
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time_span < DELAY_MAX_NTB);
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/* check which condition jumps out of the while */
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if (cur_ntb_temp < (MAX_UINT32_NTB >> 1)) {
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result |= 1 << 4;
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/* set delta next part */
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u_ntb_delta = ntb_delta_b;
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} else {
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result |= 1 << 5;
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/* timeout and give up this sync part b */
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u_ntb_delta = 0;
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iot_printf("%s wait overflow timeout\n", __FUNCTION__);
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}
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} else {
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iot_printf("%s sync ntb error\n", __FUNCTION__);
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IOT_ASSERT(0);
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}
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} else {
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u_ntb_delta = ntb_delta;
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}
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} else {
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/* negative */
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if ((iot_uint64_lower32(cur_ntb) < (-ntb_delta)) &&
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(vdev_get_tei(vdev) != PLC_TEI_INVAL)) {
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result |= 1 << 6;
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u_ntb_delta = iot_uint64_lower32(cur_ntb);
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} else {
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u_ntb_delta = MAX_UINT32_NTB + ntb_delta;
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}
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}
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/* launch ntb delta first as enable NTB modify bit will cause HW
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* launch the delta value right away.
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*/
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_1_ADDR, u_ntb_delta);
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_0_ADDR, value);
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/* enable irq */
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os_enable_irq();
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if (result) {
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mac_record_sync_ntb_overflow(cur_ntb, result);
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}
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#else
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if (ntb_delta < 0) {
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u_ntb_delta = MAX_UINT32_NTB + ntb_delta;
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} else {
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u_ntb_delta = ntb_delta;
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}
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/* launch ntb delta first as enable NTB modify bit will cause HW
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* launch the delta value right away.
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*/
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_1_ADDR, u_ntb_delta);
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RGF_MAC_WRITE_REG(CFG_NTB_SYNC_0_ADDR, value);
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/* enable irq */
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os_enable_irq();
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#endif
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#if MAC_SCHED_HW_DEBUG
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iot_printf("MAC_SCHED_HW ---%s--- CFG_NTB_SYNC_0_ADDR %x\n", __FUNCTION__,
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value);
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iot_printf("MAC_SCHED_HW ---%s--- CFG_NTB_SYNC_1_ADDR %d\n", __FUNCTION__,
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ntb_delta);
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#endif
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}
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uint32_t IRAM_ATTR mac_sched_get_ntb(mac_vdev_t *vdev)
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{
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(void)vdev;
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return RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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}
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uint32_t IRAM_ATTR mac_sched_get_lts()
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{
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return RGF_MAC_READ_REG(CFG_RD_LOCAL_TMR_ADDR);
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}
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uint32_t mac_sched_get_neighbor_ntb(mac_vdev_t *vdev, nid_t nid)
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{
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#if (HW_PLATFORM >= HW_PLATFORM_FPGA)
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if (mac_multi_sync_get_ena(vdev->ref_pdev_id)) {
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uint32_t ntb = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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if (ERR_OK == mac_myntb_to_other_ntb(vdev->ref_pdev_id, nid, &ntb, 1)) {
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return ntb;
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} else {
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return 0;
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}
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} else {
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return 0;
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}
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#else
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(void)vdev;
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(void)nid;
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return 0;
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#endif
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}
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uint64_t IRAM_ATTR mac_sched_get_ntb64(mac_vdev_t *vdev)
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{
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uint32_t ntb;
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uint64_t ntb64_a, ntb64_b;
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(void)vdev;
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ntb64_a = RGF_MAC_READ_REG(CFG_RO_NTB_TMR_WRAP_ADDR);
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ntb = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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ntb64_b = RGF_MAC_READ_REG(CFG_RO_NTB_TMR_WRAP_ADDR);
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if (ntb64_b != ntb64_a) {
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/* wrap round happened */
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ntb = RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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}
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ntb64_b = (ntb64_b << 32) | ntb;
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return ntb64_b;
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}
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void mac_sched_set_bp_ahead_alert(mac_vdev_t *vdev, uint16_t ahead)
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{
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uint32_t value;
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(void)vdev;
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value = (((uint32_t)ahead) << CFG_BCN_ALERT_AHEAD_OFFSET)
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& CFG_BCN_ALERT_AHEAD_MASK;
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RGF_MAC_WRITE_REG(CFG_BEACON_ADDR, value);
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#if MAC_SCHED_HW_DEBUG
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iot_printf("MAC_SCHED_HW ---%s--- CFG_BEACON_ADDR %x\n", __FUNCTION__,
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value);
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#endif
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}
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void mac_sched_set_recursive_mode(mac_vdev_t *vdev, uint8_t enable)
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{
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uint32_t value;
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(void)vdev;
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value = RGF_HWQ_READ_REG(CFG_SCHEDULE_ADDR);
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value &= ~CFG_SCH_SELF_RECUR_EN_MASK;
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value |= ((uint32_t)(enable & 0x01)) << CFG_SCH_SELF_RECUR_EN_OFFSET;
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RGF_HWQ_WRITE_REG(CFG_SCHEDULE_ADDR, value);
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#if MAC_SCHED_HW_DEBUG
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iot_printf("MAC_SCHED_HW ---%s--- CFG_SCHEDULE_ADDR %x\n", __FUNCTION__,
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value);
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#endif
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}
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/* config start ntb of next beacon period */
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void mac_sched_set_bp_start_ntb(mac_vdev_t *vdev,
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uint32_t start_ntb)
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{
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(void)vdev;
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#if ENA_WAR_440
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g_phy_cpu_share_ctxt.bcn_start_update_ntb = \
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RGF_MAC_READ_REG(CFG_RD_NTB_ADDR);
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#endif
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RGF_MAC_WRITE_REG(CFG_BCN_START_NTB_ADDR, start_ntb);
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#if MAC_SCHED_HW_DEBUG
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iot_printf("MAC_SCHED_HW ---%s--- CFG_BCN_START_NTB_ADDR %x\n",
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__FUNCTION__, start_ntb);
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#endif
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}
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uint32_t mac_sched_get_bp_start_ntb()
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{
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return RGF_MAC_READ_REG(CFG_BCN_START_NTB_ADDR);
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}
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uint32_t mac_sched_get_bp_dur()
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{
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uint32_t tmp = RGF_MAC_READ_REG(CFG_BEACON_PERIOD_ADDR);
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return REG_FIELD_GET(CFG_BEACON_PERIOD, tmp);
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}
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/* config next beacon period duration */
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void mac_sched_set_bp_dur(mac_vdev_t *vdev, uint16_t bp)
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{
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uint32_t value;
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(void)vdev;
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value = (((uint32_t)bp) << CFG_BEACON_PERIOD_OFFSET)
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& CFG_BEACON_PERIOD_MASK;
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RGF_MAC_WRITE_REG(CFG_BEACON_PERIOD_ADDR, value);
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#if MAC_SCHED_HW_DEBUG
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iot_printf("MAC_SCHED_HW ---%s--- CFG_BEACON_PERIOD_ADDR %x\n",
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__FUNCTION__, value);
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#endif
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}
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/* config scheduler of next beacon period */
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void mac_sched_set_bp_cmd_list(mac_vdev_t *vdev, hw_sched_cmd_t *cmd,
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uint16_t cnt)
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{
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uint32_t value;
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(void)vdev;
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value = RGF_HWQ_READ_REG(CFG_SCHEDULE_ADDR);
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value &= ~CFG_SCH_CMD_NUM_MASK;
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value |= (((uint32_t)cnt << 1) << CFG_SCH_CMD_NUM_OFFSET)
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& CFG_SCH_CMD_NUM_MASK;
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RGF_HWQ_WRITE_REG(CFG_SCHEDULE_ADDR, value);
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RGF_HWQ_WRITE_REG(CFG_SCH_PTR_ADDR, (uint32_t)cmd);
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#if MAC_SCHED_HW_DEBUG
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iot_printf("MAC_SCHED_HW ---%s--- CFG_SCHEDULE_ADDR %x\n", __FUNCTION__,
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value);
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iot_printf("MAC_SCHED_HW ---%s--- CFG_SCH_PTR_ADDR %x\n", __FUNCTION__,
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cmd);
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#endif
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}
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/* get cmd list cnt being used by HW */
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uint8_t mac_sched_get_cmd_list_cnt(mac_vdev_t *vdev)
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{
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uint32_t value;
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(void)vdev;
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value = RGF_HWQ_READ_REG(CFG_SCHEDULE_ADDR);
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value &= SCH_CUR_NUM_MASK;
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value >>= SCH_CUR_NUM_OFFSET;
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return (uint8_t)value;
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}
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/* write trigger for the next beacon period */
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void mac_sched_trigger_bp(mac_vdev_t *vdev)
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{
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uint32_t value;
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(void)vdev;
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value = RGF_HWQ_READ_REG(CFG_SCHEDULE_ADDR);
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if (value & SCH_WR_TRIG_ENABLE_MASK) {
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value |= 1 << CFG_SCH_WR_TRIG_OFFSET;
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RGF_HWQ_WRITE_REG(CFG_SCHEDULE_ADDR, value);
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} else {
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IOT_ASSERT(0);
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}
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#if MAC_SCHED_HW_DEBUG
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iot_printf("MAC_SCHED_HW ---%s--- CFG_SCHEDULE_ADDR %x\n", __FUNCTION__,
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value);
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#endif
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}
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#define SCHED_ENABLE_SYNC_MAX_LOOP 0xFFFFFFFE
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/* enable or disable scheduler of next beacon period */
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void mac_sched_enable_bp(mac_vdev_t *vdev, uint8_t enable)
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{
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uint32_t i, value;
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(void)vdev;
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value = RGF_HWQ_READ_REG(CFG_SCHEDULE_ADDR);
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/* check if HW scheduler already enabled or disabled */
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if ((!!(value & SCH_STATUS_MASK)) == (!!enable))
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return;
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/* enable or disable HW scheduler */
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value &= ~CFG_SCH_EN_MASK;
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value |= (((uint32_t)(enable & 0x01)) << CFG_SCH_EN_OFFSET)
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& CFG_SCH_EN_MASK;
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#if DEBUG_HWQ_SHCED_HANG
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/* WAR: if TX in progress, stop SCH would make hw tx hang
|
|
* to avoid this happen, we need to poll till we're not
|
|
* in TX process
|
|
*/
|
|
if (!!enable == 0) {
|
|
/* if to disable SCH */
|
|
uint32_t iscco = (PLC_DEV_ROLE_CCO == mac_vdev_cfg_get_node_role(vdev));
|
|
mac_tx_wait_all_queue_idle(iscco, MAC_WAIT_TX_IDLE_TIEM_MS);
|
|
}
|
|
#endif
|
|
RGF_HWQ_WRITE_REG(CFG_SCHEDULE_ADDR, value);
|
|
|
|
#if MAC_SCHED_HW_DEBUG
|
|
iot_printf("MAC_SCHED_HW ---%s--- CFG_SCHEDULE_ADDR %x\n", __FUNCTION__,
|
|
value);
|
|
#endif
|
|
#if DEBUG_HWQ_SHCED_HANG
|
|
uint32_t debug_cnt = 0;
|
|
#endif
|
|
if (!mac_txq_is_dbg_mode()) {
|
|
/* if sch mode */
|
|
/* make sure the HW scheduler status is in sync */
|
|
for (i = 0; i < SCHED_ENABLE_SYNC_MAX_LOOP; i++) {
|
|
value = RGF_HWQ_READ_REG(CFG_SCHEDULE_ADDR);
|
|
if ((!!(value & SCH_STATUS_MASK)) == (!!enable)) {
|
|
break;
|
|
}
|
|
if (i & 0x100) {
|
|
/* try to enable or disable again */
|
|
REG_FIELD_SET(CFG_SCH_EN, value, enable & 0x01);
|
|
RGF_HWQ_WRITE_REG(CFG_SCHEDULE_ADDR, value);
|
|
}
|
|
#if DEBUG_HWQ_SHCED_HANG
|
|
debug_cnt++;
|
|
if(debug_cnt > MAX_WAIT_DUMP_CNT)
|
|
{
|
|
mac_dump_buf(MAC_DUMP_TYPE_5, (uint32_t *)mac_txq_get_curr_desc_ptr(\
|
|
PLC_DEV_ROLE_CCO == mac_vdev_cfg_get_node_role(vdev), \
|
|
false), \
|
|
sizeof(tx_mpdu_start)/sizeof(uint32_t), \
|
|
(uint32_t *)RGF_HWQ_BASEADDR, 108, \
|
|
(uint32_t *)(PHY_BASEADDR + CFG_BB_RX_TD_DBG_BUS0_ADDR), 38, \
|
|
true);
|
|
}
|
|
#endif
|
|
}
|
|
if (i >= SCHED_ENABLE_SYNC_MAX_LOOP)
|
|
IOT_ASSERT(0);
|
|
}
|
|
|
|
if (!enable) {
|
|
/* clear schduler command list if scheduler disabled */
|
|
value = RGF_HWQ_READ_REG(CFG_SCHEDULE_ADDR);
|
|
value |= CFG_SCH_CLR_MASK;
|
|
RGF_HWQ_WRITE_REG(CFG_SCHEDULE_ADDR, value);
|
|
}
|
|
}
|
|
|
|
#endif /* HW_PLATFORM >= HW_PLATFORM_FPGA */
|