193 lines
5.5 KiB
C
Executable File
193 lines
5.5 KiB
C
Executable File
/****************************************************************************
|
|
|
|
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
|
|
|
|
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
|
|
be copied by any method or incorporated into another program without
|
|
the express written consent of Aerospace C.Power. This Information or any portion
|
|
thereof remains the property of Aerospace C.Power. The Information contained herein
|
|
is believed to be accurate and Aerospace C.Power assumes no responsibility or
|
|
liability for its use in any way and conveys no license or title under
|
|
any patent or copyright and makes no representation or warranty that this
|
|
Information is free from patent or copyright infringement.
|
|
|
|
****************************************************************************/
|
|
|
|
#ifndef MAC_DSR_H
|
|
#define MAC_DSR_H
|
|
|
|
/* os shim includes */
|
|
#include "os_types.h"
|
|
#include "os_mem.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/* mac dsr handler id definition. the lower the id, the higher the priority */
|
|
|
|
/* beacon alert dsr is used for HW to notify MAC to prepare for next beacon
|
|
* period.
|
|
*/
|
|
#define MAC_DSR_BC_ALERT_ID 0
|
|
|
|
/* generate when self's beacon received */
|
|
#define MAC_DSR_BC_RX_ID 1
|
|
|
|
/* generate when HW read tx start desc err */
|
|
#define MAC_DSR_START_DESC_ERR_ID 2
|
|
|
|
/* generate when HW read tx end desc err */
|
|
#define MAC_DSR_END_DESC_ERR_ID 3
|
|
|
|
/* generate when HW read pb desc err */
|
|
#define MAC_DSR_TX_UNDERRUN_ID 4
|
|
|
|
/* generate when a fc rx complete */
|
|
#define MAC_DSR_FC_RX_ID 5
|
|
|
|
/* generate when RX buf is run out for the desc */
|
|
#define MAC_DSR_RX_DESC_OVERFLOW_ID 6
|
|
|
|
/* generate when RX buf is not enough for the payload */
|
|
#define MAC_DSR_RX_LOAD_OVERFLOW_ID 7
|
|
|
|
/* generate when cfg number bcn missed, or a period of time without bcn seen */
|
|
#define MAC_DSR_BC_MISS_ID 8
|
|
|
|
/* generate when HW scheduler stop done */
|
|
#define MAC_DSR_SCH_STOP_ID 9
|
|
|
|
/* when sw disable the hwq, hwq need to complete
|
|
* the current transmit, after it done, generate this INT
|
|
*/
|
|
#define MAC_DSR_HWQ_STOP_ID 10
|
|
|
|
/* Zero cross report indication */
|
|
#define MAC_DSR_ZERO_CROSS_ID 11
|
|
|
|
|
|
/* generate when a mpdu tx complete */
|
|
#define MAC_DSR_MPDU_TX_COMP_ID 12
|
|
|
|
/* generate when a list of mpdus tx complete */
|
|
#define MAC_DSR_MPDU_LIST_TX_COMP_ID 13
|
|
|
|
/* generate when a mpdu rx complete */
|
|
#define MAC_DSR_MPDU_RX_ID 14
|
|
|
|
/* generate when a pb rx complete */
|
|
#define MAC_DSR_PB_RX_ID 15
|
|
|
|
/* RX ring buf num is under water mark */
|
|
#define MAC_DSR_RX_LOW_WATERMARK_ID 16
|
|
|
|
/* zc collect when upper bound intr */
|
|
#define MAC_DSR_ZC_UPPER_BOUND_ID 17
|
|
|
|
/* systic intr trig zc collect */
|
|
#define MAC_DSR_ZC_SYSTIC_TRIG_CB_ID 18
|
|
|
|
/* over stress */
|
|
#define MAC_DSR_OVER_STRESS_ID 19
|
|
|
|
/* power pm */
|
|
#define MAC_DSR_POWER_PM_ID 20
|
|
|
|
/* mac check tx abort */
|
|
#define MAC_DSR_CHECK_TX_ABORT_ID 21
|
|
|
|
/* mac check tx abort */
|
|
#define MAC_DSR_INVAILD_ADDR_ID 22
|
|
|
|
/* mac dsr updata phy timer */
|
|
#define MAC_DSR_PHY_TIMER_ID 23
|
|
|
|
/* mac hw tsfm complete */
|
|
#define MAC_DSR_HW_TSFM_COMPLETE_ID 24
|
|
|
|
/* mac rf dsr csma to tx check hwq */
|
|
#define MAC_RF_DSR_CSMA_TX_CHECK_ID 25
|
|
|
|
/* reserved for interrupt status sync up between isr and dsr.
|
|
* isr handler will mask out all rf mac interrupt in interrupt controller when
|
|
* deliver DSR events to dsr handler. dsr handler should unmask the interrupt
|
|
* controller when dsr handling is done.
|
|
*/
|
|
#define MAC_RF_DSR_ISR_SYNC_ID 30
|
|
|
|
/* reserved for interrupt status sync up between isr and dsr.
|
|
* isr handler will mask out all mac interrupt in interrupt controller when
|
|
* deliver DSR events to dsr handler. dsr handler should unmask the interrupt
|
|
* controller when dsr handling is done.
|
|
*/
|
|
#define MAC_DSR_ISR_SYNC_ID 31
|
|
|
|
/* max mac dsr id. this value should be not larger than 32 */
|
|
#define MAC_DSR_MAX_ID 32
|
|
|
|
/*
|
|
* function callback to handle specific dsr
|
|
* @arg: arg parameter registered alone with the callback
|
|
*/
|
|
typedef void (*mac_dsr_func_t)();
|
|
|
|
/* mac dsr entry defintion */
|
|
typedef struct _mac_dsr_entry {
|
|
/* mac dsr function callback */
|
|
mac_dsr_func_t dsr;
|
|
} mac_dsr_entry_t;
|
|
|
|
typedef struct _mac_dsr_table {
|
|
mac_dsr_entry_t entry[MAC_DSR_MAX_ID];
|
|
} mac_dsr_table_t;
|
|
|
|
/*
|
|
* mac_dsr_init() - mac dsr handler table init
|
|
* @table: pointer to mac dsr table
|
|
*/
|
|
void mac_dsr_init(mac_dsr_table_t *table);
|
|
|
|
/*
|
|
* mac_dsr_set() - set dsr event. this function can only be called from task
|
|
* context.
|
|
* @dsr: dsr id to be set
|
|
*/
|
|
void mac_dsr_set(uint32_t dsr);
|
|
|
|
/*
|
|
* mac_dsr_set_from_isr() - set dsr event from ISR context. this function can
|
|
* only be called from ISR context.
|
|
* @dsr: list of dsr id to be set
|
|
* @cnt: number of ids in the list
|
|
*/
|
|
void mac_dsr_set_from_isr(uint8_t *dsr, uint8_t cnt);
|
|
|
|
/*
|
|
* mac_dsr_clear() - clear dsr event. this function can only be called from MAC
|
|
* task context to clear it's own pending dsr event.
|
|
* @dsr: dsr id to be cleared
|
|
*/
|
|
void mac_dsr_clear(uint32_t dsr);
|
|
|
|
|
|
void mac_dsr_tx_comp();
|
|
|
|
void mac_dsr_rx();
|
|
|
|
void mac_dsr_rx_overflow();
|
|
|
|
void mac_dsr_set_entry(mac_dsr_table_t *table, uint8_t dsr_id, \
|
|
mac_dsr_func_t entry);
|
|
|
|
/*
|
|
* mac_dsr_set_phy_timer() - make phy timer handle to mac dsr .
|
|
*/
|
|
void mac_dsr_set_phy_timer();
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* MAC_DSR_H */
|