687 lines
23 KiB
C
687 lines
23 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "iot_config.h"
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#include "iot_errno_api.h"
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#include "iot_io.h"
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#include "hw_phy_api.h"
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#include "hw_tonemask.h"
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#include "phy_txrx_pwr.h"
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#include "phy_bb.h"
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#include "phy_cfg.h"
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#include "phy_dfe_reg.h"
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#include "hw_reg_api.h"
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#include "phy_rxtd_reg.h"
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#include "phy_tx_reg.h"
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#include "iot_system.h"
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#include "phy_ana.h"
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#include "phy_perf.h"
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#include "iot_share_task.h"
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#include "rx_mpdu_start.h"
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#include "rx_desc_reg_api.h"
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#define PHY_PWR_FD_RMS_MIN 27
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phy_tx_pwr_cfg_tbl_t phy_tx_pwr_ctl_tbl[] = {
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/*factor ana*/
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{31, 3}, // 124dB
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{30, 3}, // 123dB
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{29, 3}, // 122dB
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{28, 3}, // 121dB
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{27, 3}, // 120dB
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{26, 3}, // 119dB
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{25, 3}, // 118dB
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{24, 3}, // 117dB
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{23, 3}, // 116dB
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{22, 3}, // 115dB
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{21, 3}, // 114dB
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{20, 3}, // 113dB
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{25, 2}, // 112dB
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{24, 2}, // 111dB
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{23, 2}, // 110dB
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{22, 2}, // 109dB
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{21, 2}, // 108dB
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{20, 2}, // 107dB
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{25, 1}, // 106dB
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{24, 1}, // 105dB
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{23, 1}, // 104dB
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{22, 1}, // 103dB
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{21, 1}, // 102dB
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{20, 1}, // 101dB
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{25, 0}, // 100dB
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{24, 0}, // 99dB
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{23, 0}, // 98dB
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{22, 0}, // 97dB
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{21, 0}, // 96dB
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{20, 0}, // 95dB
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};
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/* get fd rms info depend on tonemask id */
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uint32_t phy_tone_msk_rms_get_by_valid_tone(uint16_t valid_tone_num, \
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uint8_t *fd_rms)
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{
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uint8_t band_idx = 0;
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uint32_t ret = ERR_FAIL;
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#if IOT_DTEST_ONLY_SUPPORT == 0
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if (g_phy_ctxt.indep.tx_pwr_psd_fix_db > 0) {
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if (g_phy_cpu_share_ctxt.tx_pwr_ctl_ena) {
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*fd_rms = (uint8_t)( \
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g_phy_ctxt.indep.tx_pwr_psd_fix_db - \
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PHY_PWR_DIG_ATT_MAX);
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} else {
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*fd_rms = (uint8_t)( \
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g_phy_ctxt.indep.tx_pwr_psd_fix_db);
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}
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return ERR_OK;
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}
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#endif
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for(band_idx = 0; \
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band_idx < sizeof(iot_plc_tonemask_rms_all)/sizeof(plc_tonemask_rms_table); \
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band_idx++)
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{
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if (iot_plc_tonemask_rms_all[band_idx].valid_tone_number == \
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valid_tone_num) {
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#if IOT_DTEST_ONLY_SUPPORT == 0
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if (g_phy_cpu_share_ctxt.tx_pwr_ctl_ena)
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#else
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if (0)
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#endif
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{
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*fd_rms = (uint8_t)( \
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iot_plc_tonemask_rms_all[band_idx].fd_rms_max);
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} else {
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*fd_rms = (uint8_t)( \
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iot_plc_tonemask_rms_all[band_idx].fd_rms_max - \
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g_phy_ctxt.indep.tx_pwr_reduce_db);
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}
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ret = ERR_OK;
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break;
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}
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}
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#if IOT_DTEST_ONLY_SUPPORT == 0
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if (!g_phy_cpu_share_ctxt.tx_pwr_ctl_ena) {
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*fd_rms += PHY_PWR_DIG_ATT_MAX;
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}
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#endif
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return ret;
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}
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/* kunlun1 pwr control */
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const phy_fd_td_ana_full_t phy_fd_td_ana_full_tbl[] = {
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{IOT_SUPPORT_TONE_80_490, {60, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 125}},
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{IOT_SUPPORT_TONE_100_230, {65, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 122}},
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{IOT_SUPPORT_TONE_32_120, {67, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 120}},
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{IOT_SUPPORT_TONE_72_120, {70, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 118}},
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{IOT_SUPPORT_TONE_231_490, {62, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 125}},
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{IOT_SUPPORT_TONE_240_370, {65, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 122}},
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{IOT_SUPPORT_TONE_200_1000, {57, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 130}},
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{IOT_SUPPORT_TONE_1160_1415, {62, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 125}},
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{IOT_SUPPORT_TONE_200_500, {62, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 126}},
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{IOT_SUPPORT_TONE_TIDE, {67, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 120}},
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{IOT_SUPPORT_TONE_100_230_CE,{70, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 118}},
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{IOT_SUPPORT_TONE_231_490_CE,{65, 3, 3, 0, 0}, {PHY_FULL_PWR_DBUV, 122}},
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};
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uint32_t phy_fd_td_ana_full_get(uint32_t band_id,
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const phy_fd_td_ana_full_t *tbl,
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uint16_t tbl_len,
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uint8_t *fd_pwr_int,
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uint8_t *fd_pwr_frac,
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uint8_t *td_pwr,
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uint8_t *ana_pwr)
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{
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for (int i = 0; i < tbl_len; i++) {
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if (tbl[i].band_id == band_id) {
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*fd_pwr_int = tbl[i].fd_td_ana_full.fd_pwr_int;
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if (phy_get_pwr_ctl_en()) {
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*fd_pwr_frac = tbl[i].fd_td_ana_full.fd_pwr_frac;
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} else {
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*fd_pwr_frac = tbl[i].fd_td_ana_full.fd_pwr_frac_lp;
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}
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*td_pwr = tbl[i].fd_td_ana_full.td_pwr;
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*ana_pwr = tbl[i].fd_td_ana_full.ana_pwr;
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return ERR_OK;
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}
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}
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return ERR_INVAL;
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}
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uint32_t phy_tx_pwr_to_fd_td_ana_value(
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uint32_t hw_rate_id,
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uint32_t band_id,
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uint8_t uint_dbuv,
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uint8_t *fd_pwr_int,
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uint8_t *fd_pwr_frac,
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uint8_t *td_pwr,
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uint8_t *ana_pwr)
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{
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uint32_t ret = ERR_OK;
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uint8_t rms_delta = 0;
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/* get set delta */
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rms_delta = PHY_FULL_PWR_DBUV - uint_dbuv;
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ret = phy_fd_td_ana_full_get(band_id,
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phy_fd_td_ana_full_tbl,
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IOT_ARRAY_CNT(phy_fd_td_ana_full_tbl),
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fd_pwr_int,
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fd_pwr_frac,
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td_pwr,
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ana_pwr);
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if (ret != ERR_OK) {
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iot_printf("phy fd_td_ana full power para get fail\n");
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return ret;
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}
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#if HW_PLATFORM == HW_PLATFORM_FPGA
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/* without analog PA */
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*fd_pwr_int = *fd_pwr_int - rms_delta;
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*ana_pwr = 0;
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#elif HW_PLATFORM == HW_PLATFORM_SILICON
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int8_t pwr_max;
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/* fd power reduce max */
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pwr_max = *fd_pwr_int - PHY_PWR_FD_RMS_MIN;
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if (rms_delta <= pwr_max) {
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*fd_pwr_int -= rms_delta;
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} else {
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*fd_pwr_int -= pwr_max;
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rms_delta -= pwr_max;
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/* ana power reduce max */
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pwr_max = *ana_pwr * PHY_PWR_ANA_STEP_LEN;
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if (rms_delta <= pwr_max) {
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*ana_pwr -= rms_delta / PHY_PWR_ANA_STEP_LEN;
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rms_delta -= (rms_delta / PHY_PWR_ANA_STEP_LEN)
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* PHY_PWR_ANA_STEP_LEN;
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} else {
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*ana_pwr = 0;
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rms_delta -= pwr_max;
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}
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if (rms_delta > 0) {
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/* td power reduce max */
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pwr_max = (int8_t)*td_pwr - PHY_PWR_TD_MIN;
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if (rms_delta <= pwr_max) {
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*td_pwr = (uint8_t)((int8_t)*td_pwr - (int8_t)rms_delta);
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} else {
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*td_pwr = PHY_PWR_TD_MIN;
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}
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}
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}
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#endif
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(void)hw_rate_id;
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return ret;
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}
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uint32_t phy_get_default_tx_pwr(uint32_t band_id,uint8_t *uint_dbuv,
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uint8_t *dlt_max)
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{
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uint32_t ret = ERR_INVAL;
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uint8_t full_dbuv, lp_dbuv;
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for (int i = 0; i < IOT_ARRAY_CNT(phy_fd_td_ana_full_tbl); i++) {
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if (phy_fd_td_ana_full_tbl[i].band_id == band_id) {
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full_dbuv = phy_fd_td_ana_full_tbl[i].psd_full.full_dbuv;
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if (!phy_get_pwr_ctl_en()) {
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lp_dbuv = phy_fd_td_ana_full_tbl[i].psd_full.lp_dbuv;
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*dlt_max = full_dbuv - lp_dbuv;
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*uint_dbuv = lp_dbuv;
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ret = ERR_OK;
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} else {
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*dlt_max = 0;
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*uint_dbuv = full_dbuv;
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ret = ERR_OK;
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break;
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}
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}
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}
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return ret;
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}
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void phy_set_sack_tx_power(uint32_t pwr_db)
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{
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(void)pwr_db;
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}
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void phy_high_perf_set(bool_t en)
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{
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#if IOT_DTEST_ONLY_SUPPORT == 0
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uint32_t tmp = 0;
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bool_t en_int = false;
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/* protect, force en_int to avoid high level call this function by mistake */
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#if (PHY_CHIP_CERT_EN == 1)
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en_int = true;
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#else
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en_int = en;
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#endif
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/* Product test Mode disable high performance setting */
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if ((1 == g_phy_cpu_share_ctxt.pt_mode_entry) || \
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(MP_MODE == phy_get_fw_mode())) {
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en_int = false;
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}
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if (en_int) {
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/* fix gain enable,
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* disable power satuation and hw adjust gain req
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*/
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phy_set_fix_gain_sat_adj_dis(1, 0, -24, 0, 1, 1);
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/* bypass dc blocker */
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tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR);
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REG_FIELD_SET(SW_DC_BLK_BYPASS, tmp, 1);
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PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR, tmp);
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/* use 192 point agc */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
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REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,0);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
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/* let cpu1 know */
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g_phy_cpu_share_ctxt.high_perf_en = 1;
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g_phy_cpu_share_ctxt.shift_low = 1;
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g_phy_cpu_share_ctxt.shift_high = 2;
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/* re-enable cpu1 to protect */
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PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0x5A5A5A5A);
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} else {
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/* not fix gain,
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* enable power satuation and hw adjust gain req
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*/
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phy_set_fix_gain_sat_adj_dis(0, 60, -24, 0, 0, 0);
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/* use 1536 point agc */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
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REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
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/* let cpu1 know */
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g_phy_cpu_share_ctxt.high_perf_en = 0;
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g_phy_cpu_share_ctxt.shift_low = 0;
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g_phy_cpu_share_ctxt.shift_high = 0;
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}
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iot_printf("[PHY] high_perf_en is %d, agc_level:0x%x\n",
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en_int, PHY_RXTD_READ_REG(CFG_BB_AGC_GAIN_LEVEL_ADDR));
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#else
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(void)en;
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#endif
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}
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uint32_t phy_pwr_psd_ctl_update(uint8_t uint_dbuv)
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{
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uint32_t ret = ERR_OK;
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#if IOT_DTEST_ONLY_SUPPORT == 0
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uint8_t para_int = 0, para_frac = 0;
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uint8_t fix_db_backup = 0;
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if (PHY_FULL_PWR_DBUV == uint_dbuv) {
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/* switch to default psd mode */
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para_int = (uint8_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db);
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phy_tx_rms_set(0, HW_FULL_BAND, para_int, para_frac);
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phy_tx_rms_set(0, HW_LOW_BAND, para_int, para_frac);
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phy_tx_rms_set(0, HW_HIGH_BAND, para_int, para_frac);
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phy_tx_rms_set(1, HW_FULL_BAND, para_int, para_frac);
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phy_tx_rms_set(1, HW_LOW_BAND, para_int, para_frac);
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phy_tx_rms_set(1, HW_HIGH_BAND, para_int, para_frac);
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/* td/ana set to default */
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phy_tx_gain_factor_set(0);
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phy_ana_pga_gain_set(3);
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} else {
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/* clear psd flag*/
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fix_db_backup = (uint8_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db);
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g_phy_ctxt.indep.tx_pwr_psd_fix_db = 0;
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if (uint_dbuv > PHY_PWR_ADJ_MAX) {
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int8_t delta = uint_dbuv;
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uint8_t fix_pga;
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if (delta <= PHY_PWR_DIG_ATT_MAX) {
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phy_tx_gain_factor_set((uint8_t)(
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((SW_TX_PWR_SCALE_FACTOR_MASK
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>> SW_TX_PWR_SCALE_FACTOR_OFFSET) + 1 - delta)));
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delta = 0;
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} else {
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phy_tx_gain_factor_set((uint8_t)(
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((SW_TX_PWR_SCALE_FACTOR_MASK
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>> SW_TX_PWR_SCALE_FACTOR_OFFSET) + 1
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- PHY_PWR_DIG_ATT_MAX)));
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delta -= PHY_PWR_DIG_ATT_MAX;
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}
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if (delta > 0) {
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if (delta <= PHY_PWR_ANA_MAX) {
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fix_pga = PHY_PWR_ANA_STEP_NUM
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- (delta / PHY_PWR_ANA_STEP_LEN);
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delta -= fix_pga * PHY_PWR_ANA_STEP_LEN;
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} else {
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fix_pga = 0;
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delta -= PHY_PWR_ANA_MAX;
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}
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phy_ana_pga_gain_set(fix_pga);
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}
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g_phy_ctxt.indep.tx_pwr_reduce_db = delta;
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} else {
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/* alloc reduce db to glb value */
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g_phy_ctxt.indep.tx_pwr_reduce_db = uint_dbuv;
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/* td/ana set to default */
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phy_tx_gain_factor_set(0);
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phy_ana_pga_gain_set(3);
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}
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/* update fd rms */
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phy_fd_rms_update();
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/* backup after get valid rms */
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g_phy_ctxt.indep.tx_pwr_psd_fix_db = fix_db_backup;
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}
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#endif
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return ret;
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}
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uint32_t phy_swagc_set(bool_t en)
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{
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if (en) {
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/* enable sw-agc */
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phy_high_perf_set(true);
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} else {
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/* clear shift en */
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PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0);
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/* dly a cycle */
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phy_rx_nf_by_rxtd_get(14);
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/* clear shift */
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phy_gain_shift_set(0,0,0,0);
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/* hw-agc init */
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phy_high_perf_set(false);
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}
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return ERR_OK;
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}
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void phy_tx_resp_pwr_ctl_en(
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uint8_t fd_int_en, uint8_t fd_frac_en, uint8_t td_en, uint8_t ana_en)
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{
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(void)fd_int_en;
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(void)fd_frac_en;
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(void)td_en;
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(void)ana_en;
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}
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void phy_set_tx_resp_pwr(
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uint8_t fd_int, uint8_t fd_frac, uint8_t td, uint8_t ana)
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{
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(void)fd_int;
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(void)fd_frac;
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(void)td;
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(void)ana;
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}
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uint32_t phy_info_check_entry(void *mpdu_st, \
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void *fc, uint32_t role, uint8_t mt_mode_sel)
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{
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uint32_t ret = ERR_OK;
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uint32_t tmp = 0;
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rx_mpdu_start *mpdu_ptr = (rx_mpdu_start *)mpdu_st;
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iot_phy_info_t *ptr = &mpdu_ptr->phy;
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(void)role;
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/* check beacon pkt */
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frame_control_t *sg_fc = (frame_control_t *)fc;
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if(sg_fc->delimiter_type == 0) {
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if(g_phy_ctxt.indep.work_mode == PHY_MODE_TEST && \
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(mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_T || \
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mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_LP)) {
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/* TODO: replace by dynamic spur check */
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if (mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_LP) {
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/* diabale sw-agc */
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PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0);
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/* dly a cycle */
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phy_rx_nf_by_rxtd_get(14);
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/* clear shift */
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phy_gain_shift_set(0,0,0,0);
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/* clr spur or pulse setting */
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phy_anti_spur_set_clr();
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phy_anti_pulse_set_clr();
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/* off check spur on loopback mode */
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//phy_channel_est_request();
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/* use 1536 point agc */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
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REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
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/* shandong cert test. band0 extmi 1 can not pass.
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* In the high frequency part, the energy is relatively low.
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* so for the TMI(EXTMI 1) copycnt < 2, increase power.
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*/
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if (phy_band_id_get() == IOT_SUPPORT_TONE_80_490) {
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phy_set_soft_shift0(15);
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}
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iot_printf("[BB] disable sw-agc for loopback!\n");
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} else if (mt_mode_sel == CERT_TEST_CMD_ENTER_PHY_T) {
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if (phy_band_id_get() == IOT_SUPPORT_TONE_100_230) {
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if (phy_cert_is_hw_agc()) {
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/* mask 2M spur by notch filter */
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phy_anf_option_set(PHY_ANF_MODE_FIX, 1, 1, 0x81ca);
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} else {
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/* mask 6M spur by notch filter */
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phy_anf_option_set(PHY_ANF_MODE_FIX, 1, 1, 0x8fd5);
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}
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/* mask 3M spur by spur mask, [-7,7] */
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phy_spur_mask_set(123, 15);
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/* mask 1M spur by notch filter */
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phy_anf_option_set(PHY_ANF_MODE_FIX, 1, 2, 0x8073);
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} else if (phy_band_id_get() == IOT_SUPPORT_TONE_32_120) {
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/* mask 2M spur by spur mask, [-7,7] */
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/* NOTE: mendong cert test.
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* do not mask tone.
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*/
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if (!(phy_cert_is_hw_agc())) {
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phy_spur_mask_set(82, 15);
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}
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}
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if (phy_cert_is_hw_agc()) {
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/* NOTE: mendong cert test,
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* low rssi need use swagc.
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* but other place(like gansu) cert test,
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* low rssi need use hwagc.
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*/
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/* use rssi judge whether use swagc or not */
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uint32_t rssi_t = PHY_RSSI_FROM_RMI_GAIN(ptr->adc_power, \
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ptr->agc_tbl_entry);
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if (rssi_t < 45) {
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phy_swagc_set(true);
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phy_rxfd_pkt_det_thd_set(32, 32);
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iot_printf("[BB] rssi <= 45 for tt!\n");
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}
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} else {
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/* if adc <= 53 hw-agc */
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if (ptr->adc_power <= 114) {
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/* diabale sw-agc */
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PHY_RXTD_WRITE_REG(CFG_BB_RXTD_SPARE2_ADDR, 0);
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/* dly a cycle */
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phy_rx_nf_by_rxtd_get(14);
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/* clear shift */
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phy_gain_shift_set(0,0,0,0);
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/* clr spur or pulse setting */
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phy_anti_spur_set_clr();
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phy_anti_pulse_set_clr();
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/* use 1536 point agc */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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REG_FIELD_SET(SW_AGC_ACC_STEP_LS,tmp,4);
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REG_FIELD_SET(SW_AGC_ACC_STEP_HS,tmp,3);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_ACC_STEP_ADDR,tmp);
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iot_printf("[BB] hwagc if rssi <= 53 for tt!\n");
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}
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}
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phy_channel_est_request();
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}
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}
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/* TODO: check phy channel info */
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}
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tmp = PHY_TX_READ_REG(CFG_BB_DB_AMP_CTRL_RATE0_BAND0_ADDR);
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#if PHY_DBG_EN
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iot_printf("[BB] spare2:%x-%x-%x, psd:%d\n", \
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PHY_RXTD_READ_REG(CFG_BB_RXTD_SPARE2_ADDR), \
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PHY_RXTD_READ_REG(CFG_BB_RXTD_SPARE1_ADDR), \
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PHY_RXTD_READ_REG(CFG_BB_RXTD_SPARE3_ADDR), \
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REG_FIELD_GET(SW_RATE0_BAND0_DB_UP_AMP_PARA_INT,tmp));
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tmp = PHY_DFE_READ_REG(CFG_BB_SW_ADJUST_GAIN_ADDR);
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iot_printf("[BB] rx shift:%d-%d\n", \
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REG_FIELD_GET(SW_RX_GAIN_LEFT_SHIFT, tmp),
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REG_FIELD_GET(SW_RX_GAIN_SHIFT_BITS, tmp));
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#endif
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return ret;
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}
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void phy_check_spur_cert_handle(uint16_t notch_alpha)
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{
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(void)notch_alpha;
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}
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uint32_t phy_work_mode_set(phy_work_mode_id mode)
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{
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uint32_t ret = ERR_OK;
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uint32_t mask_id = phy_mask_id_get();
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uint32_t mac_proto = PHY_PROTO_TYPE_GET();
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if(mode < PHY_MODE_END) {
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g_phy_ctxt.indep.work_mode = mode;
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if(g_phy_ctxt.indep.work_mode == PHY_MODE_TEST) {
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/* modify tx power */
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if(g_phy_ctxt.indep.tx_pwr_psd_fix_db > 0) {
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phy_tx_rms_set(0, HW_FULL_BAND, \
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(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
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phy_tx_rms_set(0, HW_LOW_BAND, \
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(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
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phy_tx_rms_set(0, HW_HIGH_BAND, \
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(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
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phy_tx_rms_set(1, HW_FULL_BAND, \
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(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
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phy_tx_rms_set(1, HW_LOW_BAND, \
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(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
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phy_tx_rms_set(1, HW_HIGH_BAND, \
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(uint16_t)(g_phy_ctxt.indep.tx_pwr_psd_fix_db), 0);
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} else {
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phy_tx_rms_set(0, HW_FULL_BAND, PHY_CERT_DST_RMS, 0);
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phy_tx_rms_set(0, HW_LOW_BAND, PHY_CERT_DST_RMS, 0);
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phy_tx_rms_set(0, HW_HIGH_BAND, PHY_CERT_DST_RMS, 0);
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phy_tx_rms_set(1, HW_FULL_BAND, PHY_CERT_DST_RMS, 0);
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phy_tx_rms_set(1, HW_LOW_BAND, PHY_CERT_DST_RMS, 0);
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phy_tx_rms_set(1, HW_HIGH_BAND, PHY_CERT_DST_RMS, 0);
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}
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/* if box4 or box5, rise the power */
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if (1 == g_phy_ctxt.indep.chn.is_pwr_rise) {
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phy_pwr_adjust_set(PHY_FULL_PWR_DBUV);
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}
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/* del time domain shift */
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phy_tx_gain_factor_set(0);
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/* init tonemask */
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phy_tone_mask_amp_phase_tab_load( \
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&all_mask_amp_phase_table, mask_id, mac_proto);
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/* del shift in cert mode */
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g_phy_cpu_share_ctxt.shift_low = 0;
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g_phy_cpu_share_ctxt.shift_high = 0;
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/* reduce wraning */
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if (phy_band_id_get() == IOT_SUPPORT_TONE_32_120 || \
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phy_band_id_get() == IOT_SUPPORT_TONE_72_120) {
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phy_rxfd_pkt_det_thd_set(32, 48);
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phy_rxfd_frame_sync_set(32);
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} else if (phy_band_id_get() == IOT_SUPPORT_TONE_100_230) {
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if (1 == g_phy_ctxt.indep.chn.is_pwr_rise) {
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phy_rxfd_pkt_det_thd_set(16, 32);
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} else {
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phy_rxfd_pkt_det_thd_set(32, 32);
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}
|
|
}
|
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|
|
iot_printf("[BB] enter cert mode!\n");
|
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}
|
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} else {
|
|
ret = ERR_FAIL;
|
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}
|
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|
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return ret;
|
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}
|
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|
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void phy_overstress_power_down(uint32_t dowm_db)
|
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{
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
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uint32_t tx_power = phy_get_tx_pwr_limit(phy_proto_single_band_id_get());
|
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if (tx_power > dowm_db) {
|
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tx_power -= dowm_db;
|
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}
|
|
g_phy_ctxt.indep.ovs_ctxt.ovr_pwr = max(tx_power, MIN_TX_POWER);
|
|
phy_set_tx_pwr_limit(tx_power);
|
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#else
|
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(void)dowm_db;
|
|
#endif
|
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}
|
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|
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void phy_overstress_power_up()
|
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{
|
|
#if HW_PLATFORM >= HW_PLATFORM_FPGA
|
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/* ignore overstress power and set sw_set_power */
|
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phy_set_tx_pwr_limit(g_phy_ctxt.dep.sw_set_pwr);
|
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#endif
|
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}
|
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|
|
uint32_t phy_set_common_pwr_reg(uint32_t pwr_db)
|
|
{
|
|
uint8_t fd_pwr_int, fd_pwr_frac, td_pwr, ana_pwr;
|
|
uint32_t single_proto_band = phy_proto_single_band_id_get();
|
|
phy_tx_pwr_to_fd_td_ana_value(0,
|
|
single_proto_band,
|
|
(uint8_t)pwr_db,
|
|
&fd_pwr_int,
|
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&fd_pwr_frac,
|
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&td_pwr,
|
|
&ana_pwr);
|
|
/* set td and ana power to register */
|
|
|
|
/* rate0 band0/1/2 */
|
|
phy_tx_rms_set(0, HW_FULL_BAND, fd_pwr_int, fd_pwr_frac);
|
|
phy_tx_rms_set(0, HW_LOW_BAND, fd_pwr_int, fd_pwr_frac);
|
|
phy_tx_rms_set(0, HW_HIGH_BAND, fd_pwr_int, fd_pwr_frac);
|
|
|
|
/* rate1 band0/1/2 */
|
|
phy_tx_rms_set(1, HW_FULL_BAND, fd_pwr_int, fd_pwr_frac);
|
|
phy_tx_rms_set(1, HW_LOW_BAND, fd_pwr_int, fd_pwr_frac);
|
|
phy_tx_rms_set(1, HW_HIGH_BAND, fd_pwr_int, fd_pwr_frac);
|
|
|
|
/* td power */
|
|
phy_tx_gain_factor_set(td_pwr);
|
|
|
|
/* tx pga config */
|
|
phy_ana_pga_gain_set(ana_pwr);
|
|
|
|
iot_printf("[ptr_dbg] set pwr_reg power:%d, td_pwr:%d, ana_pwr:%d, "
|
|
"fd_frac:%d, fd_int:%d\n",
|
|
pwr_db, td_pwr, ana_pwr, fd_pwr_frac, fd_pwr_int);
|
|
return 0;
|
|
}
|
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|