Files
kunlun/plc/halphy/hw/phy_reset.c
2024-09-28 14:24:04 +08:00

73 lines
2.2 KiB
C
Executable File

/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#include "hw_reg_api.h"
#include "phy_dfe_reg.h"
#include "phy_ana.h"
#include "phy_bb.h"
#include "ahb.h"
/*
* when phy reset, must close PA in order
* to prevent generate step signal
*/
void phy_reset_pre_protect()
{
uint32_t tmp;
phy_ana_enlic_en(false);
/* close PA, make HW can't control analog */
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_CFG_ADDR);
REG_FIELD_SET(SW_TX_START_CFG_DATA, tmp, 0x0);
PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, tmp);
}
/*
* in order to prevent Resets the unsigned DAC input to 0
* 1 force tx,open dac's clk
* 2 set dac'reg to 512
* 3 Restore the previous configuration
*/
void phy_reset_post_protect()
{
uint32_t tmp;
/* force phy in tx state */
phy_txrx_ovr_set(true, 2);
phy_ana_enlic_en(false);
/* en analog tx */
phy_ana_tx_set(true, true);
phy_ana_rx_set(false, false);
/* overwrite DAC = unsigned 512 = signed 0 */
phy_dac_data_ovr_set(true, 512);
phy_dac_data_ovr_set(false, 512);
/* disable force idle */
phy_txrx_ovr_set(false, 0);
/*
* make hardware can't control Analog
* top_en_tx: 1
* top_enlic:10
* top_en_dac: 1
*/
tmp = PHY_DFE_READ_REG(CFG_BB_ANA_TX_START_CFG_ADDR);
REG_FIELD_SET(SW_TX_START_CFG_DATA, tmp, 0x20202);
PHY_DFE_WRITE_REG(CFG_BB_ANA_TX_START_CFG_ADDR, tmp);
}