397 lines
9.9 KiB
C
Executable File
397 lines
9.9 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "mac_sys_reg.h"
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#include "phy_reg.h"
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#include "hw_reg_api.h"
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#include "phy_tx_reg.h"
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#include "phy_bb.h"
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#include "phy_rx_fd_reg.h"
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#include "phy_rxtd_reg.h"
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#include "phy_mix.h"
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#include "phy_tmap.h"
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void phy_tx_dly_gp_set(uint16_t dly)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_TX_READ_REG(CFG_BB_TX_DLY_ADDR);
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REG_FIELD_SET(SW_TX_DLY_GP, tmp, dly);
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PHY_TX_WRITE_REG(CFG_BB_TX_DLY_ADDR, tmp);
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#else
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(void)dly;
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#endif
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}
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void phy_tx_long_pream_enable()
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{
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uint32_t tmp = 0;
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/* enable phy tx long preamble */
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tmp = RGF_MAC_READ_REG(CFG_PHY_CTRL_ADDR);
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REG_FIELD_SET(CFG_PHY_TX_LONG_PREAM_EN, tmp, 1);
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RGF_MAC_WRITE_REG(CFG_PHY_CTRL_ADDR,tmp);
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/* matching SG num of preambles to be sent */
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tmp = PHY_READ_REG(CFG_BB_PRE_CFG_ADDR);
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REG_FIELD_SET(SW_TX_PRE_NUM,tmp,13);
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PHY_WRITE_REG(CFG_BB_PRE_CFG_ADDR, tmp);
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#if PLC_SUPPORT_CCO_ROLE
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tmp = PHY_TX_READ_REG(CFG_BB_TX_DLY_ADDR);
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REG_FIELD_SET(SW_TX_DLY_SG, tmp, 4095);
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REG_FIELD_SET(SW_TX_DLY_GP, tmp, 4095);
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PHY_TX_WRITE_REG(CFG_BB_TX_DLY_ADDR, tmp);
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#else
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tmp = PHY_TX_READ_REG(CFG_BB_TX_DLY_ADDR);
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REG_FIELD_SET(SW_TX_DLY_SG, tmp, 4095);
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REG_FIELD_SET(SW_TX_DLY_GP, tmp, 4095);
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PHY_TX_WRITE_REG(CFG_BB_TX_DLY_ADDR, tmp);
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#endif
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}
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void phy_pb_robo_set(bool_t nsg_en, bool_t mn_invert)
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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uint32_t tmp = 0;
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tmp = PHY_READ_REG(CFG_BB_PB_ROBO_ADDR);
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REG_FIELD_SET(SW_IS_NSG_PB_ROBO, tmp, nsg_en);
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REG_FIELD_SET(SW_MN_INVERT, tmp, mn_invert);
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PHY_WRITE_REG(CFG_BB_PB_ROBO_ADDR, tmp);
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#else
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(void)nsg_en;
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(void)mn_invert;
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#endif
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}
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void phy_td_robo_mode_set(bool_t en, uint8_t robo_mod)
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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uint32_t tmp = 0;
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tmp = PHY_READ_REG(CFG_BB_TD_ROBO_ADDR);
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REG_FIELD_SET(SW_TD_ROBO_MODE, tmp, robo_mod);
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REG_FIELD_SET(SW_TD_ROBO_EN, tmp, en);
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PHY_WRITE_REG(CFG_BB_TD_ROBO_ADDR, tmp);
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#else
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(void)en;
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(void)robo_mod;
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#endif
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}
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void phy_tx_pre_num_set(uint16_t pre_num)
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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uint32_t tmp = 0;
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tmp = PHY_READ_REG(CFG_BB_PRE_CFG_ADDR);
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REG_FIELD_SET(SW_TX_PRE_NUM, tmp, pre_num);
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PHY_WRITE_REG(CFG_BB_PRE_CFG_ADDR, tmp);
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#else
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(void)pre_num;
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#endif
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}
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void phy_2syncm_en(bool_t en)
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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uint32_t tmp = 0;
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tmp = PHY_RX_FD_READ_REG(CFG_BB_FRAME_SYNC_ADDR);
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REG_FIELD_SET(SW_2SYNCM_EN, tmp, en);
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PHY_RX_FD_WRITE_REG(CFG_BB_FRAME_SYNC_ADDR, tmp);
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#else
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(void)en;
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#endif
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}
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void phy_sync_symb_acc_en(bool_t en)
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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uint32_t tmp = 0;
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tmp = PHY_RX_FD_READ_REG(CFG_BB_FRAME_SYNC_ADDR);
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REG_FIELD_SET(SW_SYNC_SYMB_ACC_EN, tmp, en);
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PHY_RX_FD_WRITE_REG(CFG_BB_FRAME_SYNC_ADDR, tmp);
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#else
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(void)en;
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#endif
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}
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void phy_skip_for_td_robo_set(uint32_t skip)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_RXTD_READ_REG(CFG_BB_SKIP_FOR_TD_ROBO_ADDR);
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REG_FIELD_SET( \
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SW_EXT_SKIP_FOR_TD_TOBO, tmp, skip);
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PHY_RXTD_WRITE_REG(CFG_BB_SKIP_FOR_TD_ROBO_ADDR, tmp);
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#else
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(void)skip;
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#endif
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}
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void phy_neg_pream_ctrl_set(uint16_t symb_num)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_READ_REG(CFG_BB_NEG_PREAM_CTRL_ADDR);
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REG_FIELD_SET( \
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SW_NEG_PREAM_SYMB_NUM, tmp, symb_num);
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PHY_WRITE_REG(CFG_BB_NEG_PREAM_CTRL_ADDR, tmp);
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#else
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(void)symb_num;
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#endif
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}
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void phy_av_high_speed_gi_x_set(uint8_t gi_x)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_READ_REG(CFG_BB_PLD_CFG_ADDR);
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REG_FIELD_SET(SW_AV_HIGH_SPEED_GI_X, tmp, gi_x);
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PHY_WRITE_REG(CFG_BB_PLD_CFG_ADDR, tmp);
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#else
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(void)gi_x;
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#endif
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}
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void phy_av_high_speed_code_rate_set(uint8_t rate)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_READ_REG(CFG_BB_PLD_CFG_ADDR);
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REG_FIELD_SET(SW_AV_HIGH_SPEED_CODE_RATE, tmp, rate);
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PHY_WRITE_REG(CFG_BB_PLD_CFG_ADDR, tmp);
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#else
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(void)rate;
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#endif
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}
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void phy_rxfd_mc_en(bool_t en)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_RX_FD_READ_REG(CFG_BB_MC_PER_SUBC_ADDR);
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REG_FIELD_SET(SW_MC_PER_SUBC_EN, tmp, en);
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PHY_RX_FD_WRITE_REG(CFG_BB_MC_PER_SUBC_ADDR, tmp);
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#else
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(void)en;
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#endif
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}
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void phy_tx_prs_pre_num_cal(uint8_t robo_mod)
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{
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uint16_t sw_tx_pream_num = 0;
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uint16_t neg_pream_num = 0;
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uint16_t pos_pream_num = 0;
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uint32_t proto_id = PHY_PROTO_TYPE_GET();
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if(proto_id == PLC_PROTO_TYPE_GP) {
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sw_tx_pream_num = PHY_SPEC_TX_PREAM_NUM_GP;
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} else if(proto_id == PLC_PROTO_TYPE_SPG) {
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sw_tx_pream_num = PHY_SPEC_TX_PREAM_NUM_SPG;
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} else if(proto_id == PLC_PROTO_TYPE_SG) {
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sw_tx_pream_num = PHY_SPEC_TX_PREAM_NUM_SG;
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}
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/* cal neg preamble number */
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neg_pream_num = \
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((2 << (robo_mod - 1)) << 1) + \
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((2 << (robo_mod - 1)) >> 1) + 1;
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/* config neg preamble number */
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phy_neg_pream_ctrl_set(neg_pream_num);
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/* cal pos preamble number */
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pos_pream_num = \
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sw_tx_pream_num * (2 << (robo_mod - 1));
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/* cal total preamble number*/
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sw_tx_pream_num = neg_pream_num + pos_pream_num;
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/* config total preamble number */
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phy_tx_pre_num_set(sw_tx_pream_num);
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phy_sg_bmcs_pream_num_set( \
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sw_tx_pream_num, sw_tx_pream_num, sw_tx_pream_num);
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phy_sg_emcs_pream_num_set( \
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sw_tx_pream_num, sw_tx_pream_num, sw_tx_pream_num);
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}
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void phy_gp_fc101_set(bool_t always_en, uint8_t thr, bool_t en)
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{
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#if HW_PLATFORM != HW_PLATFORM_SIMU
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uint32_t tmp = 0;
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tmp = PHY_RX_FD_READ_REG(CFG_BB_FC101_ADDR);
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REG_FIELD_SET(SW_ALWAYS_FC101_EN, tmp, always_en);
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REG_FIELD_SET(SW_FC101_THR, tmp, thr);
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REG_FIELD_SET(SW_FC101_EN, tmp, en);
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PHY_RX_FD_WRITE_REG(CFG_BB_FC101_ADDR, tmp);
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#else
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(void)always_en;
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(void)thr;
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(void)en;
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#endif
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}
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void phy_gp_skip_for_fc101_set(uint16_t skip)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_RXTD_READ_REG(CFG_BB_RX_TD_CTRL_DLY_ADDR);
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REG_FIELD_SET( \
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SW_SKIP_FOR_FC101, tmp, skip);
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PHY_RXTD_WRITE_REG(CFG_BB_RX_TD_CTRL_DLY_ADDR, tmp);
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#else
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(void)skip;
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#endif
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}
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void phy_gp_tune_skip_for_fc101_set(uint16_t skip)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_RXTD_READ_REG(CFG_BB_OFFSET_FROM_CORR_ADDR);
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REG_FIELD_SET( \
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SW_TUNE_SKIP_FOR_FC, tmp, skip);
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PHY_RXTD_WRITE_REG(CFG_BB_OFFSET_FROM_CORR_ADDR, tmp);
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#else
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(void)skip;
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#endif
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}
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void phy_skip_for_burst_set(uint32_t skip)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_RXTD_READ_REG(CFG_BB_SKIP_FOR_BST_ADDR);
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REG_FIELD_SET(SW_SKIP_FOR_BST, tmp, skip);
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PHY_RXTD_WRITE_REG(CFG_BB_SKIP_FOR_BST_ADDR, tmp);
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#else
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(void)skip;
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#endif
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}
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void phy_rxfd_burst_stop_time_set(uint32_t time)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_RX_FD_READ_REG(CFG_BB_TURBO_STOP_BST_ADDR);
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REG_FIELD_SET(SW_TURBO_STOP_TIME_BST, tmp, time);
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PHY_RX_FD_WRITE_REG(CFG_BB_TURBO_STOP_BST_ADDR, tmp);
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#else
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(void)time;
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#endif
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}
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void phy_rxtd_bifs_time_set(uint32_t time)
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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tmp = PHY_RXTD_READ_REG(CFG_BB_BIFS_TIME_ADDR);
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REG_FIELD_SET(SW_BIFS_TIME, tmp, time);
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PHY_RXTD_WRITE_REG(CFG_BB_BIFS_TIME_ADDR, tmp);
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#else
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(void)time;
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#endif
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}
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void phy_td_robo_ext_init(uint8_t robo_mod)
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{
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/* check mod */
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if(!robo_mod) {
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/* not use td robo */
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return;
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}
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/* pb robo */
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phy_pb_robo_set(false, true);
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/* robo mode */
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phy_td_robo_mode_set(true, robo_mod);
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/* cal tx pre num */
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phy_tx_prs_pre_num_cal(robo_mod);
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/* update pkt det time out */
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phy_pkt_time_out_set(35000 * (2 << (robo_mod - 1)));
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phy_pkt_time_out_384_set(4000 * (2 << (robo_mod - 1)));
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phy_find_minus_time_out_384_set(4000 * (2 << (robo_mod - 1)));
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phy_find_minus_time_out_3k_set(50000 * (2 << (robo_mod - 1)));
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phy_skip_for_td_robo_set(3072 * ((2 << (robo_mod - 1)) - 1));
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/* rxfd */
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phy_2syncm_en(false);
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phy_sync_symb_acc_en(true);
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}
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void phy_spcl_feat_init()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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/* enable phy tx long preamble */
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#if IOT_TX_LONG_PREAMBLE_ENABLE
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phy_tx_long_pream_enable();
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#endif
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/* td robo for reduce power */
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phy_td_robo_ext_init(PHY_TD_ROBO_EXT_MODE_LVL);
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#endif
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}
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void phy_gp_hybrid_mode_init()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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/* global config for all pkt */
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phy_gp_fc101_set(true, 63, true);
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/* neg preamble symb num */
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phy_neg_pream_ctrl_set(2);
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/* skip */
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phy_gp_skip_for_fc101_set(2508);
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phy_gp_tune_skip_for_fc101_set(186);
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#endif
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}
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void phy_gp_burst_init()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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phy_mix_flag_set(false);
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phy_rxfd_rate_offset_set(0);
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phy_av_high_speed_gi_x_set(0);
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/* enable only for tmap */
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phy_rxfd_mc_en(false);
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phy_av_high_speed_code_rate_set(PHY_TURBO_RATE_16_21);
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phy_skip_for_burst_set(1374/2+384*3+192);
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phy_tx_dly_gp_set(487);
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phy_rxfd_burst_stop_time_set(4500);
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phy_rxtd_bifs_time_set(1820);
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#endif
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}
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