315 lines
7.6 KiB
C
Executable File
315 lines
7.6 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#ifndef PHY_ANA_H
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#define PHY_ANA_H
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#include "plc_fr.h"
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#include "os_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PHY_ANA_HW_EN (0xFFFFFFFF)
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#define MAC_RX_BUF_SIZE (32*1024-1)
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#define MAC_RX_SAMPLE_SIZE (31*1024)
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typedef enum
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{
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DA_B_PATH_PHY = 0x00U,
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DA_B_PATH_TONE = 0x01U,
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}DA_B_PATH_CFG;
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typedef enum
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{
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ADC_MODE_FORCE = 0x00U,
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ADC_MODE_AUTO = 0x01U,
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}ADC_MODE_CFG;
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typedef enum {
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PHY_ENLIC_TXRX_IDLE,
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PHY_ENLIC_TXRX_RX,
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PHY_ENLIC_TXRX_TX,
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PHY_ENLIC_TXRX_LP
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} PHY_ENLIC_TXRX_ID;
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/* tx para */
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typedef struct
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{
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uint32_t buf_size;
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DA_B_PATH_CFG path;
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bool_t inv_en;
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bool_t tone_mode_en;
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uint32_t tone_num;
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}DaTxPara_t;
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/* rx para */
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typedef struct
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{
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/***/
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uint32_t buf_size;
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uint32_t sample_size;
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ADC_MODE_CFG mode;
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uint32_t thrd;
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bool_t clk_inv_en;
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bool_t dmsb_inv_en;
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}DaRxPara_t;
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void phy_ada_enable(uint32_t enable);
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void phy_ada_clk_ratio_cfg(uint8_t data);
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void phy_ada_tx_cfg(DaTxPara_t *tp);
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void phy_ada_rx_cfg(DaRxPara_t *rp);
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void phy_adc_en_cfg(uint32_t enable);
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void phy_dac_en_cfg(uint32_t enable);
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bool_t phy_adc_is_sample_done();
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void phy_adc_thrd_cfg(uint32_t thrd);
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void phy_adc_trig_en_cfg(uint32_t enable);
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void warm_rst_ada();
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uint32_t phy_adc_trig_addr_get();
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uint32_t phy_ada_get_power_on();
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void phy_adc_mode_cfg(ADC_MODE_CFG mode);
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void phy_ana_top_reset_n_set(bool_t en);
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/**
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*@brief enable_ada
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*
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* enable ada clock.
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*
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*@param enable [clock enable/disable]
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*@exception [none.]
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*@return [none.]
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*/
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void enable_ada(uint32_t enable);
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/**
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*@brief phy_ana_init.
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*
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* initialize granite and geode depend on band id.
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*
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*@param band_id [band index.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_init(uint32_t band_id);
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/**
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*@brief phy_ana_tx_set.
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*
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* enable or disable analog TX and DAC.
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*
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*@param tx_en [analog TX enable.]
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*@param dac_en [analog DAC enable.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_tx_set(bool_t tx_en, bool_t dac_en);
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/**
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*@brief phy_ana_rx_set.
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*
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* enable or disable analog RX and ADC.
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*
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*@param rx_en [analog RX enable.]
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*@param adc_en [analog ADC enable.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_rx_set(bool_t rx_en, bool_t adc_en);
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/**
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*@brief phy_ana_sadc_enable.
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*
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* enable or disable sadc.
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*
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*@param enable [analog RX enable.]
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*@return [none.]
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*/
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void phy_ana_sadc_enable(bool_t enable);
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/**
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*@brief phy_ana_dfe_init.
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*
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* initialize bias switch auto for low power.
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*
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*@param none [none.]
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*@return [none.]
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*/
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void phy_ana_dfe_init(void);
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/**
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*@brief phy_ana_i2c_write.
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*
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* analog write interface.
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*
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*@param reg_id [register index from 0 to 10.]
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*@param wdata [the data will be written.]
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*@param mask [mask for the data.]
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*@return [none.]
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*/
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void phy_ana_i2c_write(uint32_t reg_id, uint32_t wdata, uint32_t mask);
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/**
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*@brief phy_ana_i2c_read.
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*
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* read the value from analog register.
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*
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*@param reg_id [register index from 0 to 10.]
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*@param rdata [the data read from analog with the reg_id.]
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*@param rodata [extend status value.]
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*@return [none.]
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*/
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void phy_ana_i2c_read(uint32_t reg_id, uint32_t *rdata, uint8_t *rodata);
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/**
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*@brief phy_ana_pga_gain_set.
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*
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* set the gpa gain value to analog register.
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*
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*@param val [0-3.]
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*@return [none.]
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*/
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void phy_ana_pga_gain_set(uint32_t val);
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/**
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*@brief phy_ana_pga_gain_get.
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*
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* get the gpa gain value
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*
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*@return [0-3.]
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*/
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uint32_t phy_ana_pga_gain_get(void);
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/**
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*@brief phy_ana_tx_en.
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*
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* enable analog tx.
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*
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*@param en [true for enable and false for disable.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_tx_en(bool_t en);
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/**
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*@brief phy_ana_rx_en.
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*
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* enable analog rx.
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*
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*@param en [true for enable and false for disable.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_rx_en(bool_t en);
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/**
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*@brief phy_ana_enlic_en.
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*
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* enable analog enlic.
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*
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*@param val [0:off, 1:rx, 2:tx, 3:loopback.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_enlic_en(uint8_t val);
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/**
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*@brief phy_ana_filter_set.
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*
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* set analog filter value.
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*
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*@param val [valid value from 7 to 63.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_filter_set(uint8_t val);
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/**
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*@brief phy_ana_dbg_print.
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*
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* print analog debug register value.
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*
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*@param none [none.]
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*@exception [none.]
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*@return [none.]
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*/
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void phy_ana_dbg_print();
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/**
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*@brief phy_sadc_pt_init.
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*
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* init sadc reg for pt.
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*
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*@param none [none.]
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*@return [none.]
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*/
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void phy_sadc_pt_init();
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void phy_ana_tx_comp_set(bool_t tx_en);
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void phy_ana_tx_gpga_set(uint32_t data);
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void phy_ana_rx_pgfloop_set(bool_t en);
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void phy_ana_rx_fe_set(bool_t en);
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void phy_ana_rx_fe_gpga_offset(uint32_t data);
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void phy_ana_rx_fe_gpga(uint8_t data);
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void phy_ana_rx_bq_qvalue(uint8_t data);
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void phy_ana_rx_fe_gbq(uint8_t data);
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void phy_ana_rx_fe_gpgf_offset(uint32_t data);
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void phy_ana_rx_fe_gpgf(uint8_t data);
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void phy_ana_rx_fe_hpfenord2_set(bool_t en);
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void phy_ana_rx_fe_byphpf_set(bool_t en);
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void phy_ana_rx_fe_pwdpgf_offset_set(bool_t en);
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void phy_ana_rx_fe_pwdpga_offset_set(bool_t en);
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void phy_ana_rx_glna(uint8_t data);
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void phy_ana_top_tx_en(bool_t en);
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void phy_ana_top_rx_en(bool_t en);
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void phy_ana_top_adc_en(bool_t en);
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void phy_ana_top_dac_en(bool_t en);
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void phy_ana_top_enlic_rx_set(bool_t en);
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void phy_ana_top_enlic_tx_set(bool_t en);
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void phy_ana_rx_fe_selc_hpf(uint8_t data);
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void phy_ana_rx_fe_selc_pgf_bq(uint8_t data);
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void phy_ana_adc_set(bool_t en);
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uint32_t phy_ana_tx_pgacomp_read();
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void phy_ana_bias_ic0_cfg(uint32_t value);
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void phy_ana_bias_ic1_cfg(uint32_t value);
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void phy_ana_bias_ir0_cfg(uint32_t value);
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void phy_ana_bias_ir1_cfg(uint32_t value);
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/**
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*@brief phy_ana_hw_en_bitmap.
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*
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* init analog hw or sw control.
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*
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*@param value [value 0 for sw contrl,0xFFFFFFFF for hw contrl]
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*@return [none.]
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*/
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void phy_ana_hw_en_bitmap(uint32_t value);
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/**
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*@brief phy_ana_set_filter_init. ana filter init
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*
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*@param band_id [band id]
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*@return [none.]
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*/
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void phy_ana_set_filter_init(uint32_t band_id);
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#ifdef __cplusplus
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}
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#endif
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#endif // !PHY_ANA_H
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