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kunlun/plc/inc/plc_const.h
2024-09-28 14:24:04 +08:00

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/****************************************************************************
Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
be copied by any method or incorporated into another program without
the express written consent of Aerospace C.Power. This Information or any portion
thereof remains the property of Aerospace C.Power. The Information contained herein
is believed to be accurate and Aerospace C.Power assumes no responsibility or
liability for its use in any way and conveys no license or title under
any patent or copyright and makes no representation or warranty that this
Information is free from patent or copyright infringement.
****************************************************************************/
#ifndef PLC_CONST_H
#define PLC_CONST_H
#include "plc_utils.h"
#include "plc_cert_test.h"
#include "plc_conn_less.h"
#include "plc_mac_header.h"
#include "plc_mac_cfg.h"
#include "plc_beacon.h"
#include "plc_fr.h"
#include "hw_war.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
* max logic network number on a single node
* shared by SG, SPG(NW), and GP
* usually used by security setting
* NOTE: must be <= MAX_AVLN_HW_NUM, it's 8 for kunlun
*/
#define MAX_AVLN_NUM (1)
/* max logic key table number for an avln
* NOTE: must be <= MAX_KEY_TABLE_HW_NUM, it's 4 for kunlun
*/
#define MAX_KEY_TABLE_NUM (2)
/* max logic key number for a key table
* NOTE: must be <= MAX_KEY_ENTRY_HW_NUM, it's 32 for kunlun
*/
#define MAX_KEY_ENTRY_NUM (4)
#define MAC_QUE_NUM (24)
/* ieee1901 */
#define MAC_HDR_LEN_NO_VAR_I1901 (sizeof(i1901_mac_header_t))
#define MAC_HDR_LEN_WITH_VAR_I1901 (sizeof(i1901_mac_header_t) \
+ sizeof(i1901_mac_header_var_t))
#define MAC_HDR_LEN_WITH_VAR_ADDR_I1901 (MAC_HDR_LEN_WITH_VAR_I1901 \
+ IOT_MAC_ADDR_LEN * 2)
/* smart grid */
#define MAC_HDR_LEN_WITH_ADDR (sizeof(mac_header_t) + IOT_MAC_ADDR_LEN * 2)
#define MAC_HDR_LEN_NO_ADDR (sizeof(mac_header_t))
#define MAC_HDR_LEN_SHORT (sizeof(mac_short_header_t))
#define FC_LEN (sizeof(frame_control_t))
/* MAC layer required reserved len when sending data through mac_send_msdu_ex */
#define MAC_REQ_HEAD_RSVD_LEN (FC_LEN + 16)
#define MAC_REQ_TAIL_RSVD_LEN (4)
#define MME_HEAD_RESERVE_LEN (MAC_REQ_HEAD_RSVD_LEN)
#define MME_TAIL_RESERVE_LEN (MAC_REQ_TAIL_RSVD_LEN)
#define APP_HEAD_RESERVE_LEN (MAC_REQ_HEAD_RSVD_LEN + MAC_HDR_LEN_WITH_ADDR)
#define APP_TAIL_RESERVE_LEN (MAC_REQ_TAIL_RSVD_LEN)
#define APP_HEAD_CONN_LESS_RESERVE_LEN \
(APP_HEAD_RESERVE_LEN + sizeof(cert_test_t) + sizeof(plc_conn_less_hdr_t))
#define APP_HEAD_SILA_NHM_RESERVE_LEN \
(APP_HEAD_RESERVE_LEN + sizeof(nhm_header_t))
/* southern power grid */
#define MAC_LONG_HDR_LEN_SPG \
(sizeof(spg_mac_header_t) + sizeof(spg_mac_lheader_tail_t))
#define MAC_SHORT_HDR_LEN_SPG (sizeof(spg_mac_header_t))
#define MAC_SINGLE_HOP_HDR_LEN_SPG (sizeof(spg_mac_short_header_t))
#define MSDU_LONG_HDR_LEN_SPG (sizeof(spg_msdu_lfrm_t))
#define MSDU_SHORT_HDR_LEN_SPG (sizeof(spg_msdu_sfrm_t))
#define FC_LEN_SPG (sizeof(spg_frame_control_t))
#define MAC_REQ_HEAD_RSVD_LEN_SPG (FC_LEN_SPG + 16)
#define MAC_REQ_TAIL_RSVD_LEN_SPG (4)
#define MME_HEAD_RESERVE_LEN_SPG (MAC_REQ_HEAD_RSVD_LEN_SPG)
#define MME_TAIL_RESERVE_LEN_SPG (MAC_REQ_TAIL_RSVD_LEN_SPG)
#define APP_HEAD_RESERVE_LEN_SPG \
(MAC_REQ_HEAD_RSVD_LEN_SPG + MAC_LONG_HDR_LEN_SPG + MSDU_LONG_HDR_LEN_SPG \
+ 16)
#define APP_TAIL_RESERVE_LEN_SPG (MAC_REQ_TAIL_RSVD_LEN_SPG)
#define APP_HEAD_CONN_LESS_RESERVE_LEN_SPG \
(APP_HEAD_RESERVE_LEN_SPG + sizeof(spg_cert_test_hdr_t) + \
sizeof(plc_conn_less_hdr_t))
/* 1901 */
#define FC_LEN_1901 FC_LEN
#define PLC_PDEV_ID 0 // PLC default pDEV id
#define RF_PDEV_ID 0 // rf default PDEV id
#define PLC_DEFAULT_VDEV 0
#define PLC_INV_DBG_PKT_MODE_VDEV_ID 0xFF
#define PLC_MAX_PB_PER_MPDU 4
/* give smallest number, which is -128 */
#define INVALID_SNR (-128)
/* give smallest number, which is -128 */
#define INVALID_RSSI (-128)
/* give largest number, which is 127 */
#define MAX_SNR (127)
/* highest available snr */
#define SNR_HIGHEST (90)
/* lowest available snr */
#define SNR_LOWEST (-10)
/* update snr max threshold value */
#define MAX_FD_SNR (20)
/* update snr min threshold value */
#define MIN_FD_SNR (-10)
/* update rf snr max threshold value */
#define RF_MAX_FD_SNR (63)
/* update rf snr max threshold value */
#define RF_MIN_FD_SNR (0)
/* give smallest rf snr number, which is 0 */
#define RF_INVALID_SNR (INVALID_SNR)
/* rf highest snr value in protocal */
#define RF_SNR_HIGHEST (90)
/* rf lowest snr value in protocal */
#define RF_SNR_LOWEST (-10)
/* highest available rssi */
#define RF_RSSI_HIGHEST (-10)
/* lowest available rssi */
#define RF_RSSI_LOWEST (-110)
/* define rf tx power max value for smart power grid */
#define RF_TX_PWR_MAX_DBM_NSG (20)
/* define rf tx power min value for smart power grid */
#define RF_TX_PWR_MIN_DBM_NSG (-35)
/* define rf tx power default value for smart power grid */
#define RF_TX_PWR_DEF_DBM_NSG (10)
/* define rf tx full power value for smart power grid */
#define RF_TX_FULL_PWR_DBM_NSG (15)
/* define rf tx power max value for overseas power grid */
#define RF_TX_PWR_MAX_DBM_OVERSEAS (8)
/* define rf tx power min value for overseas power grid */
#define RF_TX_PWR_MIN_DBM_OVERSEAS (-35)
/* define rf tx power default value for overseas power grid */
#define RF_TX_PWR_DEF_DBM_OVERSEAS (8)
/* define rf tx full power value for overseas power grid */
#define RF_TX_FULL_PWR_DBM_OVERSEAS (8)
/* define rf loopback tx power value */
#define RF_TX_LOOPBACK_PWR_DBM (5)
/* define rf tx power invalid value */
#define RF_TX_PWR_INVALID (-128)
/* war for qianjing sack snr alway queal 100 */
#define WAR_QJWY_SNR_INPUT (100)
#define WAR_QJWY_SNR_OUTPUT (0)
/* calculate ppm parameter. 1 << 20 meanse 1million */
#define PPM_CALC_MILLION_SHIFT (20)
/* max ppm supported, if in this range, we try to re-cal */
#define PLC_MAX_PPM_SUPPORT (250)
/* ntb ppm shift bit, ntb_ppm_accuracy = 1/(1 << 6) ppm */
#define PLC_NTB_PPM_SHIFT (6)
/* register ppm shift bit, reg_ppm_accuracy = 1/(1 << 4) ppm */
#define PLC_REG_PPM_SHIFT (4)
/* max mac ntb supported */
#define PLC_MAX_MAC_NTB_PPM \
((PLC_MAX_PPM_SUPPORT) << (PLC_NTB_PPM_SHIFT))
/* the max ppm for sync ntb beacon */
#define PLC_SYNC_NTB_MAX_PPM (50 << PLC_NTB_PPM_SHIFT)
/* the max ppm for rf sync ntb beacon */
#define RF_SYNC_NTB_MAX_PPM (50 << PLC_NTB_PPM_SHIFT)
/* hw ppm available snr */
#define PLC_HW_PPM_AVL_SNR (20)
#if (HW_PLATFORM != HW_PLATFORM_SIMU)
/* KPI for Performance */
#if PLC_SUPPORT_CCO_ROLE
#if (IOT_FLASH_BUILD)
#if RUN_IN_PSRAM
#if (IOT_PSRAM_SIZE >= 4)
#define PCO_PERFORMANCE_MBPS (6) // x1 Mbps
#define PLC_LONG_BUF_MIN_NUM (50) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (140) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (6) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#else /* (IOT_PSRAM_SIZE >= 4) */
#define PCO_PERFORMANCE_MBPS (6) // x1 Mbps
#define PLC_LONG_BUF_MIN_NUM (30) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (100) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (6) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#endif /* (IOT_PSRAM_SIZE >= 4) */
#else /* RUN_IN_PSRAM */
#define PCO_PERFORMANCE_MBPS (1) // x1 Mbps
#define PLC_LONG_BUF_MIN_NUM (5) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (10) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (1) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#endif /* RUN_IN_PSRAM */
#else
/* PSRAM build don't have so much RAM */
#define PCO_PERFORMANCE_MBPS (1) // x1 Mbps
#define PLC_LONG_BUF_MIN_NUM (5) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (5) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (1) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#endif
#elif ((IOT_STA_CONTROL_MODE == IOT_STA_CONTROL_TYPE_STA) || \
(IOT_STA_CONTROL_MODE == IOT_STA_CONTROL_TYPE_METER) || \
(IOT_STA_CONTROL_MODE == IOT_STA_CONTROL_TYPE_PPM_DETECT) || \
IOT_DEV_TEST_CCO_MODE)
#if RUN_IN_PSRAM
#define PCO_PERFORMANCE_MBPS (6) // x6 Mbps
#define PLC_LONG_BUF_MIN_NUM (50) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (100) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (6) /* nmber of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#else
#define PCO_PERFORMANCE_MBPS (5/4) // x1.25 Mbps
#define PLC_LONG_BUF_MIN_NUM (6) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (21) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (4) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#endif
#else
#if RUN_IN_PSRAM
#define PCO_PERFORMANCE_MBPS (6) // x6 Mbps
#define PLC_LONG_BUF_MIN_NUM (50) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (100) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (20) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#else
#define PCO_PERFORMANCE_MBPS (1) // x1 Mbps
#define PLC_LONG_BUF_MIN_NUM (6) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (20) /* 1k buffer minimal requirement */
#define PLC_BCSMA_TOKEN_NUM (1) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#endif
#endif
#else /* HW_PLATFORM != HW_PLATFORM_SIMU */
#define PCO_PERFORMANCE_MBPS (6) // x6 Mbps
#define PLC_BCSMA_TOKEN_NUM (20) /* number of bound CSMA tokens */
#define PLC_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#if PLC_SUPPORT_CCO_ROLE
#define PLC_LONG_BUF_MIN_NUM (110) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (215) /* 1k buffer minimal requirement */
#else /* PLC_SUPPORT_CCO_ROLE */
#define PLC_LONG_BUF_MIN_NUM (6) /* 2k buffer minimal requirement */
#define PLC_LARGE_BUF_MIN_NUM (30) /* 1k buffer minimal requirement */
#endif /* PLC_SUPPORT_STA_ROLE */
#endif /* HW_PLATFORM == HW_PLATFORM_SIMU */
/* max buf required under KPI */
#define PCO_RX_DATA_BUF_KB ((64 * PCO_PERFORMANCE_MBPS) << 10)
#if HPLC_RF_DEV_SUPPORT
#if (PLC_NETWORK_SCALE > 1015)
/* 3K : reserved for rf discovery node list mme generation */
#define PLC_HUGE_BUF_SIZE (3000)
#define PLC_HUGE_BUF_COUNT (2)
#elif (PLC_NETWORK_SCALE > 256)
/* 2K : reserved for rf discovery node list mme generation */
#define PLC_HUGE_BUF_SIZE (PLC_LONG_BUF_SIZE)
#define PLC_HUGE_BUF_COUNT (0)
#else
/* 1K : reserved for rf discovery node list mme generation */
#define PLC_HUGE_BUF_SIZE (PLC_LARGE_BUF_SIZE)
#define PLC_HUGE_BUF_COUNT (0)
#endif
#else /* HPLC_RF_DEV_SUPPORT */
#if (PLC_NETWORK_SCALE > 1015)
/* 3K : reserved for discovery node list mme generation */
#define PLC_HUGE_BUF_SIZE (3000)
#define PLC_HUGE_BUF_COUNT (1)
#elif (PLC_NETWORK_SCALE > 256)
#define PLC_HUGE_BUF_SIZE (PLC_LONG_BUF_SIZE)
#define PLC_HUGE_BUF_COUNT (0)
#else
#define PLC_HUGE_BUF_SIZE (PLC_SHORT_BUF_SIZE)
#define PLC_HUGE_BUF_COUNT (0)
#endif
#endif /* HPLC_RF_DEV_SUPPORT */
/* 2K : 1/16 at least 2 */
#define PLC_LONG_BUF_SIZE (PLC_HW_RX_BUF_SIZE)
#define PLC_LONG_BUF_COUNT ((PCO_RX_DATA_BUF_KB/PLC_LONG_BUF_SIZE / 16) \
< PLC_LONG_BUF_MIN_NUM ? \
PLC_LONG_BUF_MIN_NUM : \
(PCO_RX_DATA_BUF_KB/PLC_LONG_BUF_SIZE / 16))
#define PLC_LONG_RX_BUF_COUNT (PLC_LONG_BUF_COUNT / 2)
#define PLC_LONG_TX_BUF_COUNT (PLC_LONG_BUF_COUNT - PLC_LONG_RX_BUF_COUNT)
/* 1K : 1/16 */
#define PLC_LARGE_BUF_SIZE (PLC_HW_RX_BUF_SIZE / 2)
#define PLC_LARGE_BUF_COUNT \
((PCO_RX_DATA_BUF_KB/PLC_LARGE_BUF_SIZE / 16) < PLC_LARGE_BUF_MIN_NUM ? \
PLC_LARGE_BUF_MIN_NUM : (PCO_RX_DATA_BUF_KB/PLC_LARGE_BUF_SIZE / 16))
#define PLC_LARGE_RX_BUF_COUNT (PLC_LARGE_BUF_COUNT / 2)
#define PLC_LARGE_TX_BUF_COUNT (PLC_LARGE_BUF_COUNT - PLC_LARGE_RX_BUF_COUNT)
/* 136 : 3/8, in rx ring */
#define PLC_SMALL_BUF_SIZE (PLC_RX_BUF_RESV_SIZE + 136 + MAC_HW_WAR_RESV_BYTES)
#if (PLC_SUPPORT_STA_ROLE && (TARGET_VERSION == TARGET_KUNLUN))
#define PLC_SMALL_BUF_COUNT ((PCO_RX_DATA_BUF_KB/PLC_SMALL_BUF_SIZE / 8 * 3) \
- 10)
#else /* PLC_SUPPORT_STA_ROLE && (TARGET_VERSION == TARGET_KUNLUN) */
#define PLC_SMALL_BUF_COUNT ((PCO_RX_DATA_BUF_KB/PLC_SMALL_BUF_SIZE / 8 * 3))
#endif /* PLC_SUPPORT_STA_ROLE && (TARGET_VERSION == TARGET_KUNLUN) */
#define PLC_SMALL_RX_BUF_COUNT (PLC_SMALL_BUF_COUNT / 2)
#define PLC_SMALL_TX_BUF_COUNT (PLC_SMALL_BUF_COUNT - PLC_SMALL_RX_BUF_COUNT)
/* 520 : 4/8, in rx ring */
/* the rest alloc to 520's buffer size */
#define PLC_SHORT_BUF_SIZE (PLC_RX_BUF_RESV_SIZE + 520 \
+ MAC_HW_WAR_RESV_BYTES + MAC_HW_WAR_SPG_RESV_SHORT_BYTES)
#define PLC_SHORT_BUF_COUNT (PCO_RX_DATA_BUF_KB/PLC_SHORT_BUF_SIZE / 8 * 4)
#define PLC_SHORT_RX_BUF_COUNT (PLC_SHORT_BUF_COUNT / 2)
#define PLC_SHORT_TX_BUF_COUNT (PLC_SHORT_BUF_COUNT - PLC_SHORT_RX_BUF_COUNT)
#if HPLC_RF_DEV_SUPPORT
#if RUN_IN_PSRAM
#define RF_PCO_PERFORMANCE_MBPS (6)
#else /* RUN_IN_PSRAM */
#define RF_PCO_PERFORMANCE_MBPS (1)
#endif /* RUN_IN_PSRAM */
#else /* HPLC_RF_DEV_SUPPORT */
#define RF_PCO_PERFORMANCE_MBPS (0)
#endif /* HPLC_RF_DEV_SUPPORT */
//TODO: fix rf performance base on chip
#define RF_PCO_RX_DATA_BUF_KB ((64 * RF_PCO_PERFORMANCE_MBPS) << 10)
/* 136: 1/2, rf in rx ring buffer */
#define RF_SMALL_BUF_COUNT (RF_PCO_RX_DATA_BUF_KB / PLC_SMALL_BUF_SIZE / 2)
#define RF_SMALL_RX_BUF_COUNT (RF_SMALL_BUF_COUNT / 2)
#define RF_SMALL_TX_BUF_COUNT (RF_SMALL_BUF_COUNT - RF_SMALL_RX_BUF_COUNT)
/* 520: 1/2, rf in rx ring buffer */
#define RF_SHORT_BUF_COUNT (RF_PCO_RX_DATA_BUF_KB / PLC_SHORT_BUF_SIZE / 2)
#define RF_SHORT_RX_BUF_COUNT (RF_SHORT_BUF_COUNT / 2)
#define RF_SHORT_TX_BUF_COUNT (RF_SHORT_BUF_COUNT - RF_SHORT_RX_BUF_COUNT)
#if RUN_IN_PSRAM
#define RF_BCSMA_TOKEN_NUM (20) /* number of bound CSMA tokens */
#define RF_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#else
#define RF_BCSMA_TOKEN_NUM (1) /* number of bound CSMA tokens */
#define RF_TDMA_TOKEN_NUM (1) /* number of bound TDMA tokens */
#endif
/* AVG pkt len */
#define PCO_AVG_PKT_LEN_KB (1) // 1k Byte
/* MAX Peer NUM support when not dropping packet under KPI */
#define PCO_PEER_NUM_SUPPORT \
(PCO_RX_DATA_BUF_KB / PCO_AVG_PKT_LEN_KB)
/* plc debug pkt mode parameter */
/* debug pkt mode tx/rx nid */
#define PLC_DBG_PKT_MODE_NID 0
/* debug pkt mode default link id */
#define PLC_DBG_PKT_MODE_DEF_LID LID_CSMA_CAP3
/* debug pkt mode default tx/rx phase */
#define PLC_DBG_PKT_MODE_DEF_PHASE PLC_PHASE_ALL
/* rf rssi value */
#define INV_RSSI_RF (INVALID_RSSI)
#define MAX_RSSI_RF (127)
#define MIN_RSSI_RF (-127)
/* NTB tick number for each ms */
#define NTB_TICKS_PER_MS (25000)
/* rf bcn slot tx reserver time, unit: 1us */
#define RF_BCN_TX_RESERVE_US (7 * 1000)
#ifdef __cplusplus
}
#endif
#endif // PLC_CONST_H