Files
kunlun/sp/boot/startup/hw/init_1.c
2024-09-28 14:24:04 +08:00

73 lines
1.9 KiB
C

/****************************************************************************
*
* Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
*
* This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
* be copied by any method or incorporated into another program without
* the express written consent of Aerospace C.Power. This Information or any portion
* thereof remains the property of Aerospace C.Power. The Information contained herein
* is believed to be accurate and Aerospace C.Power assumes no responsibility or
* liability for its use in any way and conveys no license or title under
* any patent or copyright and makes no representation or warranty that this
* Information is free from patent or copyright infringement.
*
* ****************************************************************************/
/* os shim includes */
#include "os_types.h"
#include "iot_irq.h"
#include "iot_wdg.h"
#include "efuse.h"
#include "iot_system.h"
#include "platform.h"
#include "encoding.h"
#include "apb.h"
extern void def_trap_entry_1();
extern void intc_handler(uint32_t cpu);
extern void trigger_zero_addr_access_detect();
extern void ahb_core0_enable();
uintptr_t handle_trap_1(uintptr_t mcause, uintptr_t epc, saved_registers *reg)
{
if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT) {
intc_handler(HAL_INTR_CPU_1);
}else {
}
return epc;
}
void _init_1()
{
/* efuse protect */
//efuse_protect();
apb_enable_ana_pfm(false);
/*disable limited curent to 250mA*/
apb_enable_ana_lmtcur(false);
/*enable core0*/
ahb_core0_enable();
write_csr(mtvec, &def_trap_entry_1);
clear_csr(mie, MIP_MEIP);
clear_csr(mie, MIP_MTIP);
iot_interrupt_init(HAL_INTR_CPU_1);
set_csr(mie, MIP_MEIP);
// Enable interrupts in general.
set_csr(mstatus, MSTATUS_MIE);
}
void _fini()
{
}