296 lines
8.7 KiB
C
296 lines
8.7 KiB
C
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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/* os shim includes */
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#include "iot_config.h"
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#include "os_types.h"
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#include "hw_reg_api.h"
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#include "iot_errno_api.h"
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/* driver includes */
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#include "phy_nf.h"
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#include "phy_bb.h"
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#include "os_timer_api.h"
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#include "phy_rxtd_reg.h"
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#include "mac_sys_reg.h"
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#include "iot_io.h"
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#include "hw_phy_api.h"
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#include "iot_system.h"
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#include "phy_ana_reg.h"
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#include "mac_rf_common_hw.h"
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#include "os_utils_api.h"
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/* callback for phy call mac dsr function */
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phy_call_mac_dsr_cb_t phy_call_mac_dsr_cb = NULL;
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/* callback for phy call mac spur function */
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phy_call_mac_spur_cb_t phy_call_mac_spur_cb = NULL;
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/* callback for phy call mac scan band function */
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phy_call_mac_scan_band_cb_t phy_call_mac_scan_band_cb = NULL;
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/* callback for phy call mac spur function */
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phy_call_mac_rf_scan_cb_t phy_call_mac_rf_scan_cb = NULL;
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/* function callback to trigger specific processing for phy rf tx power
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* compensation.
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*/
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phy_rf_tx_power_comen_cb_t phy_rf_tx_power_comen_cb = NULL;
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void register_phy_call_mac_dsr_cb(phy_call_mac_dsr_cb_t cb)
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{
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phy_call_mac_dsr_cb = cb;
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}
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void register_phy_call_mac_spur_cb(phy_call_mac_spur_cb_t cb)
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{
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phy_call_mac_spur_cb = cb;
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}
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void register_phy_call_mac_scan_band_cb(phy_call_mac_scan_band_cb_t cb)
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{
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phy_call_mac_scan_band_cb = cb;
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}
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void register_phy_call_mac_rf_scan_cb(phy_call_mac_rf_scan_cb_t cb)
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{
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phy_call_mac_rf_scan_cb = cb;
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}
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void register_phy_rf_tx_power_comen_cb(phy_rf_tx_power_comen_cb_t cb)
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{
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phy_rf_tx_power_comen_cb = cb;
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}
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uint8_t phy_agc_acc_dly_get(void)
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{
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uint32_t tmp = 0;
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uint8_t dly_exp = 0;
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/*
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* get 20ms dly for different acc step
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* 192/ 384/ 768/ 1536/ 3072/ 6144/
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*/
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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switch(REG_FIELD_GET(SW_AGC_ACC_STEP_HS, tmp))
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{
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case 0: dly_exp = 13; break;
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case 1: dly_exp = 12; break;
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case 2: dly_exp = 11; break;
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case 3: dly_exp = 10; break;
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case 4: dly_exp = 9; break;
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case 5: dly_exp = 8; break;
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default: dly_exp = 10; break;
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}
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return dly_exp;
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}
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void phy_cal_nf_systick_stop()
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{
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}
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void phy_cal_nf_on_3phase()
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{
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}
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void phy_snr_cal_timer_handler()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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uint8_t dly_exp = 0;
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uint8_t current_nf = 0;
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static uint8_t cnt = 0;
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iot_phy_sts_info_t total_sts = {0};
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/* update log cnt */
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phy_rx_cnt_t *phy_rx_info = &g_phy_ctxt.dep.phy_status.phy_rx_cnt;
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/* check cal noise done */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
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if(REG_FIELD_GET(SW_CAL_NOISE_DONE,tmp))
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{
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current_nf = REG_FIELD_GET(SW_CAL_NOISE_PWR,tmp);
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/*121 is reset value, not valid value*/
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if (current_nf != PHY_NF_RST_VAL) {
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g_phy_ctxt.dep.nf = current_nf;
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}
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}
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/* cert mode check spike by nf */
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phy_cert_check_spike();
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/* update cpu share nf */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_ACC_STEP_ADDR);
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switch(REG_FIELD_GET(SW_AGC_ACC_STEP_HS, tmp))
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{
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case 0:
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g_phy_cpu_share_ctxt.nf_192p = g_phy_ctxt.dep.nf;
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break;
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case 1:
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g_phy_cpu_share_ctxt.nf_384p = g_phy_ctxt.dep.nf;
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break;
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case 2:
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g_phy_cpu_share_ctxt.nf_768p = g_phy_ctxt.dep.nf;
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break;
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case 3:
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g_phy_cpu_share_ctxt.nf_1536p = g_phy_ctxt.dep.nf;
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break;
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case 4:
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g_phy_cpu_share_ctxt.nf_3072p = g_phy_ctxt.dep.nf;
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break;
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case 5:
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g_phy_cpu_share_ctxt.nf_6144p = g_phy_ctxt.dep.nf;
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break;
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default:
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break;
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}
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/* get dly depend on ACC_STEP */
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dly_exp = phy_agc_acc_dly_get();
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/* config dly */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
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REG_FIELD_SET(SW_CAL_NOISE_DLY_EXP, tmp, dly_exp);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);
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/* trig again */
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tmp = PHY_RXTD_READ_REG(CFG_BB_AGC_NOISE_CAL_ADDR);
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REG_FIELD_SET(SW_CAL_NOISE_START, tmp, 1);
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PHY_RXTD_WRITE_REG(CFG_BB_AGC_NOISE_CAL_ADDR, tmp);
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/* print current noise floor */
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iot_printf("[PHY] nf:%d, rx_phase:%d\n", \
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g_phy_ctxt.dep.nf, \
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(RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR) & \
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PHY_RX_PHASE_SEL_MASK) >> PHY_RX_PHASE_SEL_OFFSET);
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#if HPLC_RF_DEV_SUPPORT
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/* for rf */
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mac_rf_record_dbg_cnt();
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#endif
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if (phy_get_fw_mode() == MM_MODE && \
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cnt >= 3) {
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phy_sts_get(&total_sts);
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iot_printf("mac tx ok:%d/4s, fc_ok:%d/4s, fc_err:%d/4s,", \
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total_sts.mac_tx_ok_cnt, total_sts.fc_crc_ok_cnt, \
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total_sts.fc_crc_fail_cnt);
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iot_printf("pld_ok:%d/4s, pld fail:%d/4s, sync ok:%d/4s, tempt:%d\r\n", \
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total_sts.pld_crc_ok_cnt, total_sts.pld_crc_fail_cnt, \
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total_sts.sync_ok_cnt, total_sts.phy_tempt_celsius);
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iot_printf("ANA_TOP:%x ",PHY_ANA_READ_REG(CFG_BB_ANA_TOP_ADDR));
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iot_printf("F_0:%x F_1:%x F_2:%x ",\
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RGF_MAC_READ_REG(CFG_PHY_FORCE_0_ADDR), \
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RGF_MAC_READ_REG(CFG_PHY_FORCE_1_ADDR), \
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RGF_MAC_READ_REG(CFG_PHY_FORCE_2_ADDR));
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extern uint32_t mac_get_tx_rifs();
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iot_printf("INTF_0:%x INTF_1:%x, rifs:%lu\r\n", \
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RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_0_ADDR),\
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RGF_MAC_READ_REG(CFG_RD_MACPHY_INTF_1_ADDR),
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mac_get_tx_rifs());
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phy_rx_info->phy_rx_fc_ok_cnt += total_sts.fc_crc_ok_cnt;
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phy_rx_info->phy_rx_fc_fail_cnt += total_sts.fc_crc_fail_cnt;
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phy_rx_info->phy_rx_pld_ok_cnt += total_sts.pld_crc_ok_cnt;
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phy_rx_info->phy_rx_pld_fail_cnt += total_sts.pld_crc_fail_cnt;
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phy_rx_info->phy_rx_pkt_cnt += total_sts.sync_ok_cnt;
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g_phy_ctxt.dep.phy_status.phy_tx_pkt_cnt += total_sts.mac_tx_ok_cnt;
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#if HPLC_RF_DEV_SUPPORT
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iot_printf("mac rf tx:%lu, tx_ok_wp:%lu, tx_ok_wop:%lu\n"
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"stf:%lu, sig_ok:%lu, sig_err:%lu, phr_ok_wp:%lu, "
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"phr_ok_wop:%lu, phr_err:%lu, pld_ok:%lu, pld_err:%lu, "
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"loststf:%lu\n",
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phy_rx_info->phy_rf_tx_start_cnt,
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phy_rx_info->phy_rf_tx_ok_with_pld_cnt,
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phy_rx_info->phy_rf_tx_ok_without_pld_cnt,
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phy_rx_info->phy_rf_rx_stf_cnt,
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phy_rx_info->phy_rf_rx_sig_ok_cnt,
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phy_rx_info->phy_rf_rx_sig_err_cnt,
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phy_rx_info->phy_rf_rx_phr_ok_with_pld_cnt,
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phy_rx_info->phy_rf_rx_phr_ok_without_pld_cnt,
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phy_rx_info->phy_rf_rx_phr_err_cnt,
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phy_rx_info->phy_rf_rx_pld_ok_cnt,
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phy_rx_info->phy_rf_rx_pld_err_cnt,
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phy_rx_info->phy_rf_lost_stf_cnt);
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#endif
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cnt = 0;
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} else {
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cnt++;
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}
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/* overstress handle */
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phy_overstress_timer_handler();
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if (phy_call_mac_scan_band_cb) {
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phy_call_mac_scan_band_cb();
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}
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/* judge restart rf scan timer or not */
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if (phy_call_mac_rf_scan_cb) {
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phy_call_mac_rf_scan_cb();
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}
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if (phy_call_mac_spur_cb) {
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phy_call_mac_spur_cb();
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}
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if (phy_rf_tx_power_comen_cb) {
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phy_rf_tx_power_comen_cb();
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}
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#if MAC_SYM_NUM_FIX
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if (os_boot_time32() > 60000) {
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g_phy_cpu_share_ctxt.sym_num_fix_dis = 1;
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}
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#endif/* MAC_SYM_NUM_FIX */
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#endif
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}
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void phy_timer_handle()
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{
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if (phy_call_mac_dsr_cb) {
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phy_call_mac_dsr_cb();
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}
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}
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uint32_t phy_nf_timer_start()
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{
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uint32_t ret = ERR_FAIL;
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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if (g_phy_ctxt.dep.phy_snr_cal_timer == 0) {
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#if IOT_DTEST_ONLY_SUPPORT == 0
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g_phy_ctxt.dep.phy_snr_cal_timer = \
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os_create_timer(PLC_PHY_COMMON_MID, true,
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phy_timer_handle, NULL);
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#else
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g_phy_ctxt.dep.phy_snr_cal_timer = \
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os_create_timer(PLC_PHY_COMMON_MID, true,
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phy_snr_cal_timer_handler, NULL);
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#endif
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os_start_timer(g_phy_ctxt.dep.phy_snr_cal_timer, \
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PHY_SNR_CAL_TIMER_PERIOD);
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}
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#endif
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return ret;
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}
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