90 lines
3.3 KiB
C
90 lines
3.3 KiB
C
#ifndef CHIP_IRQ_VECTOR_H
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#define CHIP_IRQ_VECTOR_H
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enum CHIP_IRQ_VECTOR {
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GTMER0_INT = 0,
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GPIO_INT0 = 1,
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UART0_INT = 2,
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UART1_INT = 3,
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UART2_INT = 4,
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UART3_INT = 5,
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GTMER1_INT = 6,
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RFPLC_INT0_COMMON_IRQ = 7,
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RFPLC_INT1_COMMON_IRQ = 8,
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GPIO_INT1 = 9,
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PHY_INT_0 = 10,
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PHY_INT_1 = 11,
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PHY_INT_2 = 12,
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PHY_INT_3 = 13,
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PHY_INT_4 = 14,
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SPI_S0_INT = 15,
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DMA0_INT3 = 16,
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DMA0_INT2 = 17,
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DMA0_INT1 = 18,
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DMA0_INT0 = 19,
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LEDC_INT = 20,
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MAC_INT_0 = 21,
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MAC_INT_1 = 22,
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MAC_INT_2 = 23,
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MAC_INT_3 = 24,
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SPI_M0_INT = 25,
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I2C_M1_INT = 26,
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I2C_M0_INT = 27,
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WDG1_INT = 28,
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WDG1_TIMEOUT_INT = 29,
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WDG0_INT = 30,
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WDG0_TIMEOUT_INT = 31,
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SFC_DONE_INT = 32,
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ADA_INT = 33,
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PWM0_INT = 34,
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PWM1_INT = 35,
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PWM2_INT = 36,
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PWM3_INT = 37,
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UART7_INT = 38,
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UART6_INT = 39,
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UART5_INT = 40,
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UART4_INT = 41,
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RFPLC_INT1_COMMON_SHARE_IRQ = 42,
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RFPLC_INT1_COMMON_TIMEOUT = 43,
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RFPLC_INT0_COMMON_SHARE_IRQ = 44,
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RFPLC_INT0_COMMON_TIMEOUT = 45,
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DMA1_INT3 = 46,
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DMA1_INT2 = 47,
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DMA1_INT1 = 48,
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DMA1_INT0 = 49,
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WDG2_INT = 50,
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WDG2_TIMEOUT_INT = 51,
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SPI_M3_INT = 52,
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SPI_M2_INT = 53,
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SPI_M1_INT = 54,
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GTMR2_INT = 55,
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I2C_M2_INT = 56,
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MAILBOX0_INT = 57,
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MAILBOX1_INT = 58,
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MAILBOX2_INT = 59,
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MAILBOX3_INT = 60,
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MAILBOX4_INT = 61,
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MAILBOX5_INT = 62,
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SEC0_INT = 63,
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SEC1_INT = 64,
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I2C_M3_INT = 65,
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GMAC_SBD_INT = 66,
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USB_OTG_INT = 67,
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DMA2_INT3 = 68,
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DMA2_INT2 = 69,
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DMA2_INT1 = 70,
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DMA2_INT0 = 71,
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FFT_INT = 72,
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RTC_TMR_INT1 = 73,
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RTC_TMR_INT0 = 74,
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PWM4_INT = 75,
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PWM5_INT = 76,
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LEDC_FREE_INT = 77,
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GPIO_INT2 = 78,
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SADC_REG_INT = 79,
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TPID_REG_INT = 80,
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CHIP_IRQ_VECTOR_MAX,
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};
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#endif |