204 lines
6.6 KiB
C
204 lines
6.6 KiB
C
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//-----------------------------------
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#define CFG_TIMER0_ADDR 0x0000
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#define CFG_RCG_TIMER_OFFSET 16
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#define CFG_RCG_TIMER_MASK 0xFFFF0000
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#define CFG_CMG_TIMER_OFFSET 0
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#define CFG_CMG_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER1_ADDR 0x0004
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#define CFG_RIFS_TIMER_OFFSET 16
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#define CFG_RIFS_TIMER_MASK 0xFFFF0000
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#define CFG_CIFS_TIMER_OFFSET 0
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#define CFG_CIFS_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER2_ADDR 0x0008
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#define CFG_TX_DELAY_OFFSET 22
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#define CFG_TX_DELAY_MASK 0xFFC00000
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#define CFG_RX_SHORT_DELAY_OFFSET 11
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#define CFG_RX_SHORT_DELAY_MASK 0x003FF800
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#define CFG_RX_LONG_DELAY_OFFSET 0
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#define CFG_RX_LONG_DELAY_MASK 0x000007FF
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//-----------------------------------
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#define CFG_TIMER3_ADDR 0x000c
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#define CFG_DELIMITER_TIMER1_OFFSET 16
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#define CFG_DELIMITER_TIMER1_MASK 0xFFFF0000
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#define CFG_DELIMITER_TIMER0_OFFSET 0
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#define CFG_DELIMITER_TIMER0_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER4_ADDR 0x0010
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#define CFG_FC_LEN_TIMER1_OFFSET 16
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#define CFG_FC_LEN_TIMER1_MASK 0xFFFF0000
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#define CFG_FC_LEN_TIMER0_OFFSET 0
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#define CFG_FC_LEN_TIMER0_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER5_ADDR 0x0014
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#define CFG_BIFS_TIMER_OFFSET 16
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#define CFG_BIFS_TIMER_MASK 0xFFFF0000
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#define CFG_EIFS_TIMER_OFFSET 0
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#define CFG_EIFS_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER6_ADDR 0x0018
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#define CFG_AIFS_TIMER_OFFSET 16
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#define CFG_AIFS_TIMER_MASK 0xFFFF0000
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#define CFG_B2BIFS_TIMER_OFFSET 0
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#define CFG_B2BIFS_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER7_ADDR 0x001c
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#define CFG_PRS_SLOT_TIMER_OFFSET 0
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#define CFG_PRS_SLOT_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER8_ADDR 0x0020
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#define CFG_SLOT_TIMER_OFFSET 0
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#define CFG_SLOT_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER9_ADDR 0x0024
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#define CFG_DELIMITER_TIMER3_OFFSET 16
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#define CFG_DELIMITER_TIMER3_MASK 0xFFFF0000
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#define CFG_DELIMITER_TIMER2_OFFSET 0
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#define CFG_DELIMITER_TIMER2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_TIMER10_ADDR 0x0028
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#define CFG_FC_LEN_TIMER3_OFFSET 16
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#define CFG_FC_LEN_TIMER3_MASK 0xFFFF0000
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#define CFG_FC_LEN_TIMER2_OFFSET 0
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#define CFG_FC_LEN_TIMER2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_TIMER0_ADDR 0x002c
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#define CFG_SG_CIFS_TIMER_OFFSET 16
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#define CFG_SG_CIFS_TIMER_MASK 0xFFFF0000
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#define CFG_SG_EIFS_TIMER_OFFSET 0
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#define CFG_SG_EIFS_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_TIMER1_ADDR 0x0030
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#define CFG_SG_RIFS_TIMER_OFFSET 0
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#define CFG_SG_RIFS_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_TIMER2_ADDR 0x0034
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#define CFG_SG_TX_DELAY_OFFSET 0
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#define CFG_SG_TX_DELAY_MASK 0x000003FF
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//-----------------------------------
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#define CFG_SG_TIMER3_ADDR 0x0038
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#define CFG_SG_RX_SHORT_DELAY_OFFSET 0
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#define CFG_SG_RX_SHORT_DELAY_MASK 0x000007FF
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//-----------------------------------
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#define CFG_SG_TIMER4_ADDR 0x003C
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#define CFG_SG_RX_LONG_DELAY_OFFSET 0
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#define CFG_SG_RX_LONG_DELAY_MASK 0x000007FF
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//-----------------------------------
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#define CFG_SG_TIMER5_ADDR 0x0040
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#define CFG_SG_DELIMITER_TIMER_1_OFFSET 16
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#define CFG_SG_DELIMITER_TIMER_1_MASK 0xFFFF0000
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#define CFG_SG_DELIMITER_TIMER_0_OFFSET 0
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#define CFG_SG_DELIMITER_TIMER_0_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_TIMER6_ADDR 0x0044
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#define CFG_SG_DELIMITER_TIMER_3_OFFSET 16
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#define CFG_SG_DELIMITER_TIMER_3_MASK 0xFFFF0000
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#define CFG_SG_DELIMITER_TIMER_2_OFFSET 0
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#define CFG_SG_DELIMITER_TIMER_2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_TIMER7_ADDR 0x0048
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#define CFG_SG_FC_LEN_TIMER_1_OFFSET 16
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#define CFG_SG_FC_LEN_TIMER_1_MASK 0xFFFF0000
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#define CFG_SG_FC_LEN_TIMER_0_OFFSET 0
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#define CFG_SG_FC_LEN_TIMER_0_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_TIMER8_ADDR 0x004c
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#define CFG_SG_FC_LEN_TIMER_3_OFFSET 16
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#define CFG_SG_FC_LEN_TIMER_3_MASK 0xFFFF0000
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#define CFG_SG_FC_LEN_TIMER_2_OFFSET 0
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#define CFG_SG_FC_LEN_TIMER_2_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_TIMER9_ADDR 0x0050
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#define CFG_SG_B2BIFS_TIMER_OFFSET 0
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#define CFG_SG_B2BIFS_TIMER_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_SG_DUMMY1_ADDR 0x0054
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//-----------------------------------
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#define CFG_TMR_CTRL_ADDR 0x0058
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#define CFG_EIFS_SELECT_OFFSET 0
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#define CFG_EIFS_SELECT_MASK 0x00000001
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//-----------------------------------
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#define CFG_VCS_CNT_ADDR 0x0060
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#define CFG_VCS_TRACK_USE_FC_RCV_DONE_OFFSET 17
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#define CFG_VCS_TRACK_USE_FC_RCV_DONE_MASK 0x00020000
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#define CFG_VCS_INIT_VALUE_OFFSET 1
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#define CFG_VCS_INIT_VALUE_MASK 0x0001FFFE
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#define CFG_VCS_INIT_LOAD_TRIG_OFFSET 0
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#define CFG_VCS_INIT_LOAD_TRIG_MASK 0x00000001
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//-----------------------------------
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#define CFG_VCS_CTRL_ADDR 0x0064
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#define CFG_TX_CIFS_VCS_EN_OFFSET 1
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#define CFG_TX_CIFS_VCS_EN_MASK 0x00000002
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#define CFG_RX_CIFS_VCS_EN_OFFSET 0
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#define CFG_RX_CIFS_VCS_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_TX_FC_CTRL_ADDR 0x0068
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#define CFG_TX_FC_FL_BY_SW_OFFSET 2
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#define CFG_TX_FC_FL_BY_SW_MASK 0x00000004
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#define CFG_TX_FC_PBNUM_BY_SW_OFFSET 1
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#define CFG_TX_FC_PBNUM_BY_SW_MASK 0x00000002
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#define CFG_TX_FC_SYMBNUM_BY_SW_OFFSET 0
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#define CFG_TX_FC_SYMBNUM_BY_SW_MASK 0x00000001
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//-----------------------------------
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#define CFG_NTB_COMM_INT0_VAL_ADDR 0x006c
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#define CFG_NTB_COMM_INT0_VAL_OFFSET 0
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#define CFG_NTB_COMM_INT0_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_NTB_COMM_INT1_VAL_ADDR 0x0070
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#define CFG_NTB_COMM_INT1_VAL_OFFSET 0
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#define CFG_NTB_COMM_INT1_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_NTB_COMM_INT2_VAL_ADDR 0x0074
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#define CFG_NTB_COMM_INT2_VAL_OFFSET 0
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#define CFG_NTB_COMM_INT2_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_NTB_COMM_INT3_VAL_ADDR 0x0078
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#define CFG_NTB_COMM_INT3_VAL_OFFSET 0
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#define CFG_NTB_COMM_INT3_VAL_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_NTB_COMM_INT_CTRL_ADDR 0x007c
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#define CFG_NTB_COMM_INT3_EN_OFFSET 3
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#define CFG_NTB_COMM_INT3_EN_MASK 0x00000008
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#define CFG_NTB_COMM_INT2_EN_OFFSET 2
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#define CFG_NTB_COMM_INT2_EN_MASK 0x00000004
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#define CFG_NTB_COMM_INT1_EN_OFFSET 1
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#define CFG_NTB_COMM_INT1_EN_MASK 0x00000002
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#define CFG_NTB_COMM_INT0_EN_OFFSET 0
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#define CFG_NTB_COMM_INT0_EN_MASK 0x00000001
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//HW module read/write macro
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#define RGF_TMR_READ_REG(addr) SOC_READ_REG(RGF_TMR_BASEADDR + addr)
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#define RGF_TMR_WRITE_REG(addr,value) SOC_WRITE_REG(RGF_TMR_BASEADDR + addr,value)
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