794 lines
27 KiB
C
Executable File
794 lines
27 KiB
C
Executable File
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//-----------------------------------
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#define CFG_BB_ADA_FORMAT_CFG_ADDR 0x0000
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#define SW_AGC_DATA_VLD_SEL_OFFSET 13
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#define SW_AGC_DATA_VLD_SEL_MASK 0x00006000
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#define SW_SOC_ADC_SEL_OFFSET 11
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#define SW_SOC_ADC_SEL_MASK 0x00001800
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#define SW_MON_ADC_SEL_OFFSET 10
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#define SW_MON_ADC_SEL_MASK 0x00000400
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#define SW_AGC_RAW_DATA_SEL_OFFSET 9
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#define SW_AGC_RAW_DATA_SEL_MASK 0x00000200
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#define SW_SADC_DATA_INV_OFFSET 8
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#define SW_SADC_DATA_INV_MASK 0x00000100
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#define SW_DAC_DATA_INV_OFFSET 7
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#define SW_DAC_DATA_INV_MASK 0x00000080
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#define SW_ADC_DATA_INV_OFFSET 6
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#define SW_ADC_DATA_INV_MASK 0x00000040
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#define SW_SADC_DATA_FORMAT_OFFSET 5
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#define SW_SADC_DATA_FORMAT_MASK 0x00000020
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#define SW_DAC_DATA_FORMAT_OFFSET 4
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#define SW_DAC_DATA_FORMAT_MASK 0x00000010
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#define SW_ADC_DATA_FORMAT_OFFSET 3
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#define SW_ADC_DATA_FORMAT_MASK 0x00000008
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#define SW_CLK_SADC_INV_EN_OFFSET 2
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#define SW_CLK_SADC_INV_EN_MASK 0x00000004
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#define SW_CLK_DAC_INV_EN_OFFSET 1
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#define SW_CLK_DAC_INV_EN_MASK 0x00000002
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#define SW_CLK_ADC_INV_EN_OFFSET 0
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#define SW_CLK_ADC_INV_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_DC_COMP0_ADDR 0x0004
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#define SW_DC_COMP_GAIN3_OFFSET 24
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#define SW_DC_COMP_GAIN3_MASK 0xFF000000
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#define SW_DC_COMP_GAIN2_OFFSET 16
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#define SW_DC_COMP_GAIN2_MASK 0x00FF0000
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#define SW_DC_COMP_GAIN1_OFFSET 8
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#define SW_DC_COMP_GAIN1_MASK 0x0000FF00
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#define SW_DC_COMP_GAIN0_OFFSET 0
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#define SW_DC_COMP_GAIN0_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_DC_COMP1_ADDR 0x0008
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#define SW_DC_COMP_GAIN7_OFFSET 24
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#define SW_DC_COMP_GAIN7_MASK 0xFF000000
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#define SW_DC_COMP_GAIN6_OFFSET 16
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#define SW_DC_COMP_GAIN6_MASK 0x00FF0000
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#define SW_DC_COMP_GAIN5_OFFSET 8
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#define SW_DC_COMP_GAIN5_MASK 0x0000FF00
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#define SW_DC_COMP_GAIN4_OFFSET 0
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#define SW_DC_COMP_GAIN4_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_PPM_SETTING_ADDR 0x000C
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#define SW_TX_PPM_OFFSET 16
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#define SW_TX_PPM_MASK 0xFFFF0000
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#define SW_RX_PPM_OFFSET 0
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#define SW_RX_PPM_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_PPM_FIFO_SETTING_ADDR 0x0010
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#define SW_EN_RX_FREQ_PPM_OFFSET 29
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#define SW_EN_RX_FREQ_PPM_MASK 0x20000000
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#define SW_RX_PPM_FIFO_EMPTY_TH_OFFSET 24
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#define SW_RX_PPM_FIFO_EMPTY_TH_MASK 0x1F000000
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#define SW_RX_PPM_FIFO_CD_EN_OFFSET 23
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#define SW_RX_PPM_FIFO_CD_EN_MASK 0x00800000
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#define SW_RX_PPM_FIFO_FULL_CNT_CLR_OFFSET 22
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#define SW_RX_PPM_FIFO_FULL_CNT_CLR_MASK 0x00400000
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#define SW_RX_PPM_FIFO_EMPTY_CNT_CLR_OFFSET 21
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#define SW_RX_PPM_FIFO_EMPTY_CNT_CLR_MASK 0x00200000
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#define SW_RX_PPM_FIFO_FULL_TH_OFFSET 16
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#define SW_RX_PPM_FIFO_FULL_TH_MASK 0x001F0000
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#define SW_TX_PPM_FIFO_EMPTY_TH_OFFSET 8
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#define SW_TX_PPM_FIFO_EMPTY_TH_MASK 0x00001F00
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#define SW_TX_PPM_FIFO_CD_EN_OFFSET 7
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#define SW_TX_PPM_FIFO_CD_EN_MASK 0x00000080
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#define SW_TX_PPM_FIFO_FULL_CNT_CLR_OFFSET 6
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#define SW_TX_PPM_FIFO_FULL_CNT_CLR_MASK 0x00000040
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#define SW_TX_PPM_FIFO_EMPTY_CNT_CLR_OFFSET 5
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#define SW_TX_PPM_FIFO_EMPTY_CNT_CLR_MASK 0x00000020
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#define SW_TX_PPM_FIFO_FULL_TH_OFFSET 0
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#define SW_TX_PPM_FIFO_FULL_TH_MASK 0x0000001F
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//-----------------------------------
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#define CFG_BB_PPM_EST_SETTING_ADDR 0x0014
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#define SW_RO_FREQ_PPM_OFFSET 0
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#define SW_RO_FREQ_PPM_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_TX_CLIP_CFG_ADDR 0x0018
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#define SW_TXCLIP_EN_OFFSET 31
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#define SW_TXCLIP_EN_MASK 0x80000000
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#define SW_TXCLIP_16QAM_TH_OFFSET 20
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#define SW_TXCLIP_16QAM_TH_MASK 0x3FF00000
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#define SW_TXCLIP_QPSK_TH_OFFSET 10
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#define SW_TXCLIP_QPSK_TH_MASK 0x000FFC00
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#define SW_TXCLIP_BPSK_TH_OFFSET 0
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#define SW_TXCLIP_BPSK_TH_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_DEC_CIC_SETTING_ADDR 0x001C
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#define SW_RX_XR_SHIFT_EN_OFFSET 1
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#define SW_RX_XR_SHIFT_EN_MASK 0x00000002
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#define SW_RX_QR_SHIFT_EN_OFFSET 0
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#define SW_RX_QR_SHIFT_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_RX_PPM_SETTING_ADDR 0x0020
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#define SW_DIS_RX_QR_PPM_OFFSET 31
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#define SW_DIS_RX_QR_PPM_MASK 0x80000000
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#define SW_DIS_RX_XR_PPM_OFFSET 30
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#define SW_DIS_RX_XR_PPM_MASK 0x40000000
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#define SW_DIS_RX_QR_PPM_GI_OFFSET 29
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#define SW_DIS_RX_QR_PPM_GI_MASK 0x20000000
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#define SW_DIS_RX_XR_PPM_GI_OFFSET 28
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#define SW_DIS_RX_XR_PPM_GI_MASK 0x10000000
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#define SW_DIS_RX_PPM_GI_WIN_POS_OFFSET 27
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#define SW_DIS_RX_PPM_GI_WIN_POS_MASK 0x08000000
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#define SW_RX_PPM_START_N_OFFSET 16
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#define SW_RX_PPM_START_N_MASK 0x001F0000
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#define SW_RX_PPM_START_P_OFFSET 8
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#define SW_RX_PPM_START_P_MASK 0x00001F00
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#define SW_RX_PPM_START_0_OFFSET 0
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#define SW_RX_PPM_START_0_MASK 0x0000001F
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//-----------------------------------
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#define CFG_BB_TX_PPM_SETTING_ADDR 0x0024
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#define SW_DIS_TX_QR_PPM_OFFSET 31
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#define SW_DIS_TX_QR_PPM_MASK 0x80000000
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#define SW_DIS_TX_XR_PPM_OFFSET 30
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#define SW_DIS_TX_XR_PPM_MASK 0x40000000
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#define SW_DIS_TX_QR_PPM_GI_OFFSET 29
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#define SW_DIS_TX_QR_PPM_GI_MASK 0x20000000
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#define SW_DIS_TX_XR_PPM_GI_OFFSET 28
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#define SW_DIS_TX_XR_PPM_GI_MASK 0x10000000
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#define SW_DIS_TX_PPM_GI_WIN_POS_OFFSET 27
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#define SW_DIS_TX_PPM_GI_WIN_POS_MASK 0x08000000
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#define SW_TX_PPM_START_N_OFFSET 16
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#define SW_TX_PPM_START_N_MASK 0x001F0000
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#define SW_TX_PPM_START_P_OFFSET 8
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#define SW_TX_PPM_START_P_MASK 0x00001F00
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#define SW_TX_PPM_START_0_OFFSET 0
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#define SW_TX_PPM_START_0_MASK 0x0000001F
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//-----------------------------------
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#define CFG_BB_ANA_TX_PGA_SELC_ADDR 0x0028
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#define SW_TX_SELC_PGA_GAIN7_OFFSET 28
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#define SW_TX_SELC_PGA_GAIN7_MASK 0x70000000
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#define SW_TX_SELC_PGA_GAIN6_OFFSET 24
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#define SW_TX_SELC_PGA_GAIN6_MASK 0x07000000
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#define SW_TX_SELC_PGA_GAIN5_OFFSET 20
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#define SW_TX_SELC_PGA_GAIN5_MASK 0x00700000
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#define SW_TX_SELC_PGA_GAIN4_OFFSET 16
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#define SW_TX_SELC_PGA_GAIN4_MASK 0x00070000
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#define SW_TX_SELC_PGA_GAIN3_OFFSET 12
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#define SW_TX_SELC_PGA_GAIN3_MASK 0x00007000
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#define SW_TX_SELC_PGA_GAIN2_OFFSET 8
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#define SW_TX_SELC_PGA_GAIN2_MASK 0x00000700
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#define SW_TX_SELC_PGA_GAIN1_OFFSET 4
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#define SW_TX_SELC_PGA_GAIN1_MASK 0x00000070
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#define SW_TX_SELC_PGA_GAIN0_OFFSET 0
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#define SW_TX_SELC_PGA_GAIN0_MASK 0x00000007
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//-----------------------------------
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#define CFG_BB_DFE_RESET_CTRL_ADDR 0x002C
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#define SW_GAIN_CHG_RST_OFFSET 0
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#define SW_GAIN_CHG_RST_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_SW_ADJUST_GAIN_ADDR 0x0100
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#define SW_TX_PWR_SCALE_FACTOR_OFFSET 16
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#define SW_TX_PWR_SCALE_FACTOR_MASK 0x001F0000
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#define SW_TX_GAIN_LEFT_SHIFT_OFFSET 13
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#define SW_TX_GAIN_LEFT_SHIFT_MASK 0x00002000
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#define SW_TX_GAIN_SHIFT_BITS_OFFSET 9
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#define SW_TX_GAIN_SHIFT_BITS_MASK 0x00001E00
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#define SW_IMPULSE_CANCLE_SHIFT_NUM_OFFSET 6
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#define SW_IMPULSE_CANCLE_SHIFT_NUM_MASK 0x000001C0
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#define SW_IMPULSE_CANCLE_SHIFT_EN_OFFSET 5
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#define SW_IMPULSE_CANCLE_SHIFT_EN_MASK 0x00000020
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#define SW_RX_GAIN_LEFT_SHIFT_OFFSET 4
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#define SW_RX_GAIN_LEFT_SHIFT_MASK 0x00000010
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#define SW_RX_GAIN_SHIFT_BITS_OFFSET 0
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#define SW_RX_GAIN_SHIFT_BITS_MASK 0x0000000F
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG0_ADDR 0x0104
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#define SW_GAIN_CFG0_DATA_OFFSET 0
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#define SW_GAIN_CFG0_DATA_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG0_START_ADDR 0x0108
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#define SW_GAIN_CFG0_START_OFFSET 0
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#define SW_GAIN_CFG0_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG1_ADDR 0x010c
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#define SW_GAIN_CFG1_DATA_OFFSET 0
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#define SW_GAIN_CFG1_DATA_MASK 0x000000FF
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//-----------------------------------
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#define CFG_GAIN_SERIAL_CFG1_START_ADDR 0x0110
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#define SW_GAIN_CFG1_START_OFFSET 0
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#define SW_GAIN_CFG1_START_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_STDY_RX_DLY_ADDR 0x0118
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#define SW_STDY_RX_DLY_OFFSET 0
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#define SW_STDY_RX_DLY_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_STDY_TX_DLY_ADDR 0x011C
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#define SW_STDY_TX_DLY_OFFSET 0
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#define SW_STDY_TX_DLY_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_GAIN_ADJ_TIME_ADDR 0x0120
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#define SW_GAIN_ADJ_TIME_OFFSET 0
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#define SW_GAIN_ADJ_TIME_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_AGC_SWCFG_EN_ADDR 0x0128
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#define AGC_BYPASS_MODE_OFFSET 31
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#define AGC_BYPASS_MODE_MASK 0x80000000
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#define SW_FAKE_LIC_EN_OFFSET 2
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#define SW_FAKE_LIC_EN_MASK 0x00000004
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#define SW_AR1540_EN_OFFSET 1
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#define SW_AR1540_EN_MASK 0x00000002
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#define SW_GAIN_CFG_EN_OFFSET 0
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#define SW_GAIN_CFG_EN_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_ANA_TX_START_CFG_ADDR 0x012C
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#define SW_TX_START_CFG_DATA_OFFSET 0
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#define SW_TX_START_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_END_CFG_ADDR 0x0130
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#define SW_TX_END_CFG_DATA_OFFSET 0
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#define SW_TX_END_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_START_CFG_ADDR 0x0134
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#define SW_RX_START_CFG_DATA_OFFSET 0
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#define SW_RX_START_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_END_CFG_ADDR 0x0138
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#define SW_RX_END_CFG_DATA_OFFSET 0
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#define SW_RX_END_CFG_DATA_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_START_EXT_0_ADDR 0x013C
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#define SW_TX_START_EXT_CTRL_0_OFFSET 0
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#define SW_TX_START_EXT_CTRL_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_START_EXT_1_ADDR 0x0140
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#define SW_TX_START_EXT_CTRL_1_OFFSET 0
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#define SW_TX_START_EXT_CTRL_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_TX_START_EXT_2_ADDR 0x0144
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#define SW_TX_START_EXT_CTRL_2_OFFSET 0
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#define SW_TX_START_EXT_CTRL_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_START_EXT_0_ADDR 0x0148
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#define SW_RX_START_EXT_CTRL_0_OFFSET 0
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#define SW_RX_START_EXT_CTRL_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_START_EXT_1_ADDR 0x014C
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#define SW_RX_START_EXT_CTRL_1_OFFSET 0
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#define SW_RX_START_EXT_CTRL_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_RX_START_EXT_2_ADDR 0x0150
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#define SW_RX_START_EXT_CTRL_2_OFFSET 0
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#define SW_RX_START_EXT_CTRL_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_IDLE_EXT_0_ADDR 0x0154
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#define SW_IDLE_EXT_CTRL_0_OFFSET 0
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#define SW_IDLE_EXT_CTRL_0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_IDLE_EXT_1_ADDR 0x0158
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#define SW_IDLE_EXT_CTRL_1_OFFSET 0
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#define SW_IDLE_EXT_CTRL_1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_IDLE_EXT_2_ADDR 0x015C
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#define SW_IDLE_EXT_CTRL_2_OFFSET 0
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#define SW_IDLE_EXT_CTRL_2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_ANA_SPARE_IO_ADDR 0x0190
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#define SW_RX_END_SPARE_IO_OFFSET 24
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#define SW_RX_END_SPARE_IO_MASK 0xFF000000
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#define SW_RX_START_SPARE_IO_OFFSET 16
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#define SW_RX_START_SPARE_IO_MASK 0x00FF0000
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#define SW_TX_END_SPARE_IO_OFFSET 8
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#define SW_TX_END_SPARE_IO_MASK 0x0000FF00
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#define SW_TX_START_SPARE_IO_OFFSET 0
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#define SW_TX_START_SPARE_IO_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_DFE_SPARE0_ADDR 0x0200
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#define SW_DFE_SPARE0_OFFSET 0
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#define SW_DFE_SPARE0_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_DFE_SPARE1_ADDR 0x0204
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#define SW_DFE_SPARE1_OFFSET 0
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#define SW_DFE_SPARE1_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_DFE_SPARE2_ADDR 0x0208
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#define SW_DFE_SPARE2_OFFSET 0
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#define SW_DFE_SPARE2_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_DFE_SPARE3_ADDR 0x020C
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#define SW_DFE_SPARE3_OFFSET 0
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#define SW_DFE_SPARE3_MASK 0xFFFFFFFF
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//-----------------------------------
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#define CFG_BB_DC_BLK_STEP_ADDR 0x0300
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#define SW_DC_BLK_ALPHA_STEP3_OFFSET 16
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#define SW_DC_BLK_ALPHA_STEP3_MASK 0x00FF0000
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#define SW_DC_BLK_ALPHA_STEP2_OFFSET 8
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#define SW_DC_BLK_ALPHA_STEP2_MASK 0x0000FF00
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#define SW_DC_BLK_ALPHA_STEP1_OFFSET 0
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#define SW_DC_BLK_ALPHA_STEP1_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_DC_BLK_STAGE_DLY_ADDR 0x0304
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#define SW_DC_BLK_BYPASS_OFFSET 16
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#define SW_DC_BLK_BYPASS_MASK 0x00010000
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#define SW_DC_BLK_STAGE2_DLY_OFFSET 8
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#define SW_DC_BLK_STAGE2_DLY_MASK 0x0000FF00
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#define SW_DC_BLK_STAGE1_DLY_OFFSET 0
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#define SW_DC_BLK_STAGE1_DLY_MASK 0x000000FF
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//-----------------------------------
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#define CFG_BB_DC_TH_CFG_ADDR 0x0308
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#define SW_DC_LARGE_TH_OFFSET 0
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#define SW_DC_LARGE_TH_MASK 0x000003FF
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//-----------------------------------
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#define CFG_BB_ANF_CFG_ADDR 0x0310
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#define SW_PHY_PKT_SEL_OFFSET 28
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#define SW_PHY_PKT_SEL_MASK 0x30000000
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#define SW_ALPHA_CNT_OFFSET 19
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#define SW_ALPHA_CNT_MASK 0x0FF80000
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#define SW_ALPHA_OUT_CLR_OFFSET 18
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#define SW_ALPHA_OUT_CLR_MASK 0x00040000
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#define SW_ANF_UNLOCK_THR_SEL_OFFSET 15
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#define SW_ANF_UNLOCK_THR_SEL_MASK 0x00038000
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#define SW_ANF_LOCK_THR_SEL_OFFSET 12
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#define SW_ANF_LOCK_THR_SEL_MASK 0x00007000
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#define SW_ANF_LAMD_SEL_OFFSET 9
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#define SW_ANF_LAMD_SEL_MASK 0x00000E00
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#define SW_ANF_MIU_LOW_SEL_OFFSET 6
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#define SW_ANF_MIU_LOW_SEL_MASK 0x000001C0
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#define SW_ANF_MIU_HIGH_SEL_OFFSET 3
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#define SW_ANF_MIU_HIGH_SEL_MASK 0x00000038
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#define SW_MONIT_DEC4_OFFSET 2
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#define SW_MONIT_DEC4_MASK 0x00000004
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#define SW_IS_ANF2_MONITOR_OFFSET 1
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#define SW_IS_ANF2_MONITOR_MASK 0x00000002
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#define SW_IS_ANF1_MONITOR_OFFSET 0
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#define SW_IS_ANF1_MONITOR_MASK 0x00000001
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//-----------------------------------
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#define CFG_BB_ANF_1_ALPHA_BETA_ADDR 0x0314
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#define SW_ANF_OPTION1_OFFSET 30
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#define SW_ANF_OPTION1_MASK 0xC0000000
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#define SW_ANF1_MAX_LSHIFT_OFFSET 28
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#define SW_ANF1_MAX_LSHIFT_MASK 0x30000000
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#define SW_ANF_BETA_SEL1_OFFSET 16
|
|
#define SW_ANF_BETA_SEL1_MASK 0x00070000
|
|
#define SW_ANF_ALPHA1_OFFSET 0
|
|
#define SW_ANF_ALPHA1_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ANF_2_ALPHA_BETA_ADDR 0x0318
|
|
#define SW_ANF_OPTION2_OFFSET 30
|
|
#define SW_ANF_OPTION2_MASK 0xC0000000
|
|
#define SW_ANF2_MAX_LSHIFT_OFFSET 28
|
|
#define SW_ANF2_MAX_LSHIFT_MASK 0x30000000
|
|
#define SW_ANF_BETA_SEL2_OFFSET 16
|
|
#define SW_ANF_BETA_SEL2_MASK 0x00070000
|
|
#define SW_ANF_ALPHA2_OFFSET 0
|
|
#define SW_ANF_ALPHA2_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ANF_1_ALPHA_OUT_ADDR 0x031C
|
|
#define SW_ANF1_CONVGC_CNT_OFFSET 19
|
|
#define SW_ANF1_CONVGC_CNT_MASK 0xFFF80000
|
|
#define SW_ANF1_ISCONVERGE_OFFSET 16
|
|
#define SW_ANF1_ISCONVERGE_MASK 0x00010000
|
|
#define SW_ANF1_ALPHA_OUT_OFFSET 0
|
|
#define SW_ANF1_ALPHA_OUT_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ANF_2_ALPHA_OUT_ADDR 0x0320
|
|
#define SW_ANF2_CONVGC_CNT_OFFSET 19
|
|
#define SW_ANF2_CONVGC_CNT_MASK 0xFFF80000
|
|
#define SW_ANF2_ISCONVERGE_OFFSET 16
|
|
#define SW_ANF2_ISCONVERGE_MASK 0x00010000
|
|
#define SW_ANF2_ALPHA_OUT_OFFSET 0
|
|
#define SW_ANF2_ALPHA_OUT_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ANF_OUT_PWR_CFG_ADDR 0x0324
|
|
#define SW_ANF1_LSHIFT_OFFSET 30
|
|
#define SW_ANF1_LSHIFT_MASK 0xC0000000
|
|
#define SW_ANF2_LSHIFT_OFFSET 28
|
|
#define SW_ANF2_LSHIFT_MASK 0x30000000
|
|
#define SW_ANF1_PWR_THR_OFFSET 13
|
|
#define SW_ANF1_PWR_THR_MASK 0x03FFE000
|
|
#define SW_ANF2_PWR_THR_OFFSET 0
|
|
#define SW_ANF2_PWR_THR_MASK 0x00001FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FNF_OUT_PWR_CFG_ADDR 0x0328
|
|
#define SW_FNF1_LSHIFT_OFFSET 30
|
|
#define SW_FNF1_LSHIFT_MASK 0xC0000000
|
|
#define SW_FNF2_LSHIFT_OFFSET 28
|
|
#define SW_FNF2_LSHIFT_MASK 0x30000000
|
|
#define SW_FNF1_PWR_THR_OFFSET 13
|
|
#define SW_FNF1_PWR_THR_MASK 0x03FFE000
|
|
#define SW_FNF2_PWR_THR_OFFSET 0
|
|
#define SW_FNF2_PWR_THR_MASK 0x00001FFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FNF1_CFG_ADDR 0x032C
|
|
#define SW_FNF1_OPTION_OFFSET 31
|
|
#define SW_FNF1_OPTION_MASK 0x80000000
|
|
#define SW_FNF1_MAX_LSHIFT_OFFSET 29
|
|
#define SW_FNF1_MAX_LSHIFT_MASK 0x60000000
|
|
#define SW_FNF1_BETA_SEL_OFFSET 16
|
|
#define SW_FNF1_BETA_SEL_MASK 0x00070000
|
|
#define SW_FNF1_ALPHA_OFFSET 0
|
|
#define SW_FNF1_ALPHA_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FNF2_CFG_ADDR 0x0330
|
|
#define SW_FNF2_OPTION_OFFSET 31
|
|
#define SW_FNF2_OPTION_MASK 0x80000000
|
|
#define SW_FNF2_MAX_LSHIFT_OFFSET 29
|
|
#define SW_FNF2_MAX_LSHIFT_MASK 0x60000000
|
|
#define SW_FNF2_BETA_SEL_OFFSET 16
|
|
#define SW_FNF2_BETA_SEL_MASK 0x00070000
|
|
#define SW_FNF2_ALPHA_OFFSET 0
|
|
#define SW_FNF2_ALPHA_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ANF_0_FSK_ADDR 0x0334
|
|
#define SW_ANF_FSK_START0_OFFSET 31
|
|
#define SW_ANF_FSK_START0_MASK 0x80000000
|
|
#define SW_ANF_FSK_DONE0_OFFSET 30
|
|
#define SW_ANF_FSK_DONE0_MASK 0x40000000
|
|
#define SW_ANF_FSK_OUT0_OFFSET 0
|
|
#define SW_ANF_FSK_OUT0_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ANF_1_FSK_ADDR 0x0338
|
|
#define SW_ANF_FSK_START1_OFFSET 31
|
|
#define SW_ANF_FSK_START1_MASK 0x80000000
|
|
#define SW_ANF_FSK_DONE1_OFFSET 30
|
|
#define SW_ANF_FSK_DONE1_MASK 0x40000000
|
|
#define SW_ANF_FSK_OUT1_OFFSET 0
|
|
#define SW_ANF_FSK_OUT1_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FNF_0_FSK_ADDR 0x033C
|
|
#define SW_FNF_FSK_START0_OFFSET 31
|
|
#define SW_FNF_FSK_START0_MASK 0x80000000
|
|
#define SW_FNF_FSK_DONE0_OFFSET 30
|
|
#define SW_FNF_FSK_DONE0_MASK 0x40000000
|
|
#define SW_FNF_FSK_OUT0_OFFSET 0
|
|
#define SW_FNF_FSK_OUT0_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FNF_1_FSK_ADDR 0x0340
|
|
#define SW_FNF_FSK_START1_OFFSET 31
|
|
#define SW_FNF_FSK_START1_MASK 0x80000000
|
|
#define SW_FNF_FSK_DONE1_OFFSET 30
|
|
#define SW_FNF_FSK_DONE1_MASK 0x40000000
|
|
#define SW_FNF_FSK_OUT1_OFFSET 0
|
|
#define SW_FNF_FSK_OUT1_MASK 0x000FFFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_FSK_MODE_EN_ADDR 0x0344
|
|
#define SW_FSK_DELAY_OFFSET 1
|
|
#define SW_FSK_DELAY_MASK 0x00003FFE
|
|
#define SW_FSK_RX_EN_OFFSET 0
|
|
#define SW_FSK_RX_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SADC_EXT_CFG_ADDR 0x0348
|
|
#define SW_SADC_ANF_EN_OFFSET 31
|
|
#define SW_SADC_ANF_EN_MASK 0x80000000
|
|
#define SW_SADC_ANF_OUT_SEL_OFFSET 30
|
|
#define SW_SADC_ANF_OUT_SEL_MASK 0x40000000
|
|
#define SW_SADC_VLD_DLY_OFFSET 26
|
|
#define SW_SADC_VLD_DLY_MASK 0x1C000000
|
|
#define SW_SADC_HIGH_THRD_OFFSET 16
|
|
#define SW_SADC_HIGH_THRD_MASK 0x03FF0000
|
|
#define SW_SADC_LOW_THRD_OFFSET 0
|
|
#define SW_SADC_LOW_THRD_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_LOOPBACK_TEST_CFG_ADDR 0x034C
|
|
#define SW_LOOPBACK_EN_OFFSET 31
|
|
#define SW_LOOPBACK_EN_MASK 0x80000000
|
|
#define SW_LOOP_FFT_TRIG_EN_OFFSET 30
|
|
#define SW_LOOP_FFT_TRIG_EN_MASK 0x40000000
|
|
#define SW_LOOP_BACK_SHIFT_EN_OFFSET 29
|
|
#define SW_LOOP_BACK_SHIFT_EN_MASK 0x20000000
|
|
#define LOOP_FFT_DONE_OFFSET 8
|
|
#define LOOP_FFT_DONE_MASK 0x00000100
|
|
#define SW_LOOP_FFT_START_OFFSET 4
|
|
#define SW_LOOP_FFT_START_MASK 0x00000010
|
|
#define SW_LOOP_FFT_CYCLE_OFFSET 0
|
|
#define SW_LOOP_FFT_CYCLE_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_SPUR_DET_OUT_ADDR 0x0350
|
|
#define SW_SPUR2_OUT_AVG_OFFSET 20
|
|
#define SW_SPUR2_OUT_AVG_MASK 0xFFF00000
|
|
#define SW_SPUR1_OUT_AVG_OFFSET 8
|
|
#define SW_SPUR1_OUT_AVG_MASK 0x000FFF00
|
|
#define SW_AGC_GAIN_OUT_OFFSET 0
|
|
#define SW_AGC_GAIN_OUT_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_TONE_0_CFG_ADDR 0x0400
|
|
#define SW_TONE_CFG_EN_OFFSET 31
|
|
#define SW_TONE_CFG_EN_MASK 0x80000000
|
|
#define SW_TONE_1_CFG_NUM_OFFSET 12
|
|
#define SW_TONE_1_CFG_NUM_MASK 0x003FF000
|
|
#define SW_TONE_0_CFG_NUM_OFFSET 0
|
|
#define SW_TONE_0_CFG_NUM_MASK 0x000003FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_TX_TONE_1_CFG_ADDR 0x0404
|
|
#define SW_TONE_DC_OFFSET_OFFSET 8
|
|
#define SW_TONE_DC_OFFSET_MASK 0x0003FF00
|
|
#define SW_TONE_1_ATTEN_OFFSET 3
|
|
#define SW_TONE_1_ATTEN_MASK 0x00000038
|
|
#define SW_TONE_0_ATTEN_OFFSET 0
|
|
#define SW_TONE_0_ATTEN_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DFE_OPTION_0_ADDR 0x0408
|
|
#define SW_CCA_OVR_OFFSET 24
|
|
#define SW_CCA_OVR_MASK 0x01000000
|
|
#define SW_CCA_OVR_EN_OFFSET 23
|
|
#define SW_CCA_OVR_EN_MASK 0x00800000
|
|
#define SW_DAC_DATA_OVR_OFFSET 13
|
|
#define SW_DAC_DATA_OVR_MASK 0x007FE000
|
|
#define SW_DAC_DATA_OVR_EN_OFFSET 12
|
|
#define SW_DAC_DATA_OVR_EN_MASK 0x00001000
|
|
#define SW_ENLIC_C_OVR_OFFSET 10
|
|
#define SW_ENLIC_C_OVR_MASK 0x00000C00
|
|
#define SW_ENLIC_C_OVR_EN_OFFSET 9
|
|
#define SW_ENLIC_C_OVR_EN_MASK 0x00000200
|
|
#define SW_ENLIC_B_OVR_OFFSET 7
|
|
#define SW_ENLIC_B_OVR_MASK 0x00000180
|
|
#define SW_ENLIC_B_OVR_EN_OFFSET 6
|
|
#define SW_ENLIC_B_OVR_EN_MASK 0x00000040
|
|
#define SW_ENLIC_A_OVR_OFFSET 4
|
|
#define SW_ENLIC_A_OVR_MASK 0x00000030
|
|
#define SW_ENLIC_A_OVR_EN_OFFSET 3
|
|
#define SW_ENLIC_A_OVR_EN_MASK 0x00000008
|
|
#define SW_MAC_TXRX_OVR_OFFSET 1
|
|
#define SW_MAC_TXRX_OVR_MASK 0x00000006
|
|
#define SW_MAC_TXRX_OVR_EN_OFFSET 0
|
|
#define SW_MAC_TXRX_OVR_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DFE_OPTION_1_ADDR 0x040C
|
|
#define SW_GLNA_OVR_OFFSET 10
|
|
#define SW_GLNA_OVR_MASK 0x00001C00
|
|
#define SW_GLNA_OVR_EN_OFFSET 9
|
|
#define SW_GLNA_OVR_EN_MASK 0x00000200
|
|
#define SW_GAIN_TABLE_OVR_OFFSET 8
|
|
#define SW_GAIN_TABLE_OVR_MASK 0x00000100
|
|
#define SW_GAIN_TABLE_OVR_EN_OFFSET 7
|
|
#define SW_GAIN_TABLE_OVR_EN_MASK 0x00000080
|
|
#define SW_RX_RATE_MODE_OVR_OFFSET 4
|
|
#define SW_RX_RATE_MODE_OVR_MASK 0x00000070
|
|
#define SW_RX_RATE_MODE_OVR_EN_OFFSET 3
|
|
#define SW_RX_RATE_MODE_OVR_EN_MASK 0x00000008
|
|
#define SW_TX_RATE_MODE_OVR_OFFSET 1
|
|
#define SW_TX_RATE_MODE_OVR_MASK 0x00000006
|
|
#define SW_TX_RATE_MODE_OVR_EN_OFFSET 0
|
|
#define SW_TX_RATE_MODE_OVR_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_LIC_FLAG_CFG_ADDR 0x0410
|
|
#define LIC_OVR_STRESS_STATUS_OFFSET 31
|
|
#define LIC_OVR_STRESS_STATUS_MASK 0x80000000
|
|
#define SW_LIC_FLAG_INV_OFFSET 12
|
|
#define SW_LIC_FLAG_INV_MASK 0x00001000
|
|
#define SW_LIC_FLAG_CNT_TH_OFFSET 5
|
|
#define SW_LIC_FLAG_CNT_TH_MASK 0x00000FE0
|
|
#define SW_LIC_INT_LEVEL_OFFSET 4
|
|
#define SW_LIC_INT_LEVEL_MASK 0x00000010
|
|
#define SW_LIC_INT_EDGE_OFFSET 3
|
|
#define SW_LIC_INT_EDGE_MASK 0x00000008
|
|
#define SW_LIC_INT_NEG_OFFSET 2
|
|
#define SW_LIC_INT_NEG_MASK 0x00000004
|
|
#define SW_LIC_INT_POS_OFFSET 1
|
|
#define SW_LIC_INT_POS_MASK 0x00000002
|
|
#define SW_LIC_FLAG_INT_EN_OFFSET 0
|
|
#define SW_LIC_FLAG_INT_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_DFE_CFG_0_ADDR 0x0414
|
|
#define SW_DIG_LOOPBACK_EN_OFFSET 2
|
|
#define SW_DIG_LOOPBACK_EN_MASK 0x00000004
|
|
#define SW_RX_PHASE_CHG_RESTART_EN_OFFSET 1
|
|
#define SW_RX_PHASE_CHG_RESTART_EN_MASK 0x00000002
|
|
#define SW_TX_PHASE_CHG_RESTART_EN_OFFSET 0
|
|
#define SW_TX_PHASE_CHG_RESTART_EN_MASK 0x00000001
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ENLIC_TBL_0_ADDR 0x041C
|
|
#define SW_CFG_PHASE_EN_OFFSET 31
|
|
#define SW_CFG_PHASE_EN_MASK 0x80000000
|
|
#define SW_IDLE_PHASE_TBL_OFFSET 24
|
|
#define SW_IDLE_PHASE_TBL_MASK 0x3F000000
|
|
#define SW_TX_PHASE_TBL_3_OFFSET 18
|
|
#define SW_TX_PHASE_TBL_3_MASK 0x00FC0000
|
|
#define SW_TX_PHASE_TBL_2_OFFSET 12
|
|
#define SW_TX_PHASE_TBL_2_MASK 0x0003F000
|
|
#define SW_TX_PHASE_TBL_1_OFFSET 6
|
|
#define SW_TX_PHASE_TBL_1_MASK 0x00000FC0
|
|
#define SW_TX_PHASE_TBL_0_OFFSET 0
|
|
#define SW_TX_PHASE_TBL_0_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ENLIC_TBL_1_ADDR 0x0420
|
|
#define SW_RX_PHASE_TBL_3_OFFSET 18
|
|
#define SW_RX_PHASE_TBL_3_MASK 0x00FC0000
|
|
#define SW_RX_PHASE_TBL_2_OFFSET 12
|
|
#define SW_RX_PHASE_TBL_2_MASK 0x0003F000
|
|
#define SW_RX_PHASE_TBL_1_OFFSET 6
|
|
#define SW_RX_PHASE_TBL_1_MASK 0x00000FC0
|
|
#define SW_RX_PHASE_TBL_0_OFFSET 0
|
|
#define SW_RX_PHASE_TBL_0_MASK 0x0000003F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_ADC_CNT_DBG_ADDR 0x0480
|
|
#define EOC_SADC_OFFSET 12
|
|
#define EOC_SADC_MASK 0x00007000
|
|
#define TIMEOUT_SADC_OFFSET 8
|
|
#define TIMEOUT_SADC_MASK 0x00000700
|
|
#define EOC_ADC_OFFSET 4
|
|
#define EOC_ADC_MASK 0x00000070
|
|
#define TIMEOUT_ADC_OFFSET 0
|
|
#define TIMEOUT_ADC_MASK 0x00000007
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_IMPULSE_CANCEL_CFG_ADDR 0x0484
|
|
#define SW_IMPULSE_CANCEL_BLANK_THRES_OFFSET 22
|
|
#define SW_IMPULSE_CANCEL_BLANK_THRES_MASK 0xFFC00000
|
|
#define SW_IMPULSE_CANCEL_CLIP_THRES_OFFSET 12
|
|
#define SW_IMPULSE_CANCEL_CLIP_THRES_MASK 0x003FF000
|
|
#define SW_IMPULSE_CANCEL_MODE_OFFSET 10
|
|
#define SW_IMPULSE_CANCEL_MODE_MASK 0x00000C00
|
|
#define SW_IMPULSE_CANCEL_SEG_LEN_OFFSET 8
|
|
#define SW_IMPULSE_CANCEL_SEG_LEN_MASK 0x00000300
|
|
#define SW_IMPULSE_CANCEL_CLIP_RATIO_OFFSET 4
|
|
#define SW_IMPULSE_CANCEL_CLIP_RATIO_MASK 0x000000F0
|
|
#define SW_IMPULSE_CANCEL_BLANK_RATIO_OFFSET 0
|
|
#define SW_IMPULSE_CANCEL_BLANK_RATIO_MASK 0x0000000F
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_PPM_CFG2_ADDR 0x0488
|
|
#define SW_PPM_FAKE_GI_LEN_OFFSET 22
|
|
#define SW_PPM_FAKE_GI_LEN_MASK 0xFFC00000
|
|
#define SW_PPM_XR_FILTER_OPT_OFFSET 21
|
|
#define SW_PPM_XR_FILTER_OPT_MASK 0x00200000
|
|
#define SW_NN_PPM_EN_OFFSET 20
|
|
#define SW_NN_PPM_EN_MASK 0x00100000
|
|
#define SW_TX_PPM_BYPASS_OFFSET 19
|
|
#define SW_TX_PPM_BYPASS_MASK 0x00080000
|
|
#define SW_RX_PPM_BYPASS_OFFSET 18
|
|
#define SW_RX_PPM_BYPASS_MASK 0x00040000
|
|
#define SW_TX_LARGE_PPM_EN_OFFSET 17
|
|
#define SW_TX_LARGE_PPM_EN_MASK 0x00020000
|
|
#define SW_RX_LARGE_PPM_EN_OFFSET 16
|
|
#define SW_RX_LARGE_PPM_EN_MASK 0x00010000
|
|
#define SW_TX_PPM_MSB_OFFSET 8
|
|
#define SW_TX_PPM_MSB_MASK 0x0000FF00
|
|
#define SW_RX_PPM_MSB_OFFSET 0
|
|
#define SW_RX_PPM_MSB_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_HPF_CFG_ADDR 0x048c
|
|
#define SW_BB_HPF_BYPASS_OFFSET 31
|
|
#define SW_BB_HPF_BYPASS_MASK 0x80000000
|
|
#define SW_BB_HPF_ALPHA_OFFSET 0
|
|
#define SW_BB_HPF_ALPHA_MASK 0x000000FF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NN_PPM_CFG0_ADDR 0x0490
|
|
#define SW_RX_NN_PHASE_ADJ_VAL0_OFFSET 16
|
|
#define SW_RX_NN_PHASE_ADJ_VAL0_MASK 0xFFFF0000
|
|
#define SW_RX_NN_PPM0_OFFSET 0
|
|
#define SW_RX_NN_PPM0_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NN_PPM_CFG1_ADDR 0x0494
|
|
#define SW_RX_NN_PHASE_ADJ_VAL1_OFFSET 16
|
|
#define SW_RX_NN_PHASE_ADJ_VAL1_MASK 0xFFFF0000
|
|
#define SW_RX_NN_PPM1_OFFSET 0
|
|
#define SW_RX_NN_PPM1_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NN_PPM_CFG2_ADDR 0x0498
|
|
#define SW_RX_NN_PHASE_ADJ_VAL2_OFFSET 16
|
|
#define SW_RX_NN_PHASE_ADJ_VAL2_MASK 0xFFFF0000
|
|
#define SW_RX_NN_PPM2_OFFSET 0
|
|
#define SW_RX_NN_PPM2_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NN_PPM_CFG3_ADDR 0x049c
|
|
#define SW_RX_NN_PHASE_ADJ_VAL3_OFFSET 16
|
|
#define SW_RX_NN_PHASE_ADJ_VAL3_MASK 0xFFFF0000
|
|
#define SW_RX_NN_PPM3_OFFSET 0
|
|
#define SW_RX_NN_PPM3_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NN_PPM_CFG4_ADDR 0x04a0
|
|
#define SW_RX_NN_PHASE_ADJ_VAL4_OFFSET 16
|
|
#define SW_RX_NN_PHASE_ADJ_VAL4_MASK 0xFFFF0000
|
|
#define SW_RX_NN_PPM4_OFFSET 0
|
|
#define SW_RX_NN_PPM4_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NN_PPM_CFG5_ADDR 0x04a4
|
|
#define SW_RX_NN_PHASE_ADJ_VAL5_OFFSET 16
|
|
#define SW_RX_NN_PHASE_ADJ_VAL5_MASK 0xFFFF0000
|
|
#define SW_RX_NN_PPM5_OFFSET 0
|
|
#define SW_RX_NN_PPM5_MASK 0x0000FFFF
|
|
|
|
//-----------------------------------
|
|
#define CFG_BB_NN_PPM_CFG6_ADDR 0x04a8
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#define SW_RX_NN_PHASE_ADJ_VAL6_OFFSET 16
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#define SW_RX_NN_PHASE_ADJ_VAL6_MASK 0xFFFF0000
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#define SW_RX_NN_PPM6_OFFSET 0
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#define SW_RX_NN_PPM6_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_NN_PPM_CFG7_ADDR 0x04ac
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#define SW_RX_NN_PHASE_ADJ_VAL7_OFFSET 16
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#define SW_RX_NN_PHASE_ADJ_VAL7_MASK 0xFFFF0000
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#define SW_RX_NN_PPM7_OFFSET 0
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#define SW_RX_NN_PPM7_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_RX_PPM_PHASE_ADJ_CFG_ADDR 0x04b0
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#define SW_RX_PPM_PHASE_ADJ_EN_OFFSET 18
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#define SW_RX_PPM_PHASE_ADJ_EN_MASK 0x00040000
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#define SW_RX_PPM_PHASE_ADJ_SW_FORCE_OFFSET 17
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#define SW_RX_PPM_PHASE_ADJ_SW_FORCE_MASK 0x00020000
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#define SW_RX_PPM_PHASE_ADJ_START_OFFSET 16
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#define SW_RX_PPM_PHASE_ADJ_START_MASK 0x00010000
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#define SW_RX_PPM_PHASE_ADJ_VAL_OFFSET 0
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#define SW_RX_PPM_PHASE_ADJ_VAL_MASK 0x0000FFFF
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//-----------------------------------
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#define CFG_BB_PPM_FIFO_STATUS_ADDR 0x04b4
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#define SW_RX_PPM_FIFO_FULL_CNT_OFFSET 24
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#define SW_RX_PPM_FIFO_FULL_CNT_MASK 0xFF000000
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#define SW_RX_PPM_FIFO_EMPTY_CNT_OFFSET 16
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#define SW_RX_PPM_FIFO_EMPTY_CNT_MASK 0x00FF0000
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#define SW_TX_PPM_FIFO_FULL_CNT_OFFSET 8
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#define SW_TX_PPM_FIFO_FULL_CNT_MASK 0x0000FF00
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#define SW_TX_PPM_FIFO_EMPTY_CNT_OFFSET 0
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#define SW_TX_PPM_FIFO_EMPTY_CNT_MASK 0x000000FF
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//HW module read/write macro
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#define PHY_DFE_READ_REG(addr) SOC_READ_REG(PHY_DFE_BASEADDR + addr)
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#define PHY_DFE_WRITE_REG(addr,value) SOC_WRITE_REG(PHY_DFE_BASEADDR + addr,value)
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