91 lines
2.7 KiB
C
Executable File
91 lines
2.7 KiB
C
Executable File
/****************************************************************************
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Copyright(c) 2019 by Aerospace C.Power (Chongqing) Microelectronics. ALL RIGHTS RESERVED.
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This Information is proprietary to Aerospace C.Power (Chongqing) Microelectronics and MAY NOT
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be copied by any method or incorporated into another program without
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the express written consent of Aerospace C.Power. This Information or any portion
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thereof remains the property of Aerospace C.Power. The Information contained herein
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is believed to be accurate and Aerospace C.Power assumes no responsibility or
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liability for its use in any way and conveys no license or title under
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any patent or copyright and makes no representation or warranty that this
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Information is free from patent or copyright infringement.
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****************************************************************************/
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#include "hw_reg_api.h"
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#include "iot_config.h"
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#include "phy_bb.h"
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#include "phy_dfe_reg.h"
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#include "phy_rxtd_reg.h"
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#include "granite_reg.h"
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#include "hw_tonemask.h"
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#include "iot_io.h"
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#include "iot_errno_api.h"
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#include "mac_sys_reg.h"
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#include "os_mem.h"
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#include "hw_phy_api.h"
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#include "phy_ana.h"
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#include "phy_phase.h"
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#include "iot_share_task.h"
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#include "math_log10.h"
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#include "phy_data.h"
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#include "hw_phy_api.h"
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#include "phy_perf.h"
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#include "math_log10.h"
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#include "phy_dump_hw.h"
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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#include "phy_tools.h"
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#include "phy_ada_dump.h"
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#endif
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void phy_fft_dump_prepare()
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{
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#if HW_PLATFORM >= HW_PLATFORM_FPGA
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uint32_t tmp = 0;
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uint32_t fft_loop = 1;
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/* config det tone */
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phy_rxfd_rate0_det(0, 1535);
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phy_rxfd_rate1_det(0, 1535);
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/* tone enable */
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phy_dfe_tone_cfg(1,0,0);
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/* force inte rx state */
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phy_txrx_ovr_set(1,1);
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/* disable packet detect timeout */
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phy_pkt_time_out_disable(true);
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/* bypass dc blocker */
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tmp = PHY_DFE_READ_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR);
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REG_FIELD_SET(SW_DC_BLK_BYPASS, tmp, 1);
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PHY_DFE_WRITE_REG(CFG_BB_DC_BLK_STAGE_DLY_ADDR, tmp);
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/* disable adj req and sat */
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phy_agc_sat_adj_set(1,1);
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tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
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REG_FIELD_SET(SW_LOOPBACK_EN, tmp, 1);
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PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
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/* en adc and rx, disable dac and tx */
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phy_ana_tx_en(false);
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phy_ana_rx_en(true);
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phy_ana_enlic_en(PHY_ENLIC_TXRX_RX);
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/* trig fft */
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tmp = PHY_DFE_READ_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR);
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REG_FIELD_SET(SW_LOOP_FFT_CYCLE, tmp, fft_loop);
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REG_FIELD_SET(SW_LOOP_FFT_START, tmp, 1);
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PHY_DFE_WRITE_REG(CFG_BB_LOOPBACK_TEST_CFG_ADDR, tmp);
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#endif
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}
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void phy_increase_tgt_pwr(uint32_t spur_exist)
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{
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(void)spur_exist;
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}
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